wt., 3 sie 2021 o 08:53 Ard Biesheuvel napisał(a):
>
> On Mon, 2 Aug 2021 at 19:00, Marcin Wojtas wrote:
> >
> > Hi Ard,
> >
> > pon., 2 sie 2021 o 10:43 Ard Biesheuvel napisał(a):
> > >
> > > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote:
> > > >
> > > > On CN913x-based platforms it is poss
On Mon, 2 Aug 2021 at 19:00, Marcin Wojtas wrote:
>
> Hi Ard,
>
> pon., 2 sie 2021 o 10:43 Ard Biesheuvel napisał(a):
> >
> > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote:
> > >
> > > On CN913x-based platforms it is possible to have up to 9 PCIE
> > > root complexes. In such case it may be n
Hi Ard,
pon., 2 sie 2021 o 10:43 Ard Biesheuvel napisał(a):
>
> On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote:
> >
> > On CN913x-based platforms it is possible to have up to 9 PCIE
> > root complexes. In such case it may be necessary to configure
> > more configuration spaces with smaller bus
On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote:
>
> On CN913x-based platforms it is possible to have up to 9 PCIE
> root complexes. In such case it may be necessary to configure
> more configuration spaces with smaller bus count, so that
> to fit the memory layout constraints. For that purpose r
On CN913x-based platforms it is possible to have up to 9 PCIE
root complexes. In such case it may be necessary to configure
more configuration spaces with smaller bus count, so that
to fit the memory layout constraints. For that purpose remove
forcing ECAM base to be divisible by SIZE_256MB.
Signe
