XO 1.75 ofw_olpc.c question

2011-09-30 Thread Andrei E. Warkentin
Hi, Since OFW is resident, I thought it would be nice to try to enter into it with something like - __olpc_ofw(enter, 0, NULL, 0, NULL); I'm doing this from SVC mode. Yet this just hangs. Am I doing something that's not supposed to work by design? Is there any hardware state that I need to

MMP2 Interrupt Controller forcing IRQ

2011-09-26 Thread Andrei E. Warkentin
Hi, I have a question about the ICU controller in the XO 1.75. I was looking into porting over and extending the FIQ debugger onto the XO (which allows debugging wedged/deadlocked kernels), and was wondering if it was possible to force triggering a particular IRQ (not FIQ). It's a feature common

Re: MMP2 Interrupt Controller forcing IRQ

2011-09-26 Thread Andrei E. Warkentin
Hi Chris, Mitch, 2011/9/26 Chris Ball c...@laptop.org: Here's a transcription of an explanation Mitch just gave: It's certainly possible to route any given interrupt to either FIQ or IRQ on either core.  It is possible for an instruction to cause an interrupt/exception; that's how OFW does

Re: MMP2 Interrupt Controller forcing IRQ

2011-09-26 Thread Andrei E. Warkentin
2011/9/26 Mitch Bradley w...@firmworks.com: If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 . You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c. This uses an inter-processor communication unit.  Presumably the FIG handler would assert the interrupt

Re: MMP2 Interrupt Controller forcing IRQ

2011-09-26 Thread Andrei E. Warkentin
2011/9/26 Andrei E. Warkentin andrey.warken...@gmail.com: 2011/9/26 Mitch Bradley w...@firmworks.com: If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 . You can then clear it by writing 0x400 to APB_VIRT_BASE + 0x1d40c. This uses an inter-processor communication

Re: MMP2 Interrupt Controller forcing IRQ

2011-09-26 Thread Andrei E. Warkentin
2011/9/27 Mitch Bradley w...@firmworks.com: On 9/26/2011 4:40 PM, Andrei E. Warkentin wrote: 2011/9/26 Andrei E. Warkentinandrey.warken...@gmail.com: 2011/9/26 Mitch Bradleyw...@firmworks.com: If you write 0x400 to APB_VIRT_BASE + 0x1d008, it will assert interrupt 56 . You can then clear