I added instrumentation to track FPGA-internal state on my scope.
I first tried to have a look at the FSM state, but that's trickier
than I expected and may tell me less that I had hoped.
I then looked at the I2C bit counter (D0-D3, SDA yellow, SCL is
blue):
On 04/12/2013 12:06 PM, Khobatha Setetemela wrote:
-I have confirmed that migensim.vpi installation path is visible in
python3 sys.path
Python's sys.path has nothing to do with the VPI module installation
path. sys.path just where Python looks for Python modules. VPI modules
are something
In an attempt to filter out noise, Sebastien had reworked the
circuit by adding 100 pF capacitors parallel to the pull-ups
R25 and R28. He suggested removing them, given that they didn't
seem to have much effect on noise.
Removing them improved the rise time further but didn't affect
the overall
Using the SCL delay buffer (20 entries), I added a count of the
number of times SCL was sampled high. If that count ends up 7
I take SCL as asserted, otherwise not.
This is the code:
https://github.com/wpwrak/ming-ddc-debug/commit/a3d338cbcf361a1b5c379ae381604f02b207b731
On the scope it looks
Committed, thanks Werner!
On 04/12/2013 10:38 PM, Werner Almesberger wrote:
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the forbidden region
between Vil(max) and Vih(min).
By lowering the sample rate from once per system clock to
