Hi Sebastien,
I've simulated your code under ISim from ISE Webpack 13.4 running from
Debian Squeeze
ISim> restart
ISim> init
Simulator is doing circuit initialization process.
Finished circuit initialization process.
bar=x
bar=1
bar=1
bar=1
bar=1
[...]
ERROR: at 0 ns: Iteration limit 1 is rea
On Tuesday, November 27, 2012 12:03:49 AM William Heatley wrote:
> reading a signal is meant to affect simulation behavior.
Adding the signal to the automatic (*) sensitivity list is an expected side
effect of the read, and the problem actually originates from "bar" being in the
sensitivity list
>Anyone with a Modelsim install wants to see what it does?
"ModelSim SE PLUS 6.5, 2009.01" also goes into a loop:
# bar=x
# bar=1
# bar=1
# bar=1
and eventually ends with:
# ** Error: (vsim-3601) Iteration limit reached at time 0 ns.
If "$display("bar=%d", bar);" is removed, ModelSim does not e
Hi,
Consider the following Verilog source:
module event_test();
reg foo, bar;
always @(*) begin
$display("bar=%d", bar);
bar <= 1'b0;
if(foo)
bar <= 1'b1;
end
initial begin
foo <= 1'd1;
#1 $display("End of simulation - bar=%d
