In an attempt to filter out noise, Sebastien had reworked the
circuit by adding 100 pF capacitors parallel to the pull-ups
R25 and R28. He suggested removing them, given that they didn't
seem to have much effect on noise.
Removing them improved the rise time further but didn't affect
the overall o
I added instrumentation to track FPGA-internal state on my scope.
I first tried to have a look at the FSM state, but that's trickier
than I expected and may tell me less that I had hoped.
I then looked at the I2C bit counter (D0-D3, SDA yellow, SCL is
blue):
http://downloads.qi-hardware.com/peopl
