Rolf,
We have identified a need in certain high performance applications to
specify memory sections -> L3 -> L2 - >L1 -> specific core -> specific
CPU -> specific machine. These tend toward hybridized CUDA apps where
other sections of the CPU are involved in non-CUDA (non-GPU) functions.
In our di
I see in the sm BTL that there is the concept of memory affinity and the
potential to support multiple memory pools. I am curious if anyone is making
use of that feature? I am looking in the function sm_btl_first_time_init() in
the btl_sm.c file.
Thanks,
Rolf
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