Hi Ben,
I found the reason for system hang in BBB after link goes up. It is
caused by enabling the interrupt before it is processed creating a
continuous flow of interrupts hogging the CPU.
In rtems-libbsd we do not directly call the interrupt handler. we
create an event through interrupt trigg
Hello,
the bsp_interrupt_dispatch() is quite complicated in the beagle BSP. Is
the interrupt controller of this chip really that broken? Sane interrupt
controllers block interrupts of equal or lower priority relative to the
currently pending interrupt.
On 28/05/15 13:14, ragu nath wrote:
Hi
Hi Sebastian,
The problem is with rx interrupt. We are enabling rx interrupt before
it is processed. The rtems server task do not get an opportunity to
run.
I found this might be the logical explanation of the issue.
bsp_interrupt_dispatch() calls bsp_interrupt_server_trigger which
disables the r
It depends on the capabilities of the interrupt controller. Maybe you
have to drop the support for nested interrupts. The
bsp_interrupt_dispatch() function for a state of the art interrupt
controller looks like this (arm-gic-irq.c):
void bsp_interrupt_dispatch(void)
{
volatile gic_cpuif *cpu
I'm going to chime in since this sounds like a similar problem I've
experienced on a PIC32.
I wanted to reword what Ragunath said in my own words to see if I
understand it.
1) The RX ISR fires, vectoring the code to the ISR entry.
2) The code in the ISR disables interrupts, creates an event to be
This interrupt server task is a hack. It works for proper interrupt
controllers. You must be able to disable a single interrupt source in
the interrupt controller.
On 28/05/15 14:23, Isaac Gutekunst wrote:
I'm going to chime in since this sounds like a similar problem I've
experienced on a PIC
That explains a lot and makes a lot of sense. I was thinking about only
disabling the entire interrupt controller.
Thanks!
Isaac
On Thu, May 28, 2015 at 8:34 AM, Sebastian Huber <
sebastian.hu...@embedded-brains.de> wrote:
> This interrupt server task is a hack. It works for proper interrupt
>
This changed is now merged. Congratulations & thank you Ragunath!
On Sun, May 3, 2015 at 1:02 PM, ragu nath wrote:
> Hi All,
>
> I have attached the RTC patch for BBB. I have addressed the comments
> given for my earlier submission.
>
> I am having problems with sending patch using git send-email
Hi All,
I have to implement the cache coherency support for Cortex A7. But for A7
MPCore, unlike for A9, I am not able to find any register description for
the Snoop Control Unit from the TRM.
I need help here on how to proceed.
Additionally for A9 there is a single bit for A9 in the Auxiliary Co
Hi
I decided to attempt to build rtems-libbsd for all BSPs. I didn't
expect great results but 136 of 193 BSPs did not complete the build.
Overall, the results are surprising. No x86 or SPARC BSPs could
build rtems-libbsd. And many ARM and PowerPC BSPs had build issues
that were *NOT* running out
On i386/pc386, adding a line :
extern u_int64_t tsc_freq;
to freebsd/sys/contrib/altq/altq/altq_subr.c
gets it to build successfully. Though I wonder what its repercussions would be.
On Thu, May 28, 2015 at 8:43 PM, Joel Sherrill
wrote:
> Hi
>
> I decided to attempt to build rtems-libbsd for a
On 5/28/2015 10:30 AM, Sujay Raj wrote:
On i386/pc386, adding a line :
extern u_int64_t tsc_freq;
to freebsd/sys/contrib/altq/altq/altq_subr.c
gets it to build successfully. Though I wonder what its repercussions would be.
Does the variable have a value? I looked at it enough to think
that
On 29/05/2015 1:13 am, Joel Sherrill wrote:
>
> I decided to attempt to build rtems-libbsd for all BSPs. I didn't
> expect great results but 136 of 193 BSPs did not complete the build.
>
> Overall, the results are surprising. No x86 or SPARC BSPs could
> build rtems-libbsd. And many ARM and Power
On 5/28/2015 5:38 PM, Chris Johns wrote:
On 29/05/2015 1:13 am, Joel Sherrill wrote:
I decided to attempt to build rtems-libbsd for all BSPs. I didn't
expect great results but 136 of 193 BSPs did not complete the build.
Overall, the results are surprising. No x86 or SPARC BSPs could
build rt
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