Re: [PATCH v1 6/6] spec/aarch64: Add BSPs for real ZynqMP hardware

On 24/05/2021 22:29, Kinsey Moore wrote: +# don't compile due to toolchain issues +spconfig01: exclude +spmisc01: exclude Is this still the case? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.hu...@embedded-brains.de phone: +49-8

Re: [PATCH v1 2/6] bsps/aarch64: Invert cache line mask use

On 24/05/2021 22:29, Kinsey Moore wrote: diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 9bdbe88c92..240cfb043a 100644 --- a/bsps/aarch64/shared/cache/cache.c +++ b/bsps/aarch64/shared/cache/cache.c @@ -43,7 +43,7 @@ #define AARCH64_CACHE_L1_DATA_LINE

[PATCH v1 3/6] bsps/aarch64: Advertise cache function support

Ensure that cache functions are flagged as usable by the generic cache implementation code. --- bsps/aarch64/shared/cache/cache.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 240cfb043a..76465aeb86 1006

[PATCH v1 6/6] spec/aarch64: Add BSPs for real ZynqMP hardware

Add the BSPs for running on the UZ3EG Ultrascale+ Zynq MPSoC and alter the option defaults necessary for them to run properly using the standard BOOT.BIN configured for PetaLinux that comes in the Out-of-Box package. --- spec/build/bsps/aarch64/xilinx-zynqmp/abi.yml | 1 + .../aarch64/xilinx-zynq

[PATCH v1 4/6] bsps/a53: Increase available RAM

The default available RAM on the A53 BSP is quite small at 8MB. This bumps that to 128MB to avoid allocation failures in tmcontext01 caused by large allocations on a cache size of 16MB reported by the system registers in QEMU. --- spec/build/bsps/aarch64/a53/optramlen.yml | 2 +- 1 file changed, 1

[PATCH v1 5/6] bsps/aarch64: Add MMU driver to relax alignment

Currently, the AArch64 BSPs have a hard time running on real hardware without building the toolchain and the bsps with -mstrict-align in multiple places. Configuring the MMU on these chips allows for unaligned memory accesses for non-device memory which avoids requiring strict alignment in the tool

[PATCH v1 1/6] bsps/aarch64: Break out system registers

--- bsps/aarch64/include/bsp/aarch64-sysregs.h| 291 ++ bsps/aarch64/shared/cache/cache.c | 168 +- spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 + 3 files changed, 293 insertions(+), 167 deletions(-) create mode 100644 bsps/aarch64/include/bsp/aarch

[PATCH v1 2/6] bsps/aarch64: Invert cache line mask use

Invert usage of the cache line mask so it actually works properly. --- bsps/aarch64/shared/cache/cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/aarch64/shared/cache/cache.c b/bsps/aarch64/shared/cache/cache.c index 9bdbe88c92..240cfb043a 100644 --- a/bsps/aarch64

Minimum.exe Text Size Outliers

Hi I built all 187 BSPs overnight and saved minimum.exe. Although I think 64K is still too much code, I am using that as an initial cutoff when asking for some help in identifying why minimum.exe is surprisingly large for some BSPs. 146 stayed under 64k which leaves 41 needing some investigation o

About interrupt processing

Hi, When the CPU issues an interrupt, and when the interrupt is processed, where does it run the code from? Is there a place where the commands are written based on the interrupt number? I followed the call to _Scheduler_SMP_Allocate_processor_exact