Re: [PATCH v2 1/2] bsps: Import Xilinx support code

On 22/12/2022 19:56, Kinsey Moore wrote: This support code is necessary for many Xilinx-provided bare metal device drivers supported on ARM, AArch64, and MicroBlaze platforms. Support for all of these architectures is kept under bsps/include due to multiple architecture variants being supported

Re: [PATCH] rtems_shell_main_mmove problem

Bump On Wed, 14 Dec 2022 at 20:12, zack leung wrote: > Closes #4556 > --- > cpukit/libmisc/shell/main_mmove.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/cpukit/libmisc/shell/main_mmove.c > b/cpukit/libmisc/shell/main_mmove.c > index 38731b10a2..0029882d62 100644 >

Re: [PATCH 1/2] bsps: Import xilinx support code

On Thu, Dec 22, 2022 at 12:58 AM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 21/12/2022 21:54, Kinsey Moore wrote: > > +includes: > > +- bsps/include/xilinx_support/ > > +- bsps/include/xilinx_support/${XIL_SUPPORT_PATH}/ > > Is the xilinx_support a name from you or Xilinx?

Re: [PATCH v2 1/3] spec/build/riscv: Default rv64* BSPs to medany cmodel

On 22/12/2022 13:22, heshamelmat...@gmail.com wrote: From: Hesham Almatary Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x7000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal

[PATCH v2 3/3] RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT

From: Hesham Almatary Updates #4779 --- bsps/riscv/noel/include/bsp/riscv.h | 2 -- bsps/riscv/riscv/console/console-config.c | 10 ++ bsps/riscv/riscv/console/htif.c | 4 bsps/riscv/riscv/include/bsp/riscv.h | 2 -- bsps/riscv/riscv/irq/irq.c

[PATCH v2 1/3] spec/build/riscv: Default rv64* BSPs to medany cmodel

From: Hesham Almatary Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x7000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal programs that start at 0x8000. Further, testing now has

[PATCH v2 2/3] spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000

From: Hesham Almatary To follow other RISC-V-based OSes conventions. Delete generic BSPs that start at 0x7000 as BSPs are now medany by default. Updates #4775 --- spec/build/bsps/riscv/optrambegin.yml | 6 -- 1 file changed, 6 deletions(-) diff --git

[PATCH 18/18] adds automatic testgen examples

--- formal/promela/src/examples/draft/make.sh | 77 +++ formal/promela/src/examples/draft/parse.pml | 129 ++ .../src/examples/model_checker/spin.pml | 8 ++ formal/promela/src/examples/requirements.txt | 35 + 4 files changed, 249 insertions(+)

[PATCH 15/18] modifies 3rd party code - comment filter

--- .../comment-filter/.circleci/config.yml | 9 - .../src/modules/comment-filter/.coveragerc| 2 - .../src/src/modules/comment-filter/.gitignore | 104 --- .../modules/comment-filter/CODE-OF-CONDUCT.md | 73 - .../modules/comment-filter/CONTRIBUTING.md| 87 --

[PATCH 14/18] third party code - comment filter

forked from https://github.com/quic/comment-filter/commits/master commit 9cfb52318e5f71af56b5808e280a9b089b9abc32 --- .../comment-filter/.circleci/config.yml | 9 + .../src/modules/comment-filter/.coveragerc| 2 + .../src/src/modules/comment-filter/.gitignore | 104 +

[PATCH 13/18] modifies 3rd party code - promela parser

--- .../src/src/modules/promela_yacc/.gitignore | 20 - .../src/src/modules/promela_yacc/.travis.yml | 21 - .../src/src/modules/promela_yacc/LICENSE | 1 + .../src/src/modules/promela_yacc/MANIFEST.in | 4 - .../src/src/modules/promela_yacc/doc.md | 100 ---

[PATCH 12/18] third party code - promela parser

forked from https://github.com/johnyf/promela, commit 32d14184a50e920a92201058e4f601329be8c9c7 --- .../src/src/modules/promela_yacc/.gitignore | 20 + .../src/src/modules/promela_yacc/.travis.yml | 21 + .../src/src/modules/promela_yacc/LICENSE | 31 +

[PATCH 10/18] adds weak memory models

--- .../models/threadq/Weak-Memory/RAM.pml| 48 + .../models/threadq/Weak-Memory/SPARC-TSO.pml | 198 ++ .../threadq/Weak-Memory/memory_model.pml | 60 ++ .../models/threadq/Weak-Memory/wmemory.pml| 74 +++ 4 files changed, 380 insertions(+)

[PATCH 08/18] adds message manager model

>From 4364f65705b387697c33181cb8a9a7b772ea7f58 Mon Sep 17 00:00:00 2001 From: Andrew Butterfield Date: Wed, 21 Dec 2022 16:31:40 + Subject: [PATCH 08/18] adds message manager model --- formal/promela/models/messages/README.md | 10 + formal/promela/models/messages/STATUS.md |

[PATCH 06/18] adds event manager model

--- formal/promela/models/events/.gitignore | 1 + formal/promela/models/events/STATUS.md| 21 + .../models/events/event-mgr-model-post.h | 8 + .../models/events/event-mgr-model-pre.h | 51 ++ .../models/events/event-mgr-model-rfn.yml | 182

[PATCH 04/18] adds chains API model

--- formal/promela/models/chains/.gitignore | 1 + formal/promela/models/chains/STATUS.md| 11 + .../models/chains/chains-api-model-post.h | 3 + .../models/chains/chains-api-model-pre.h | 43 .../models/chains/chains-api-model-rfn.yml| 64 ++

[PATCH 02/18] adds barrier manager model

--- formal/promela/models/barriers/README.md | 11 + formal/promela/models/barriers/STATUS.md | 95 ++ .../models/barriers/barrier-mgr-model-post.h | 44 + .../models/barriers/barrier-mgr-model-pre.h | 51 + .../models/barriers/barrier-mgr-model-rfn.yml | 169 +++

[PATCH 01/18] adds in high-level directories and READMEs

--- formal/.gitignore | 3 ++ formal/README.md| 27 + formal/promela/.gitignore | 4 ++ formal/promela/README.md| 27 + formal/promela/models/README.md | 53 formal/promela/src/README.md| 71

[PATCH 00/18] Adds Formal Verification Material

>From 3390ccc51f46ce0a4baa60422a62530c7c3c29bd Mon Sep 17 00:00:00 2001 From: Andrew Butterfield Date: Wed, 21 Dec 2022 18:03:47 + Subject: [PATCH 00/18] Adds Formal Verification Material This patch-set adds in the Promela/SPIN models and tools developed as part of the ESA-sponsored activity

Re: [PATCH 1/3] spec/build/riscv: Default rv64* BSPs to medany cmodel

On 22/12/2022 11:42, heshamelmat...@gmail.com wrote: From: Hesham Almatary Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x7000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal

[PATCH 3/3] RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT

From: Hesham Almatary Updates #4779 --- bsps/riscv/noel/include/bsp/riscv.h | 2 -- bsps/riscv/riscv/console/console-config.c | 10 ++ bsps/riscv/riscv/console/htif.c | 4 bsps/riscv/riscv/include/bsp/riscv.h | 2 -- bsps/riscv/riscv/irq/irq.c

[PATCH 1/3] spec/build/riscv: Default rv64* BSPs to medany cmodel

From: Hesham Almatary Currently generic RISC-V BSPs (riscv/riscv) that start with rv64 and not rv64*_medany will start at 0x7000. This adds high maintenance overhead and deviates from almost all other RISC-V-based OSes and baremetal programs that start at 0x8000. Further, testing now has

[PATCH 2/3] spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000

From: Hesham Almatary To follow other RISC-V-based OSes conventions. Delete generic BSPs that start at 0x7000 as BSPs are now medany by default. Updates #4775 --- spec/build/bsps/riscv/optrambegin.yml | 6 -- 1 file changed, 6 deletions(-) diff --git

[PATCH 3/5] bsp/qoriq: Support message signaled interrupts

--- bsps/powerpc/qoriq/include/bsp/irq.h | 48 -- bsps/powerpc/qoriq/irq/irq.c | 233 +-- 2 files changed, 255 insertions(+), 26 deletions(-) diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h b/bsps/powerpc/qoriq/include/bsp/irq.h index

[PATCH 4/5] bsp/qoriq: Add qoriq_mmu_find_free_tlb1_entry()

--- bsps/powerpc/qoriq/include/bsp/mmu.h | 2 ++ bsps/powerpc/qoriq/start/mmu.c | 26 +- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/bsps/powerpc/qoriq/include/bsp/mmu.h b/bsps/powerpc/qoriq/include/bsp/mmu.h index e9aad505b5..2a69f683bc 100644

[PATCH 5/5] bsp/qoriq: Add qoriq_mmu_adjust_and_write_to_tlb1()

--- bsps/powerpc/qoriq/include/bsp/mmu.h | 10 ++ bsps/powerpc/qoriq/start/bspsmp.c| 9 ++--- bsps/powerpc/qoriq/start/mmu.c | 26 ++ 3 files changed, 38 insertions(+), 7 deletions(-) diff --git a/bsps/powerpc/qoriq/include/bsp/mmu.h

[PATCH 2/5] bsp/qoriq: Clear shared message signaled interrupts

--- bsps/powerpc/qoriq/irq/irq.c | 5 + 1 file changed, 5 insertions(+) diff --git a/bsps/powerpc/qoriq/irq/irq.c b/bsps/powerpc/qoriq/irq/irq.c index cadd503a6f..f33b7c24ae 100644 --- a/bsps/powerpc/qoriq/irq/irq.c +++ b/bsps/powerpc/qoriq/irq/irq.c @@ -545,6 +545,11 @@ void

[PATCH 1/5] bsp/qoriq: Use only pic_is_ipi()

--- bsps/powerpc/qoriq/irq/irq.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/bsps/powerpc/qoriq/irq/irq.c b/bsps/powerpc/qoriq/irq/irq.c index 2858ff7581..cadd503a6f 100644 --- a/bsps/powerpc/qoriq/irq/irq.c +++ b/bsps/powerpc/qoriq/irq/irq.c @@ -293,7

[PATCH 0/5] bsp/qoriq: Improve PCIe support

Sebastian Huber (5): bsp/qoriq: Use only pic_is_ipi() bsp/qoriq: Clear shared message signaled interrupts bsp/qoriq: Support message signaled interrupts bsp/qoriq: Add qoriq_mmu_find_free_tlb1_entry() bsp/qoriq: Add qoriq_mmu_adjust_and_write_to_tlb1()

Re: [PATCH 1/1] RSB: Mitigate too short error reports

On 12/21/22 00:06, Chris Johns wrote: On 21/12/2022 3:44 am, Frank Kuehndel wrote: From: Frank Kühndel Close #4642 --- source-builder/sb/ereport.py | 4 1 file changed, 4 insertions(+) diff --git a/source-builder/sb/ereport.py b/source-builder/sb/ereport.py index d8fb5f6..d391917