This patch adds the documentation for building and running RTEMS on the
Kendryte K210 RISC-V SoC.
The generic riscv introducion was re-arranged to list the multilib variants
then the specific
hardware targets. In addition a couple of errors were fixed for the generic
QEMU commands.
V2
On 31/3/2023 8:13 am, Kinsey Moore wrote:
> Xilinx wrote their A53 HAL with the assumption that the CPU did not
> support cache invalidation without a flush, so the flush and
> invalidation functions were combined and all range invalidations are
> promoted to flush/invalidate. The implementation
On 4/4/2023 12:55 am, Alan Cudmore wrote:
> Hi Chris,
> Sorry I should have read that and formatted my changes correctly. I submitted
> a
> v5 patch, but as I sent it, I realized that there are a couple of places where
> the RTEMS version macro can be embedded rather than hard-coding "6". I
I submitted a v4 patch for the user/bsps/bsps-riscv.rst page.
I improved the instructions for running on Renode by providing a .resc file
that would work, rather than modifying an existing script that was used to
run Linux.
This should work until I have some time to figure out why the
I have drafted my GSoC proposal and uploaded it to Google Docs. You
can leave suggestions as comments in the document.
https://docs.google.com/document/d/1dL5zl_iSYeyx6ZoOpKjy-CkLh_OvgGDJvblrPH5q6rg/edit?usp=sharing
I apologize for not giving you much time for this review.
Regards,
Utkarsh
Hi Alan,
We have a standard for the documentation source:
https://git.rtems.org/rtems-docs/tree/README.txt#n469
Please note the line length. That can be relaxed when pasting in output but we
need the written text to be within the bounds.
Thanks
Chris
On 1/4/2023 3:15 am, Alan Cudmore wrote:
This patch adds the documentation for building and running RTEMS on the
Kendryte K210 RISC-V SoC.
The generic riscv introducion was re-arranged to list the multilib variants
then the specific
hardware targets. In addition a couple of errors were fixed for the generic
QEMU commands.
V2
Hi Chris,
Sorry I should have read that and formatted my changes correctly. I
submitted a v5 patch, but as I sent it, I realized that there are a couple
of places where the RTEMS version macro can be embedded rather than
hard-coding "6". I should have taken more time and avoided flooding the
Thanks Alan for investigating this issue and following up with the
updates. It's fine to leave it for now, perhaps even report it to
Renode if we think it's a problem with their simulator or something.
On Sun, 2 Apr 2023 at 17:22, Alan Cudmore wrote:
>
> I submitted a v4 patch for the
This patch adds the documentation for building and running RTEMS on the
Kendryte K210 RISC-V SoC.
The generic riscv introducion was re-arranged to list the multilib variants
then the specific
hardware targets. In addition a couple of errors were fixed for the generic
QEMU commands.
V2
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