Re: GSoC Mentors and Open Projects

2018-01-03 Thread Denis Obrezkov
to mentor exist as a ticket. > > https://devel.rtems.org/wiki/Developer/OpenProjects > > Thanks, and Happy New Year, > Gedare > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel > -- Regards,

Re: RTEMS and Google Code-In

2017-09-22 Thread Denis Obrezkov
Oh, I have meant this project: https://www.outreachy.org/ 2017-09-22 21:13 GMT+02:00 Joel Sherrill : > > > On Fri, Sep 22, 2017 at 11:47 AM, Denis Obrezkov > wrote: > >> There is also the Outreachy project, does RTEMS participate in it? >> >> > There are cat

Re: RTEMS and Google Code-In

2017-09-22 Thread Denis Obrezkov
need to be done lots of times are good candidates. > > If you want more info, could mentor, or could recruit someone who uses > RTEMS who doesn't pop up on the list, please speak up. > > Thanks. > > --joel > > ___ > devel m

GSoC 2017 is over!

2017-09-06 Thread Denis Obrezkov
Hello all, the GSoC is over, I wanted only to ask - is it true that one of our students hasn't passed the final evaluation? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: GSoC 2017 RTEMS for HiFive1: The Final Report

2017-08-27 Thread Denis Obrezkov
2017-08-27 17:50 GMT+02:00 Gedare Bloom : > You might like to use the following link somewhere to identify your > specific contributions: > https://github.com/embeddedden/rtems-riscv/commits/hifive1?author= > embeddedden > > On Sun, Aug 27, 2017 at 10:54 AM, Denis Obrezkov >

GSoC 2017 RTEMS for HiFive1: The Final Report

2017-08-27 Thread Denis Obrezkov
The Final Report of my GSoC project is ready! https://embeddedden.blogspot.de/2017/08/gsoc-2017-results-rtems-for-hifive1.html Criticism appreciated. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman

Re: Change time_t and clock_t integer types to 64-bit?

2017-08-24 Thread Denis Obrezkov
icht ist keine geschäftliche Mitteilung im Sinne des EHUG. > > ___ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel In RISC-V time and time-compare registers are 64-bit wide, if it helps. -- Regards, Denis Obrezkov _

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
ter would > be merging it to rtems.org if it is ready now. :) > > --joel > > > On Tue, Aug 22, 2017 at 6:01 PM, Denis Obrezkov > wrote: > >> 2017-08-23 0:58 GMT+02:00 Joel Sherrill : >> >>> I would guess that's the case: >>> >>

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
./cpukit/libcsupport/include/machine/_kernel_cpuset.h > ./cpukit/libcsupport/include/machine/_kernel_param.h > ./cpukit/libnetworking/machine/_kernel_lock.h > > > On Tue, Aug 22, 2017 at 5:38 PM, Denis Obrezkov > wrote: > >> 2017-08-23 0:02 GMT+02:00 Denis Obrezkov : >> >

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
2017-08-23 0:02 GMT+02:00 Denis Obrezkov : > 2017-08-22 23:49 GMT+02:00 Joel Sherrill : > >> >> >> On Tue, Aug 22, 2017 at 4:25 PM, Denis Obrezkov >> wrote: >> >>> 2017-08-22 22:09 GMT+02:00 Joel Sherrill : >>> >>>> Sebastian, >

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
2017-08-22 23:49 GMT+02:00 Joel Sherrill : > > > On Tue, Aug 22, 2017 at 4:25 PM, Denis Obrezkov > wrote: > >> 2017-08-22 22:09 GMT+02:00 Joel Sherrill : >> >>> Sebastian, >>> >>> Did you consciously not add riscv do rtems-all.bset? Or was

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
ild. > > --joel > > On Tue, Aug 22, 2017 at 9:55 AM, Denis Obrezkov > wrote: > >> Ok, I will try today >> >> 2017-08-22 16:44 GMT+02:00 Gedare Bloom : >> >>> Denis, >>> >>> Please confirm if this works for you. >>> >>

Re: [PATCH v2 10/15] HiFive1: set up oscillators

2017-08-22 Thread Denis Obrezkov
Ok, I fixed it. 2017-08-22 3:48 GMT+02:00 Gedare Bloom : > On Mon, Aug 21, 2017 at 7:56 PM, Denis Obrezkov > wrote: > > --- > > c/src/lib/libbsp/riscv32/hifive1/include/prci.h | 9 + > > c/src/lib/libbsp/riscv32/hifive1/start/bspstart.c | 23 + >

Re: Basic RISC-V 32-bit tool chain

2017-08-22 Thread Denis Obrezkov
gt; > > ___ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

[PATCH v2 15/15] Add build support files for HiFive1 BSP

2017-08-21 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/Makefile.am | 104 ++ c/src/lib/libbsp/riscv32/hifive1/bsp_specs| 13 c/src/lib/libbsp/riscv32/hifive1/configure.ac | 39 ++ 3 files changed, 156 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/Make

[PATCH v2 07/15] HiFive1: add irq dispatching function

2017-08-21 Thread Denis Obrezkov
/libbsp/riscv32/hifive1/include/irq.h @@ -11,6 +11,8 @@ * Copyright (c) 2015 University of York. * Hesham ALMatary * + * Copyright (c) 2017 Denis Obrezkov + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following

[PATCH v2 01/15] HiFive1: add linker file

2017-08-21 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds | 379 ++ 1 file changed, 379 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds diff --git a/c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds b/c/src/lib/libbsp/riscv32/hifive1/startup/li

[PATCH v2 03/15] HiFive1: add start.S file with basic initialization

2017-08-21 Thread Denis Obrezkov
new file mode 100644 index 000..5d0899c --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/start/start.S @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2015 University of York. + * Hesham ALMatary + * + * Copyright (c) 2017 Denis Obrezkov + * + * Redistribution and use in source and binary forms

[PATCH v2 06/15] HiFive1: add PRCI support files

2017-08-21 Thread Denis Obrezkov
+ * Denis Obrezkov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following

[PATCH v2 11/15] HiFive1: add UART support

2017-08-21 Thread Denis Obrezkov
file mode 100644 index 000..acb8004 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/console/fe310-uart.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2017 Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at

[PATCH v2 09/15] HiFive1: add clock driver support

2017-08-21 Thread Denis Obrezkov
@@ -0,0 +1,60 @@ +/* + * Copyright (c) 2017 Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include +#include +#include + +static void

[PATCH v2 10/15] HiFive1: set up oscillators

2017-08-21 Thread Denis Obrezkov
/bspstart.c new file mode 100644 index 000..bb04a22 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/start/bspstart.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017 + * Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution

Re: [PATCH 13/15] HiFive1: add interrupts enable/disable support

2017-08-21 Thread Denis Obrezkov
2017-08-21 19:39 GMT+02:00 Gedare Bloom : > On Mon, Aug 21, 2017 at 11:33 AM, Denis Obrezkov > wrote: > > 2017-08-20 5:18 GMT+02:00 Hesham Almatary : > >> > >> On Thu, Aug 17, 2017 at 1:13 AM, Denis Obrezkov < > denisobrez...@gmail.com> > >> wr

Re: [PATCH 11/15] HiFive1: set up oscillators

2017-08-21 Thread Denis Obrezkov
2017-08-21 19:40 GMT+02:00 Gedare Bloom : > On Mon, Aug 21, 2017 at 12:27 PM, Denis Obrezkov > wrote: > > 2017-08-17 17:16 GMT+02:00 Gedare Bloom : > >> > >> On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > >> wrote: > >> > --- > >&g

Re: [PATCH 12/15] HiFive1: add UART support

2017-08-21 Thread Denis Obrezkov
2017-08-17 17:21 GMT+02:00 Gedare Bloom : > Remove the extra blank lines, and consider adding some helper > functions (for enable/disable UARTx, for example) > > On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > wrote: > > --- > > .../libbsp/riscv32/hifive1/co

Re: [PATCH 08/15] HiFive1: add irq dispatching function

2017-08-21 Thread Denis Obrezkov
2017-08-17 17:11 GMT+02:00 Gedare Bloom : > On Wed, Aug 16, 2017 at 11:12 AM, Denis Obrezkov > wrote: > > --- > > c/src/lib/libbsp/riscv32/hifive1/irq/irq.c | 90 > ++ > > 1 file changed, 90 insertions(+) > > create mode 100644 c/s

Re: [PATCH 11/15] HiFive1: set up oscillators

2017-08-21 Thread Denis Obrezkov
2017-08-17 17:16 GMT+02:00 Gedare Bloom : > On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > wrote: > > --- > > c/src/lib/libbsp/riscv32/hifive1/start/bspstart.c | 65 > +++ > > 1 file changed, 65 insertions(+) > > create mode 100644 c/src

Re: [PATCH 10/15] HiFive1: add clock driver support

2017-08-21 Thread Denis Obrezkov
2017-08-17 17:13 GMT+02:00 Gedare Bloom : > On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > wrote: > > --- > > c/src/lib/libbsp/riscv32/hifive1/clock/clock.c | 67 > ++ > > 1 file changed, 67 insertions(+) > > create mode 100644 c/src

Re: [PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-21 Thread Denis Obrezkov
2017-08-19 14:33 GMT+02:00 Gedare Bloom : > On Fri, Aug 18, 2017 at 11:30 AM, Denis Obrezkov > wrote: > > 2017-08-17 23:58 GMT+02:00 Gedare Bloom : > >> > >> On Thu, Aug 17, 2017 at 4:17 PM, Denis Obrezkov < > denisobrez...@gmail.com> > >> wrote

Re: [PATCH 13/15] HiFive1: add interrupts enable/disable support

2017-08-21 Thread Denis Obrezkov
2017-08-20 5:18 GMT+02:00 Hesham Almatary : > On Thu, Aug 17, 2017 at 1:13 AM, Denis Obrezkov > wrote: > > --- > > cpukit/score/cpu/riscv32/rtems/score/cpu.h | 18 -- > > 1 file changed, 12 insertions(+), 6 deletions(-) > > > > diff --git a/

Re: [PATCH 02/15] HiFive1: add linker file

2017-08-21 Thread Denis Obrezkov
gt; It's important you try to address comments/feedback; students should > go through the code review process, etc it's one of the goals of > Google Summer of Code and open-source involvement. > > On Fri, Aug 18, 2017 at 2:59 AM, Denis Obrezkov > wrote: > > 2017-08-1

Re: [PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-19 Thread Denis Obrezkov
2017-08-19 14:33 GMT+02:00 Gedare Bloom : > On Fri, Aug 18, 2017 at 11:30 AM, Denis Obrezkov > wrote: > > 2017-08-17 23:58 GMT+02:00 Gedare Bloom : > >> > >> On Thu, Aug 17, 2017 at 4:17 PM, Denis Obrezkov < > denisobrez...@gmail.com> > >> wrote

Re: [PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-18 Thread Denis Obrezkov
2017-08-17 23:58 GMT+02:00 Gedare Bloom : > On Thu, Aug 17, 2017 at 4:17 PM, Denis Obrezkov > wrote: > > 2017-08-17 22:07 GMT+02:00 Gedare Bloom : > >> > >> On Thu, Aug 17, 2017 at 1:48 PM, Denis Obrezkov < > denisobrez...@gmail.com> > >> wrote

Re: [PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-17 Thread Denis Obrezkov
2017-08-17 22:07 GMT+02:00 Gedare Bloom : > On Thu, Aug 17, 2017 at 1:48 PM, Denis Obrezkov > wrote: > > 2017-08-17 17:25 GMT+02:00 Gedare Bloom : > >> > >> On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > >> wrote: > >> > --- > >

Re: [PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-17 Thread Denis Obrezkov
2017-08-17 17:25 GMT+02:00 Gedare Bloom : > On Wed, Aug 16, 2017 at 11:13 AM, Denis Obrezkov > wrote: > > --- > > cpukit/score/cpu/riscv32/riscv-context-switch.S | 12 ++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/cp

Re: [PATCH 02/15] HiFive1: add linker file

2017-08-17 Thread Denis Obrezkov
2017-08-17 16:57 GMT+02:00 Gedare Bloom : > On Wed, Aug 16, 2017 at 11:12 AM, Denis Obrezkov > wrote: > > --- > > c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds | 379 > ++ > > 1 file changed, 379 insertions(+) > > create mode 100644

[PATCH 14/15] HiFive1: add authorship note

2017-08-16 Thread Denis Obrezkov
+++ b/c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds @@ -11,6 +11,8 @@ * Copyright (c) 2015 University of York. * Hesham ALMatary * + * Copyright (c) 2017 Denis Obrezkov + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided

[PATCH 10/15] HiFive1: add clock driver support

2017-08-16 Thread Denis Obrezkov
new file mode 100644 index 000..74132ed --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/clock/clock.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2017 Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http

[PATCH 15/15] HiFive1: disable/enable interrupts during context switch

2017-08-16 Thread Denis Obrezkov
--- cpukit/score/cpu/riscv32/riscv-context-switch.S | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/riscv32/riscv-context-switch.S b/cpukit/score/cpu/riscv32/riscv-context-switch.S index a199596..bcdfe0e 100644 --- a/cpukit/score/cpu/riscv32/risc

[PATCH 09/15] HiFive1: add timer support

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/timer/timer.c | 71 ++ 1 file changed, 71 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/timer/timer.c diff --git a/c/src/lib/libbsp/riscv32/hifive1/timer/timer.c b/c/src/lib/libbsp/riscv32/hifive1/timer/timer.c new

[PATCH 08/15] HiFive1: add irq dispatching function

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/irq/irq.c | 90 ++ 1 file changed, 90 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/irq/irq.c diff --git a/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c b/c/src/lib/libbsp/riscv32/hifive1/irq/irq.c new file mode 1

[PATCH 07/15] HiFive1: add PRCI support files

2017-08-16 Thread Denis Obrezkov
+ * Denis Obrezkov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following

[PATCH 04/15] HiFive1: add start.S file with basic initialization

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/start/start.S | 290 + 1 file changed, 290 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/start/start.S diff --git a/c/src/lib/libbsp/riscv32/hifive1/start/start.S b/c/src/lib/libbsp/riscv32/hifive1/start/start.S ne

[PATCH 13/15] HiFive1: add interrupts enable/disable support

2017-08-16 Thread Denis Obrezkov
--- cpukit/score/cpu/riscv32/rtems/score/cpu.h | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/cpukit/score/cpu/riscv32/rtems/score/cpu.h b/cpukit/score/cpu/riscv32/rtems/score/cpu.h index 8f8a864..9b484e6 100644 --- a/cpukit/score/cpu/riscv32/rtems/score/c

[PATCH 11/15] HiFive1: set up oscillators

2017-08-16 Thread Denis Obrezkov
/bspstart.c new file mode 100644 index 000..efef4e0 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/start/bspstart.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2017 + * Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this

[PATCH 12/15] HiFive1: add UART support

2017-08-16 Thread Denis Obrezkov
file mode 100644 index 000..1784ff7 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/console/fe310-uart.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2017 Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at

[PATCH 06/15] HiFive1: add header file with board description

2017-08-16 Thread Denis Obrezkov
/fe310.h new file mode 100644 index 000..c73db99 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/include/fe310.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017 Denis Obrezkov + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at

[PATCH 05/15] HiFive1: add basic header files

2017-08-16 Thread Denis Obrezkov
/hifive1/include/tm27.h diff --git a/c/src/lib/libbsp/riscv32/hifive1/include/bsp.h b/c/src/lib/libbsp/riscv32/hifive1/include/bsp.h new file mode 100644 index 000..669a8b8 --- /dev/null +++ b/c/src/lib/libbsp/riscv32/hifive1/include/bsp.h @@ -0,0 +1,53 @@ +/* + * + * Copyright (c) 2017 Denis

[PATCH 03/15] HiFive1: add configure file

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/make/custom/hifive1.cfg | 7 +++ 1 file changed, 7 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/make/custom/hifive1.cfg diff --git a/c/src/lib/libbsp/riscv32/hifive1/make/custom/hifive1.cfg b/c/src/lib/libbsp/riscv32/hifive1/make/cus

[PATCH 02/15] HiFive1: add linker file

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds | 379 ++ 1 file changed, 379 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds diff --git a/c/src/lib/libbsp/riscv32/hifive1/startup/linkcmds b/c/src/lib/libbsp/riscv32/hifive1/startup/li

[PATCH 01/15] Add build support files for HiFive1 BSP

2017-08-16 Thread Denis Obrezkov
--- c/src/lib/libbsp/riscv32/hifive1/Makefile.am | 104 ++ c/src/lib/libbsp/riscv32/hifive1/bsp_specs| 13 c/src/lib/libbsp/riscv32/hifive1/configure.ac | 39 ++ 3 files changed, 156 insertions(+) create mode 100644 c/src/lib/libbsp/riscv32/hifive1/Make

Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 10:27 GMT+02:00 Denis Obrezkov : > 2017-08-16 3:09 GMT+02:00 Hesham Almatary : > >> On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: >> > >> > >> > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov < >> denisobrez...@gmail.com>

Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 3:09 GMT+02:00 Hesham Almatary : > On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > > > wrote: > >> > >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >>>

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-16 2:06 GMT+02:00 Hesham Almatary : > / > > On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov > wrote: > > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" > wrote: &

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 22:46 GMT+02:00 Denis Obrezkov : > 2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : >> >>> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>> >>>> >>>> >>>> On Aug 15, 2017

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >>> >>> >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >>> wrote: >>> >>>

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >> >>> Hi Denis, >>&g

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 14:57 GMT+02:00 Joel Sherrill : > > > On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: > > 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >> Hi Denis, >> >> You just need to modify riscv_interrupt_disable(). Read the priv-spec >> man

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
; priv-1.9). > > Cheers, > Hesham > > On Mon, Aug 14, 2017 at 6:10 PM, Denis Obrezkov > wrote: > > Hello all, > > > > at the end of the GSoC I've found out that interrupts in my BSP > > weren't properly enabled/disabled globally. > > This ha

New lower ticker clock driver issue

2017-08-14 Thread Denis Obrezkov
n. I think this happens during a context switch. Could you Hasham, check my context switch and interrupt handling routine? My work branch: https://github.com/embeddedden/rtems-riscv/tree/hifive1 -- Regards, Denis Obrezkov ___ devel mailing list devel

Re: Global configure options

2017-08-14 Thread Denis Obrezkov
2017-08-14 18:38 GMT+02:00 Joel Sherrill : > > > On Mon, Aug 14, 2017 at 11:32 AM, Denis Obrezkov > wrote: > >> Hello all, >> since my target board has a small amount of memory, >> where should I put the option >> CONFIGURE_UNIFIED_WORKSPACE >> to

Global configure options

2017-08-14 Thread Denis Obrezkov
Hello all, since my target board has a small amount of memory, where should I put the option CONFIGURE_UNIFIED_WORKSPACE to make it applied by default to all executives using my BSP? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org

RISC-V interrupts in HiFive1

2017-08-14 Thread Denis Obrezkov
sabling instructions did nothing in my version of ISA. I've tried to fix this issue, but without much of success. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Patch preparation for GSoC evaluation

2017-08-11 Thread Denis Obrezkov
2017-08-11 17:34 GMT+02:00 Christian Mauderer : > Am 11.08.2017 um 17:24 schrieb Denis Obrezkov: > > 2017-08-11 17:17 GMT+02:00 Christian Mauderer > <mailto:l...@c-mauderer.de>>: > > > > Am 11.08.2017 um 12:14 schrieb Denis Obrezkov: > > >

Re: Patch preparation for GSoC evaluation

2017-08-11 Thread Denis Obrezkov
2017-08-11 17:17 GMT+02:00 Christian Mauderer : > Am 11.08.2017 um 12:14 schrieb Denis Obrezkov: > > 2017-08-11 11:53 GMT+02:00 Sebastian Huber > > > <mailto:sebastian.hu...@embedded-brains.de>>: > > > > On 11/08/17 11:44, Denis Obrezkov wrote: &g

Re: Patch preparation for GSoC evaluation

2017-08-11 Thread Denis Obrezkov
2017-08-11 11:53 GMT+02:00 Sebastian Huber < sebastian.hu...@embedded-brains.de>: > On 11/08/17 11:44, Denis Obrezkov wrote: > > during our last meeting I didn't completely understand what to do >> with my commits. >> >> I have a set of commits made during t

Patch preparation for GSoC evaluation

2017-08-11 Thread Denis Obrezkov
them into one big commit which changes the state of the code from the initial to the current state? Or how should I clean my commit history? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Current state of RISC-V BSP

2017-08-09 Thread Denis Obrezkov
2017-08-09 2:56 GMT+02:00 Hesham Almatary : > Hi Denis, > > That's good to know. You might want to try running other samples now > that are not low-memory and see if they work. > > Cheers, > Hesham > > On Tue, Aug 8, 2017 at 7:51 PM, Denis Obrezkov > wrote:

Re: Current state of RISC-V BSP

2017-08-08 Thread Denis Obrezkov
2017-08-07 0:49 GMT+02:00 Denis Obrezkov : > 2017-08-07 0:44 GMT+02:00 Hesham Almatary : > >> Hi Denis, >> >> Thanks for sharing the state of HiFive1 BSP. At this stage of GSoC, we >> would want you to clean-up the code, write documentations/comments and >> s

Re: Current state of RISC-V BSP

2017-08-06 Thread Denis Obrezkov
uctions how to use your code (compile, build, run, etc) > are also important. > > Cheers, > Hesham > > On Mon, Aug 7, 2017 at 7:25 AM, Denis Obrezkov > wrote: > > Hello all, > > > > currently I have some issues with optimization flags. > > First of

Current state of RISC-V BSP

2017-08-06 Thread Denis Obrezkov
as I said it still doesn't work with optimization flags, so I can't test it. Also, I want to say that on this stage the BSP is very fragile and requires proper configuration options to be set. -- Regards, Denis Obrezkov ___ devel mailing

Re: BSP receiving messages via uart

2017-08-04 Thread Denis Obrezkov
2017-08-02 15:58 GMT+02:00 Gedare Bloom : > samples/capture uses the shell. I don't know if there is a small shell > example. > > On Wed, Aug 2, 2017 at 5:13 AM, Denis Obrezkov > wrote: > > Hello all, > > > > I am developing a small size BSP and want to

Re: /dev/urandom issue

2017-08-02 Thread Denis Obrezkov
r not, but I can propose as a quick fix to mount via NFS /dev/urandom from host. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

BSP receiving messages via uart

2017-08-02 Thread Denis Obrezkov
Hello all, I am developing a small size BSP and want to start receiving messages via uart. What is the best way to do it? Are there any tests for message receiving? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http

Re: Optimization issue in RISC-V BSP

2017-08-02 Thread Denis Obrezkov
require special handling. > > > > Every register needs to be logically places in a class for management > > purposes. > > > > > >> As for now, I am getting an error on mret instruction, I will try to > >> figure > >> out tomorrow, why it happens. &

Re: Optimization issue in RISC-V BSP

2017-07-31 Thread Denis Obrezkov
ddenly started to work properly. So, now I can debug a bit more efficient. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Optimization issue in RISC-V BSP

2017-07-31 Thread Denis Obrezkov
2017-07-31 11:56 GMT+02:00 Denis Obrezkov : > 2017-07-31 1:08 GMT+02:00 Hesham Almatary : > >> On Mon, Jul 31, 2017 at 5:03 AM, Denis Obrezkov >> wrote: >> > 2017-07-30 20:40 GMT+02:00 Joel Sherrill : >> >> >> >> >> >>

Re: Optimization issue in RISC-V BSP

2017-07-31 Thread Denis Obrezkov
2017-07-31 1:08 GMT+02:00 Hesham Almatary : > On Mon, Jul 31, 2017 at 5:03 AM, Denis Obrezkov > wrote: > > 2017-07-30 20:40 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Jul 30, 2017 12:19 PM, "Denis Obrezkov" >

Re: Optimization issue in RISC-V BSP

2017-07-30 Thread Denis Obrezkov
2017-07-30 20:40 GMT+02:00 Joel Sherrill : > > > On Jul 30, 2017 12:19 PM, "Denis Obrezkov" > wrote: > > 2017-07-30 3:10 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 29, 2017 8:02 PM, "Denis Obrezkov" >> wrote: >> >>

Re: Optimization issue in RISC-V BSP

2017-07-30 Thread Denis Obrezkov
2017-07-30 3:10 GMT+02:00 Joel Sherrill : > > > On Jul 29, 2017 8:02 PM, "Denis Obrezkov" wrote: > > > > 2017-07-30 2:34 GMT+02:00 Joel Sherrill : > >> >> Sorry to top post but this thread is very deep to answer on a phone. >> >> Try l

Re: Optimization issue in RISC-V BSP

2017-07-29 Thread Denis Obrezkov
ms_clock_get_tod - 09:00:00 12/31/1988 TA3 - rtems_clock_get_tod - 09:00:00 12/31/1988 -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Optimization issue in RISC-V BSP

2017-07-29 Thread Denis Obrezkov
2017-07-30 1:35 GMT+02:00 Denis Obrezkov : > 2017-07-29 19:14 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 29, 2017 4:04 AM, "Denis Obrezkov" >> wrote: >> >> 2017-07-29 3:45 GMT+02:00 Joel Sherrill : >> >>> >>> >>&

Re: Optimization issue in RISC-V BSP

2017-07-29 Thread Denis Obrezkov
2017-07-29 19:14 GMT+02:00 Joel Sherrill : > > > On Jul 29, 2017 4:04 AM, "Denis Obrezkov" wrote: > > 2017-07-29 3:45 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 28, 2017 7:11 PM, "Denis Obrezkov" >> wrote: >> >> 2017-0

Re: Optimization issue in RISC-V BSP

2017-07-29 Thread Denis Obrezkov
2017-07-29 3:45 GMT+02:00 Joel Sherrill : > > > On Jul 28, 2017 7:11 PM, "Denis Obrezkov" wrote: > > 2017-07-29 1:41 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 28, 2017 6:39 PM, "Denis Obrezkov" >> wrote: >> >> 2017-0

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-29 1:41 GMT+02:00 Joel Sherrill : > > > On Jul 28, 2017 6:39 PM, "Denis Obrezkov" wrote: > > 2017-07-29 1:28 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 28, 2017 6:14 PM, "Denis Obrezkov" >> wrote: >> >> 2017-0

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-29 1:28 GMT+02:00 Joel Sherrill : > > > On Jul 28, 2017 6:14 PM, "Denis Obrezkov" wrote: > > 2017-07-29 0:57 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 28, 2017 5:55 PM, "Denis Obrezkov" >> wrote: >> >>

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-29 0:57 GMT+02:00 Joel Sherrill : > > > On Jul 28, 2017 5:55 PM, "Denis Obrezkov" wrote: > > 2017-07-28 22:36 GMT+02:00 Joel Sherrill : > >> Can you check the memory immediately after a download'? >> >> Then after the loop that

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
l > > On Fri, Jul 28, 2017 at 3:20 PM, Denis Obrezkov > wrote: > >> 2017-07-28 22:16 GMT+02:00 Joel Sherrill : >> >>> >>> >>> On Fri, Jul 28, 2017 at 2:50 PM, Denis Obrezkov >> > wrote: >>> >>>> >>>>>>

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-28 22:16 GMT+02:00 Joel Sherrill : > > > On Fri, Jul 28, 2017 at 2:50 PM, Denis Obrezkov > wrote: > >> >>>> I can see that during task initialization I have a call: >>>> _Thread_Initialize_information (information=information@entry=0x8000

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
ight want to consider lowering it permanently like one of > the Coldfires > had to. Or change the default scheduler to the Simple one to save memory. > > I haven't dealt with the Scheduler option yet. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-28 17:31 GMT+02:00 Denis Obrezkov : > 2017-07-28 17:05 GMT+02:00 Joel Sherrill : > >> >> >> On Fri, Jul 28, 2017 at 9:23 AM, Denis Obrezkov >> wrote: >> >>> 2017-07-28 15:19 GMT+02:00 Sebastian Huber < >>> sebastian.hu...@embedd

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-28 17:05 GMT+02:00 Joel Sherrill : > > > On Fri, Jul 28, 2017 at 9:23 AM, Denis Obrezkov > wrote: > >> 2017-07-28 15:19 GMT+02:00 Sebastian Huber > ns.de>: >> >>> On 28/07/17 15:15, Denis Obrezkov wrote: >>> >>>

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-28 15:19 GMT+02:00 Sebastian Huber < sebastian.hu...@embedded-brains.de>: > On 28/07/17 15:15, Denis Obrezkov wrote: > > 2017-07-28 14:56 GMT+02:00 Joel Sherrill > j...@rtems.org>>: >> >> There is a debug option near the bottom of confdefs.h which

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
terrupt stack. Because, when an interrupt occurs, I save all registers and move the stack pointer, handle interrupt, restore registers and move stack pointer back. -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Optimization issue in RISC-V BSP

2017-07-28 Thread Denis Obrezkov
2017-07-28 13:11 GMT+02:00 Gedare Bloom : > On Thu, Jul 27, 2017 at 7:43 PM, Denis Obrezkov > wrote: > > I didn't want to enable optimization because I was afraid of new > mistakes. > > So, I enabled -Os and now I have: > > _Terminate (the_source=the_

Optimization issue in RISC-V BSP

2017-07-27 Thread Denis Obrezkov
e to optimization or has the optimization revealed another issue? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

How interrupts are handled in RTEMS

2017-07-26 Thread Denis Obrezkov
e we would have a pointers to functions the same as in RTEMS IRQ table. But what if we have no interrupt vectoring in a processor? -- Regards, Denis Obrezkov ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Can't enable a dummy clock driver

2017-07-24 Thread Denis Obrezkov
2017-07-24 20:36 GMT+02:00 Joel Sherrill : > > > On Jul 24, 2017 2:28 PM, "Denis Obrezkov" wrote: > > 2017-07-24 8:56 GMT+02:00 Denis Obrezkov : > >> 2017-07-24 8:27 GMT+02:00 Hesham Almatary : >> >>> On Mon, Jul 24, 2017 at 8:27 AM, Joel Sherri

Re: Can't enable a dummy clock driver

2017-07-24 Thread Denis Obrezkov
2017-07-24 8:56 GMT+02:00 Denis Obrezkov : > 2017-07-24 8:27 GMT+02:00 Hesham Almatary : > >> On Mon, Jul 24, 2017 at 8:27 AM, Joel Sherrill wrote: >> > >> > >> > On Jul 23, 2017 5:15 PM, "Denis Obrezkov" >> wrote: >> > >> &

Re: Can't enable a dummy clock driver

2017-07-23 Thread Denis Obrezkov
2017-07-24 8:27 GMT+02:00 Hesham Almatary : > On Mon, Jul 24, 2017 at 8:27 AM, Joel Sherrill wrote: > > > > > > On Jul 23, 2017 5:15 PM, "Denis Obrezkov" > wrote: > > > > 2017-07-23 22:30 GMT+02:00 Joel Sherrill : > >> > >> In

  1   2   >