CVA6 RISC-V support

Classified as: {THALES GROUP LIMITED DISTRIBUTION} Hello, I am working on the port of RTEMS 6 on our RISC-V processor, the CORE-V CVA6 processor GitHub - ThalesGroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux Th

RE: CVA6 RISC-V support

SMP should be independent. De : Joel Sherrill Envoyé : mardi 1 août 2023 20:54 À : EYSSARTIER Kevin Cc : devel@rtems.org Objet : Re: CVA6 RISC-V support Thanks for the submission. It's a bit hard to review with the patches as attachments rather than having been sent via git send-email but

Re: [PATCH 3/3] Force ISR enable before scheduler start

Classified as: {OPEN} I don't know how to run the tests. I observe that _Thread_Do_dispatch fails with INTERNAL_ERROR_BAD_THREAD_DISPATCH_ENVIRONMENT because RTEMS_SCORE_ROBUST_THREAD_DISPATCH is activated and the _ISR_Is_enabled returns false. Indeed, the _CPU_Start_multitasking should be cal

Re: [PATCH] cpukit/riscv : RISCV multitasking with non SMP

Classified as: {OPEN} Hello Sebastian, > The level shall be zero. If it is non-zero, then this is an application > bug resulting in the INTERNAL_ERROR_BAD_THREAD_DISPATCH_ENVIRONMENT > fatal error. This error happens also if you call operating system > services which block with interrupts disable