Just a late note to say thanks for the direction Sebastien. What you suggest
makes sense to me, requiring (and enforcing) that vector registers not be used
within _RISCV_Interrupt_dispatch() while preserving the vector state across
_Thread_Do_dispatch(). (ref:
Hello RTEMS experts,
We're in the process of implementing support for RTEMS on a new RISC-V
platform. Among other things, our processor core supports the RISC-V Vector
ISA (RVV), with its 32 vector registers which in our case are 512 bits (VLEN)
deep. RVV is used by applications to
