ZynqMP hardware appears to have an odd hard-wired SGI implementation in which the SGIs are permanently set as enabled or disabled. Allow the TM27 IRQs to be overridden as necessary. --- bsps/aarch64/xilinx-zynqmp/include/tm27.h | 8 ++++++++ bsps/include/dev/irq/arm-gic-tm27.h | 4 ++++ 2 files changed, 12 insertions(+)
diff --git a/bsps/aarch64/xilinx-zynqmp/include/tm27.h b/bsps/aarch64/xilinx-zynqmp/include/tm27.h index 7598570c64..204748dd9d 100644 --- a/bsps/aarch64/xilinx-zynqmp/include/tm27.h +++ b/bsps/aarch64/xilinx-zynqmp/include/tm27.h @@ -41,6 +41,14 @@ #ifndef __tm27_h #define __tm27_h +/* + * On ZynqMP hardware, SGI0-7 are permanently enabled for IPI usage while + * SGI8-15 are permanently disabled along with PPI16-24. Override tm27's usage + * of SGI12 and SGI13 with SGI6 and SGI7. + */ +#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_6 +#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_7 + #include <dev/irq/arm-gic-tm27.h> #endif /* __tm27_h */ diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h index fde3e6392c..167310660d 100644 --- a/bsps/include/dev/irq/arm-gic-tm27.h +++ b/bsps/include/dev/irq/arm-gic-tm27.h @@ -34,9 +34,13 @@ #define MUST_WAIT_FOR_INTERRUPT 1 +#ifndef ARM_GIC_TM27_IRQ_LOW #define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12 +#endif +#ifndef ARM_GIC_TM27_IRQ_HIGH #define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13 +#endif #define ARM_GIC_TM27_PRIO_LOW 0x80 -- 2.20.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
