LIC, IMSIC.
Ken
-Original Message-
From: Sebastian Huber
Sent: Friday, March 15, 2024 7:30 AM
To: Ken Unger - C34024 ; devel@rtems.org
Subject: Re: [RFC] Adding RISC-V Vector support to RTEMS
Hello Ken,
On 14.03.24 18:33, ken.un...@microchip.com wrote:
> Hello RTEMS experts,
>
> W
Hello Ken,
On 14.03.24 18:33, ken.un...@microchip.com wrote:
Hello RTEMS experts,
We’re in the process of implementing support for RTEMS on a new RISC-V
platform. Among other things, our processor core supports the RISC-V
Vector ISA (RVV), with its 32 vector registers which in our case are 5
Hello RTEMS experts,
We're in the process of implementing support for RTEMS on a new RISC-V
platform. Among other things, our processor core supports the RISC-V Vector
ISA (RVV), with its 32 vector registers which in our case are 512 bits (VLEN)
deep. RVV is used by applications to accelerat
