Hello Jiri,
thanks, this helped to fix a bug in the SMP user extensions code for
thread switches:
https://git.rtems.org/rtems/commit/?id=26333f2ad09fc2ecd574fb167862520493c63ee3
I updated also the RSB:
https://git.rtems.org/rtems-source-builder/commit/?id=ee40e0bf0bf233902491ee3de1c56d2a93e2
Hello Sebastian,
here is a patch for RSB that improves sis debugging in gdb and on SMP systems:
* Correct break-point handling in gdb
* Detect and break on NULL pointer derefence (call/jump)
* Single stepping (stepi) in gdb/sis keeps focus on debugged cpu
* 'sim cpu' command shows active cpu
On 2/7/19 12:53 PM, Jiri Gaisler wrote:
> On 2/7/19 12:45 PM, Sebastian Huber wrote:
>> On 07/02/2019 12:43, Jiri Gaisler wrote:
>>> Works OK here:
>>>
>>> $ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4
>>> ./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe
>>>
>>> SI
On 2/7/19 12:45 PM, Sebastian Huber wrote:
>
>
> On 07/02/2019 12:43, Jiri Gaisler wrote:
>> Works OK here:
>>
>> $ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4
>> ./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe
>>
>> SIS - SPARC/RISCV instruction simulator 2.11,
On 07/02/2019 12:43, Jiri Gaisler wrote:
Works OK here:
$ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4
./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe
SIS - SPARC/RISCV instruction simulator 2.11, copyright Jiri Gaisler 1995
Bug-reports to j...@gaisler.se
Works OK here:
$ sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4
./sparc-rtems5/c/leon3/testsuites/smptests/smpswitchextension01.exe
SIS - SPARC/RISCV instruction simulator 2.11, copyright Jiri Gaisler 1995
Bug-reports to j...@gaisler.se
LEON3 emulation enabled, 4 cpus online, delta
Hello,
I get a NULL pointer exception in one of the tests:
sparc-rtems5-sis -leon3 -nouartrx -r -tlim 200 s -m 4
smpswitchextension01.exe
SIS - SPARC/RISCV instruction simulator 2.11, copyright Jiri Gaisler 1995
Bug-reports to j...@gaisler.se
LEON3 emulation enabled, 4 cpus online, delta
