Re: RISC-V interrupt vectoring

2017-07-05 Thread Denis Obrezkov
2017-07-05 15:42 GMT+02:00 Joel Sherrill : > > > On Jul 5, 2017 8:12 AM, "Denis Obrezkov" wrote: > > 2017-07-05 14:44 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 5, 2017 7:22 AM, "Gedare Bloom" wrote: >> >> On Tue, Jul 4, 2017 at 7:47 AM, Denis Obrezkov >> wrote: >> > 2017-07-03 21:17 GMT+02:00

Re: RISC-V interrupt vectoring

2017-07-05 Thread Joel Sherrill
On Jul 5, 2017 8:12 AM, "Denis Obrezkov" wrote: 2017-07-05 14:44 GMT+02:00 Joel Sherrill : > > > On Jul 5, 2017 7:22 AM, "Gedare Bloom" wrote: > > On Tue, Jul 4, 2017 at 7:47 AM, Denis Obrezkov > wrote: > > 2017-07-03 21:17 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Jul 3, 2017 12:45 PM,

Re: RISC-V interrupt vectoring

2017-07-05 Thread Denis Obrezkov
2017-07-05 14:44 GMT+02:00 Joel Sherrill : > > > On Jul 5, 2017 7:22 AM, "Gedare Bloom" wrote: > > On Tue, Jul 4, 2017 at 7:47 AM, Denis Obrezkov > wrote: > > 2017-07-03 21:17 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Jul 3, 2017 12:45 PM, "Denis Obrezkov" > wrote: > >> > >> 2017-07-03 1

Re: RISC-V interrupt vectoring

2017-07-05 Thread Joel Sherrill
On Jul 5, 2017 7:22 AM, "Gedare Bloom" wrote: On Tue, Jul 4, 2017 at 7:47 AM, Denis Obrezkov wrote: > 2017-07-03 21:17 GMT+02:00 Joel Sherrill : >> >> >> >> On Jul 3, 2017 12:45 PM, "Denis Obrezkov" wrote: >> >> 2017-07-03 19:09 GMT+02:00 Joel Sherrill : >>> >>> >>> >>> On Jul 3, 2017 11:49 AM,

Re: RISC-V interrupt vectoring

2017-07-05 Thread Gedare Bloom
On Tue, Jul 4, 2017 at 7:47 AM, Denis Obrezkov wrote: > 2017-07-03 21:17 GMT+02:00 Joel Sherrill : >> >> >> >> On Jul 3, 2017 12:45 PM, "Denis Obrezkov" wrote: >> >> 2017-07-03 19:09 GMT+02:00 Joel Sherrill : >>> >>> >>> >>> On Jul 3, 2017 11:49 AM, "Denis Obrezkov" >>> wrote: >>> >>> 2017-07-03

Re: RISC-V interrupt vectoring

2017-07-04 Thread Hesham Almatary
Hi Denis, It's not clear from your output which instruction is causing the fault. You can debug this by investigating mcause value after the faulting instruction, and see what's the value in s0, and whether it's valid or not. It's also a good idea to use objdump and/or Spike/Qemu for debugging (

Re: RISC-V interrupt vectoring

2017-07-04 Thread Denis Obrezkov
2017-07-03 21:17 GMT+02:00 Joel Sherrill : > > > On Jul 3, 2017 12:45 PM, "Denis Obrezkov" wrote: > > 2017-07-03 19:09 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 3, 2017 11:49 AM, "Denis Obrezkov" >> wrote: >> >> 2017-07-03 7:43 GMT+02:00 Hesham Almatary : >> >>> On Mon, Jul 3, 2017 at 3:36 PM,

Re: RISC-V interrupt vectoring

2017-07-04 Thread Denis Obrezkov
2017-07-03 21:17 GMT+02:00 Joel Sherrill : > > > On Jul 3, 2017 12:45 PM, "Denis Obrezkov" wrote: > > 2017-07-03 19:09 GMT+02:00 Joel Sherrill : > >> >> >> On Jul 3, 2017 11:49 AM, "Denis Obrezkov" >> wrote: >> >> 2017-07-03 7:43 GMT+02:00 Hesham Almatary : >> >>> On Mon, Jul 3, 2017 at 3:36 PM,

Re: RISC-V interrupt vectoring

2017-07-03 Thread Joel Sherrill
On Jul 3, 2017 12:45 PM, "Denis Obrezkov" wrote: 2017-07-03 19:09 GMT+02:00 Joel Sherrill : > > > On Jul 3, 2017 11:49 AM, "Denis Obrezkov" wrote: > > 2017-07-03 7:43 GMT+02:00 Hesham Almatary : > >> On Mon, Jul 3, 2017 at 3:36 PM, Denis Obrezkov >> wrote: >> > 2017-07-03 4:59 GMT+02:00 Hesham

Re: RISC-V interrupt vectoring

2017-07-03 Thread Denis Obrezkov
2017-07-03 19:09 GMT+02:00 Joel Sherrill : > > > On Jul 3, 2017 11:49 AM, "Denis Obrezkov" wrote: > > 2017-07-03 7:43 GMT+02:00 Hesham Almatary : > >> On Mon, Jul 3, 2017 at 3:36 PM, Denis Obrezkov >> wrote: >> > 2017-07-03 4:59 GMT+02:00 Hesham Almatary : >> >> >> >> You can have a look at risc

Re: RISC-V interrupt vectoring

2017-07-03 Thread Joel Sherrill
On Jul 3, 2017 11:49 AM, "Denis Obrezkov" wrote: 2017-07-03 7:43 GMT+02:00 Hesham Almatary : > On Mon, Jul 3, 2017 at 3:36 PM, Denis Obrezkov > wrote: > > 2017-07-03 4:59 GMT+02:00 Hesham Almatary : > >> > >> You can have a look at riscv-pk [1] as a RISC-V reference how to > >> handle interrupt

Re: RISC-V interrupt vectoring

2017-07-03 Thread Denis Obrezkov
2017-07-03 7:43 GMT+02:00 Hesham Almatary : > On Mon, Jul 3, 2017 at 3:36 PM, Denis Obrezkov > wrote: > > 2017-07-03 4:59 GMT+02:00 Hesham Almatary : > >> > >> You can have a look at riscv-pk [1] as a RISC-V reference how to > >> handle interrupts. RTEMS-wise, you can look at or1k and ARM code an

Re: RISC-V interrupt vectoring

2017-07-02 Thread Hesham Almatary
On Mon, Jul 3, 2017 at 3:36 PM, Denis Obrezkov wrote: > 2017-07-03 4:59 GMT+02:00 Hesham Almatary : >> >> You can have a look at riscv-pk [1] as a RISC-V reference how to >> handle interrupts. RTEMS-wise, you can look at or1k and ARM code and >> how the platform-dependent interrupt handling code i

Re: RISC-V interrupt vectoring

2017-07-02 Thread Denis Obrezkov
2017-07-03 4:59 GMT+02:00 Hesham Almatary : > You can have a look at riscv-pk [1] as a RISC-V reference how to > handle interrupts. RTEMS-wise, you can look at or1k and ARM code and > how the platform-dependent interrupt handling code is linked to > platform-independent one. > > mcause value can b

Re: RISC-V interrupt vectoring

2017-07-02 Thread Hesham Almatary
You can have a look at riscv-pk [1] as a RISC-V reference how to handle interrupts. RTEMS-wise, you can look at or1k and ARM code and how the platform-dependent interrupt handling code is linked to platform-independent one. mcause value can be used as an index to a software vector table that you s

RISC-V interrupt vectoring

2017-07-02 Thread Denis Obrezkov
Hello all, I am trying to enable vectored interrupts on my HiFive1 board. I was able to install interrupt vector base address, but it didn't work. And I wasn't able to generate a software interrupt. Though, it seems that interrupts works - at some moment of execution, I catch the exception 'Illegal