On 28/6/2022 1:14 pm, Kinsey Moore wrote:
> On 6/26/2022 22:37, Chris Johns wrote:
>> On 24/6/2022 7:43 pm, Sebastian Huber wrote:
>>> The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
>>> define) and AArch64 targets. Use the existing WRITE_SR() abstraction to
>>>
On 6/26/2022 22:37, Chris Johns wrote:
On 24/6/2022 7:43 pm, Sebastian Huber wrote:
The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets. Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers. This
On 24/6/2022 7:43 pm, Sebastian Huber wrote:
> The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
> define) and AArch64 targets. Use the existing WRITE_SR() abstraction to
> access
> the interrupt group 0 and 1 enable registers. This fixes the build for the
> AArch32