Re: [PATCH] irq/arm-gicv3.h: Enable interrupt groups 0 and 1

2022-07-01 Thread Chris Johns
On 28/6/2022 1:14 pm, Kinsey Moore wrote: > On 6/26/2022 22:37, Chris Johns wrote: >> On 24/6/2022 7:43 pm, Sebastian Huber wrote: >>> The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4 >>> define) and AArch64 targets.  Use the existing WRITE_SR() abstraction to >>>

Re: [PATCH] irq/arm-gicv3.h: Enable interrupt groups 0 and 1

2022-06-27 Thread Kinsey Moore
On 6/26/2022 22:37, Chris Johns wrote: On 24/6/2022 7:43 pm, Sebastian Huber wrote: The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4 define) and AArch64 targets. Use the existing WRITE_SR() abstraction to access the interrupt group 0 and 1 enable registers. This

Re: [PATCH] irq/arm-gicv3.h: Enable interrupt groups 0 and 1

2022-06-26 Thread Chris Johns
On 24/6/2022 7:43 pm, Sebastian Huber wrote: > The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4 > define) and AArch64 targets. Use the existing WRITE_SR() abstraction to > access > the interrupt group 0 and 1 enable registers. This fixes the build for the > AArch32