Hi Sebastian,
> On Fri, 2022-11-04 at 14:03 +0100, Sebastian Huber wrote:
> On 04/11/2022 10:49, Sebastian Huber wrote:
> > On 04/11/2022 10:44, padmarao.beg...@microchip.com wrote:
> > > Hi Sebastian,
> > >
> > > > On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote:
> > > >
> > > > On
On 04/11/2022 10:49, Sebastian Huber wrote:
On 04/11/2022 10:44, padmarao.beg...@microchip.com wrote:
Hi Sebastian,
On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote:
On 03/11/2022 06:40,padmarao.beg...@microchip.com wrote:
On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
t0
On 04/11/2022 10:44, padmarao.beg...@microchip.com wrote:
Hi Sebastian,
On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote:
On 03/11/2022 06:40,padmarao.beg...@microchip.com wrote:
On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
t0 contains the address of
Hi Sebastian,
> On Fri, 2022-11-04 at 08:07 +0100, Sebastian Huber wrote:
>
> On 03/11/2022 06:40, padmarao.beg...@microchip.com wrote:
> > > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
> > >
> > > t0 contains the address of .Lsecondary_processor_go
> > >
> > > start.S has:
> > >
On 03/11/2022 06:40, padmarao.beg...@microchip.com wrote:
On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
t0 contains the address of .Lsecondary_processor_go
start.S has:
```asm
#if __riscv_xlen == 32
.align 2
#elif __riscv_xlen == 64
.align 3
#endif
.Lsecondary_processor_go:
Check what is the address of .Lsecondary_processor_go
and confirm it is 8-byte aligned.
The patch you indicated with the `.option norelax` could have an
effect on alignment, but it should be the case that the alignment is
ensured (rather than violated).
On Thu, Nov 3, 2022 at 12:37 AM wrote:
>
> On Thu, 2022-11-03 at 05:40 +, padmarao.beg...@microchip.com
wrote:
> Hi Gedare,
> > On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
> >
> > t0 contains the address of .Lsecondary_processor_go
> >
> > start.S has:
> > ```asm
> > #if __riscv_xlen == 32
> > .align 2
> > #elif
Hi Gedare,
> On Wed, 2022-11-02 at 09:58 -0600, Gedare Bloom wrote:
>
> t0 contains the address of .Lsecondary_processor_go
>
> start.S has:
> ```asm
> #if __riscv_xlen == 32
> .align 2
> #elif __riscv_xlen == 64
> .align 3
> #endif
>
> .Lsecondary_processor_go:
> ```
> Can you confirm
t0 contains the address of .Lsecondary_processor_go
start.S has:
```asm
#if __riscv_xlen == 32
.align 2
#elif __riscv_xlen == 64
.align 3
#endif
.Lsecondary_processor_go:
```
Can you confirm the value of __riscv_xlen is properly defined to 64
for the PolarFire?
On Wed, Nov 2, 2022 at
Hi Sebastian,
The "Store/AMO address misaligned" trap occured in the "start.S"
at "amoswap.w zero, zero, 0(t0)" while testing the sample
application with the latest RTEMS master for RISC-V on
the Microchip PolarFire SoC.
The trap occured after this
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