Thanks for your review.
>
> >
> > > > +- reg: Offset and length of the clock register set
> > > > +- clock-frequency: Indicates input clock frequency of clock block.
> > > > + Will be set by u-boot
> > >
> > > Why does the fact this is set by u-boot matter to the binding?
> > >
> > OK, I wi
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月12日 星期六 3:08
> To: Tang Yuantian-B29983
> Cc: ga...@kernel.crashing.org; devicetree@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org
> Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in
Thanks for your review.
> -Original Message-
> From: Wood Scott-B07421
> Sent: 2013年10月12日 星期六 3:07
> To: Mark Rutland
> Cc: Tang Yuantian-B29983; devicetree@vger.kernel.org; linuxppc-
> d...@lists.ozlabs.org; Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock n
* Andrey Konovalov [131011 12:42]:
> Commit 851320e (ARM: dts: Fix muxing and regulator for wl12xx on the
> SDIO bus for pandaboard) put the wl12xx pins into omap4_pmx_wkup. This
> is not correct, and results in the following messages at the boot time:
>
> pinctrl-single 4a31e040.pinmux: mux off
* Suman Anna [131010 14:24]:
> Add the hwspinlock device tree node for OMAP4 family
> of SoCs.
Suman, can you please post the .dts changes separately from
the driver changes next time so driver maintainers don't
accidentally pick them up. That leads to unnecessary merge
conflicts with the .dts fi
* Sebastian Reichel [131009 14:26]:
> Add Keyboard Matrix information to N900's DTS file.
> This patch maps the keys exactly as the original
> board code.
This should be queued by Benoit along with other .dts
changes, not via the input tree:
Acked-by: Tony Lindgren
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To unsubscribe from this l
* Sebastian Reichel [131009 14:25]:
> Add device tree support for twl4030 keypad driver and update the
> Documentation with twl4030 keypad device tree binding information.
>
> This patch also adds a twl4030 keypad node to the twl4030.dtsi file,
> so that board files can just add the keymap.
>
>
* Tero Kristo [131010 01:25]:
> On 10/09/2013 09:55 PM, Paul Walmsley wrote:
> >So in my view, the right things to do here are to:
> >
> >1. associate SoC DT clock data with the device node that contains the
> >clock control registers
>
> So, either "cm", "prcm", and maybe "control_module" in
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> This commit adds support for both DSI outputs found on Tegra. Only very
> minimal functionality is implemented, so advanced features like ganged
> mode won't work.
>
> Due to the lack of other test hardware, some sections of the driver are
> hardcode
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> The gr2d hardware in Tegra114 is compatible with that of Tegra20 and
> Tegra30. No functionaly changes are required.
Similarly here, if the HW is 100% backwards-compatible, there's no need
to add compatible values to the driver.
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To unsubscribe fro
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Oh yea, one additional note you probably have missed. Mike asked us to fall
> back to vendor specific bindings at around v6 or so of this set. Take a look
> at v8, we have dropped the use of generic bindings, we are not trying to
> declare those with this
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> This driver adds support to perform calibration of the MIPI pads for CSI
> and DSI.
> diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c
> +int tegra_mipi_calibrate(struct device *device)
...
> + err = of_parse_phandle_with_args(
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> Add a driver for simple panels. Such panels can have a regulator that
> provides the supply voltage and a separate GPIO to enable the panel.
> Optionally the panels can have a backlight associated with them so it
> can be enabled or disabled according
> +#else
> +static struct device_node *of_find_gpio(struct device *dev, const char *id
> + unsigned int idx, unsigned long flags)
> +{
> + return ERR_PTR(-ENODEV);
> +}
> +#endif
... and of course I forgot to fix the main compilation error. Linus,
would you
On Fri, 11 Oct 2013, Tero Kristo wrote:
> Well, even if you sign something, you can still update it. Writing any
> software to true OTP memory is one way to commit suicide IMO. How many nasty
> bugs have you seen with ROM code? Also, if people want to make their custom
> security solutions which a
On 10/11/2013 04:19 PM, Stephen Warren wrote:
> On 10/07/2013 02:34 AM, Thierry Reding wrote:
>> From: Mikko Perttunen
>>
>> Tegra114 TMDS configuration requires a new peak_current field and the
>> driver current override bit has changed position.
>
>> diff --git a/drivers/gpu/drm/tegra/hdmi.c b/
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> From: Mikko Perttunen
>
> Tegra114 TMDS configuration requires a new peak_current field and the
> driver current override bit has changed position.
> diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
> static const struct t
On Fri, Oct 11, 2013 at 2:46 PM, Tony Lindgren wrote:
> * Brian Norris [131011 12:35]:
>> On Fri, Oct 11, 2013 at 11:28 AM, Tony Lindgren wrote:
>> >
>> > FYI, the .dts changes should be queued separately by Benoit to avoid
>> > pointless merge conflicts. The arch/arm/mach-omap2/gpmc.c changes I
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> From: Mikko Perttunen
>
> The Tegra114 display controller is backwards-compatible with previous
> generations of the Tegra SoC. No code changes are required.
If the HW is backwards-compatible, then there's no need to add extra
compatible values to
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> Tegra114 uses a slightly updated version of host1x with an additional
> syncpoint.
> drivers/gpu/host1x/hw/host1x02.c| 42 +
> drivers/gpu/host1x/hw/host1x02.h| 26 +++
> drivers/gpu/host1x/hw/hw_host1x02_channel.h | 12
On 10/07/2013 02:34 AM, Thierry Reding wrote:
> In order to subsystem-wide changes easier, move the Tegra DRM driver
^^ make ?
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More majordomo info at http://
Not all Tegra devices can set the CPU reset handler in the same way.
In particular, devices using a TrustZone secure monitor cannot set the
reset handler directly and need to do it through a firmware operation.
This patch separates the act of setting the reset handler from its
preparation, so the
Support for Trusted Foundations is light and allows the kernel to run on
a wider range of devices, so enable it by default.
Signed-off-by: Alexandre Courbot
Reviewed-by: Tomasz Figa
Reviewed-by: Stephen Warren
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --g
* Brian Norris [131011 12:35]:
> On Fri, Oct 11, 2013 at 11:28 AM, Tony Lindgren wrote:
> >
> > FYI, the .dts changes should be queued separately by Benoit to avoid
> > pointless merge conflicts. The arch/arm/mach-omap2/gpmc.c changes I
> > need to look, hopefully I can ack those for you today so
Use a firmware operation to set the CPU reset handler and only resort to
doing it ourselves if there is none defined.
This supports the booting of secondary CPUs on devices using a TrustZone
secure monitor.
Signed-off-by: Alexandre Courbot
Reviewed-by: Tomasz Figa
Reviewed-by: Stephen Warren
-
Register the firmware operations for Trusted Foundations if the device
tree indicates it is active on the device.
Signed-off-by: Alexandre Courbot
Reviewed-by: Tomasz Figa
Reviewed-by: Stephen Warren
---
Documentation/devicetree/bindings/arm/tegra.txt | 5 +
arch/arm/mach-tegra/Kconfig
Trusted Foundations is a TrustZone-based secure monitor for ARM that
can be invoked using the same SMC-based API on all supported
platforms. This patch adds initial basic support for Trusted
Foundations using the ARM firmware API. Current features are limited
to the ability to boot secondary proces
Hopefully this has received enough review to be merged (although a few more
acks/review especially from DT people on patch 1 would be nice). Thanks
everyone for all the input and comments!
Trusted Foundations is an ARM secure monitor that is used by many Tegra-based
retail devices (like SHIELD and
* Benoit Cousson [131011 12:13]:
> Hi Tony,
>
> On 11/10/2013 20:03, Tony Lindgren wrote:
> >Hi Benoit,
> >
> >* Benoit Cousson [131011 09:50]:
> >>Add the minimal DTS support for DRA7xx based SoC core.
> >>Add the initial support for N900 and gta04 phones.
> >>Enable USB3 on OMAP5 evm board.
>
From: Darbha Sriharsha
Adds support for the bq24735 charger chipset. The bq24735 is a
high-efficiency, synchronous battery charger.
It allows control of the charging current, input current, and the charger
voltage DAC's through SMBus.
Signed-off-by: Darbha Sriharsha
Signed-off-by: Rhyland Klei
Hi Pekon,
I will try to summarize the standing of your patch series.
Patches 1 and 2 look good and have addressed all of the DT maintainers'
comments, AFAICT. They are ready to go in, except that the following
patches are not ready; they should probably go in together.
You ignored most of my com
On 10/11, Stanimir Varbanov wrote:
> This adds Qualcomm PRNG driver device tree binding documentation
> to use as an example in dts trees.
>
> Signed-off-by: Stanimir Varbanov
> ---
> Documentation/devicetree/bindings/rng/qcom,prng.txt | 17 +
> 1 file changed, 17 insertions(+)
>
On 10/11, Stanimir Varbanov wrote:
> This adds a driver for hardware random number generator present
> on Qualcomm MSM SoC's.
>
> Signed-off-by: Stanimir Varbanov
> ---
Just nitpicks.
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index 0aa9d91daef5..d902330cef
On Fri, Oct 11, 2013 at 07:06:41PM +0530, Pekon Gupta wrote:
> This patch adds following two flavours of BCH4 ECC scheme in omap2-nand driver
> - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
> - uses GPMC H/W engine for calculating ECC.
> - uses software library (lib/bch.h & nand_bch.h) for error
Commit 851320e (ARM: dts: Fix muxing and regulator for wl12xx on the
SDIO bus for pandaboard) put the wl12xx pins into omap4_pmx_wkup. This
is not correct, and results in the following messages at the boot time:
pinctrl-single 4a31e040.pinmux: mux offset out of range: 0x38 (0x38)
pinctrl-single
On Fri, Oct 11, 2013 at 07:06:40PM +0530, Pekon Gupta wrote:
> OMAP NAND driver support multiple ECC scheme, which can used in following
> different flavours, depending on in-build Hardware engines supported by SoC.
>
> +---+---+---+
> |
On Fri, Oct 11, 2013 at 11:28 AM, Tony Lindgren wrote:
> * Brian Norris [131011 11:23]:
>> Hi Pekon,
>>
>> On Fri, Oct 11, 2013 at 07:06:43PM +0530, Pekon Gupta wrote:
>> > "Managed Device Resource" or devm_xx calls takes care of automatic freeing
>> > of the resource in case of:
>> > - failure d
Hello.
On 11-10-2013 3:00, Simon Horman wrote:
[ CCed devicetree@vger.kernel.org as this involves DT compatibility strings ]
Note that I did CC then-existing devicetree-discuss list when posting the
original driver but we got no feedback from there. That's why the binding
documentation i
Hi Tony,
Please pull the updated branch for OMAP Device Tree for v3.13.
I removed the 2 conflicting patches, and added 2 mores for dra7 to compensate
:-)
Thanks,
Benoit
The following changes since commit d0e639c9e06d44e713170031fe05fb60ebe680af:
Linux 3.12-rc4 (2013-10-06 14:00:20 -0700)
Hi Balaji,
On 11/10/2013 18:44, Balaji T K wrote:
On Thursday 10 October 2013 12:21 AM, Sekhar Nori wrote:
On Monday 07 October 2013 09:55 PM, Balaji T K wrote:
Add mmc1 dt node to dra7-evm board.
Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21)
on i2c1 bus. When dt supp
On Wed, 2013-10-09 at 14:38 +0800, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian +/ {
> + clockgen: global-utilities@e1000 {
> + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> + reg = <0xe1000 0x1000>;
> + clock-frequency = <0>;
>
On Fri, 2013-10-11 at 10:25 +0100, Mark Rutland wrote:
> On Fri, Oct 11, 2013 at 04:18:18AM +0100, Tang Yuantian-B29983 wrote:
> > Thanks for your review.
> > See my reply inline
> >
> > > -Original Message-
> > > From: Mark Rutland [mailto:mark.rutl...@arm.com]
> > > Sent: 2013年10月10日 星期四
Hi Tony,
On 11/10/2013 20:03, Tony Lindgren wrote:
Hi Benoit,
* Benoit Cousson [131011 09:50]:
Add the minimal DTS support for DRA7xx based SoC core.
Add the initial support for N900 and gta04 phones.
Enable USB3 on OMAP5 evm board.
Add support for cryto accelerators
Add new IGEP AQUILA board
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
On Thu, 10 Oct 2013, Tero Kristo wrote:
On 10/09/2013 09:59 PM, Paul Walmsley wrote:
Eh, one correction:
On Wed, 9 Oct 2013, Paul Walmsley wrote:
We could easily wind up with kernels that won't boot at all when used
with newer DT data.
This is
* Felipe Balbi [131011 09:04]:
> On Fri, Oct 11, 2013 at 07:06:38PM +0530, Pekon Gupta wrote:
> > OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
> > ecc-scheme, like:
> > - OMAP_ECC_HAMMING_CODE_DEFAULT
> > 1-bit hamming ecc code using software library
> > - OMAP_ECC_HA
* Felipe Balbi [131011 09:03]:
> On Fri, Oct 11, 2013 at 07:06:39PM +0530, Pekon Gupta wrote:
> > OMAP NAND driver support multiple ECC scheme, which can used in following
> > different flavours, depending on in-build Hardware engines supported by SoC.
> >
> > +---
* Brian Norris [131011 11:23]:
> Hi Pekon,
>
> On Fri, Oct 11, 2013 at 07:06:43PM +0530, Pekon Gupta wrote:
> > "Managed Device Resource" or devm_xx calls takes care of automatic freeing
> > of the resource in case of:
> > - failure during driver probe
> > - failure during resource allocation
> >
+static const struct capri_cfg_param capri_pinconf_params[] = {
+ {"brcm,hysteresis", CAPRI_PINCONF_PARAM_HYST},
+ {"brcm,pull", CAPRI_PINCONF_PARAM_PULL},
+ {"brcm,slew", CAPRI_PINCONF_PARAM_SLEW},
+ {"brcm,input_dis", C
On 10/11/2013 08:54 PM, Paul Walmsley wrote:
On Thu, 10 Oct 2013, Tero Kristo wrote:
On 10/09/2013 09:59 PM, Paul Walmsley wrote:
Eh, one correction:
On Wed, 9 Oct 2013, Paul Walmsley wrote:
We could easily wind up with kernels that won't boot at all when used
with newer DT data.
This is
Refactor the of_ functions of gpiolib to use the now public gpiod
interface, and export of_get_named_gpiod_flags() and
of_get_gpiod_flags() functions.
Signed-off-by: Alexandre Courbot
---
drivers/gpio/gpiolib-of.c | 28 +---
include/linux/of_gpio.h | 29
Add gpiod_get(), gpiod_get_index() and gpiod_put() functions that
private safer management of GPIOs.
These functions put the GPIO framework in line with the conventions of
other frameworks in the kernel, and help ensure every GPIO is declared
properly and valid while it is used.
Signed-off-by: Al
This patch exports the gpiod_* family of API functions, a safer
alternative to the legacy GPIO interface. Differences between the gpiod
and legacy gpio APIs are:
- gpio works with integers, whereas gpiod operates on opaque handlers
which cannot be forged or used before proper acquisition
- gpiod
Hi Pekon,
On Fri, Oct 11, 2013 at 07:06:43PM +0530, Pekon Gupta wrote:
> "Managed Device Resource" or devm_xx calls takes care of automatic freeing
> of the resource in case of:
> - failure during driver probe
> - failure during resource allocation
> - detaching or unloading of driver module (rmmo
Hi Linus,
Hopefully this version should compile nicely in all cases. It also improves
inline documentation, but more work is needed for the GPIO guide in
Documentation/. This should follow shortly.
I prefer to send it as-is as other patches started depending on this series and
I guess you don't w
On Oct 11, 2013, at 2:48 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2013-10-11 at 09:27 +0200, Marek Szyprowski wrote:
>> Hi all!
>>
>> Benjamin Herrenschmidt pointed a few issues in the proposed design of
>> device tree bindings for contiguous memory allocator and reserved memory
>> regions:
>
Hi Benoit,
* Benoit Cousson [131011 09:50]:
> Add the minimal DTS support for DRA7xx based SoC core.
> Add the initial support for N900 and gta04 phones.
> Enable USB3 on OMAP5 evm board.
> Add support for cryto accelerators
> Add new IGEP AQUILA board
> Add AM33XX EDMA support
> Update HSUSB nod
On Thu, 10 Oct 2013, Tero Kristo wrote:
> On 10/09/2013 09:59 PM, Paul Walmsley wrote:
> > Eh, one correction:
> >
> > On Wed, 9 Oct 2013, Paul Walmsley wrote:
> >
> > > We could easily wind up with kernels that won't boot at all when used
> > > with newer DT data.
> >
> > This is a misstatemen
On Fri, Oct 11, 2013 at 7:46 AM, Linus Walleij wrote:
> On Fri, Oct 11, 2013 at 3:10 PM, Jiří Prchal wrote:
>> Dne 11.10.2013 14:49, Linus Walleij napsal(a):
>
>>> If the GPIOs are actually connected to LEDs you should be
>>> using drivers/leds/leds-gpio.c and not export the GPIOs.
>>
>> I know t
On Thursday 10 October 2013 12:21 AM, Sekhar Nori wrote:
On Monday 07 October 2013 09:55 PM, Balaji T K wrote:
Add mmc1 dt node to dra7-evm board.
Input for ldo1 regulator is controlled by gpio 5 of pcf8575 chip (0x21)
on i2c1 bus. When dt support for gpio-pcf857x is available, input supply
will
Hi Tony,
Please pull the following commits for OMAP Device Tree for v3.13.
Thanks,
Benoit
The following changes since commit d0e639c9e06d44e713170031fe05fb60ebe680af:
Linux 3.12-rc4 (2013-10-06 14:00:20 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/ker
On Fri, Oct 11, 2013 at 6:18 PM, Prabhakar Lad
wrote:
> On 10/11/13, Linus Walleij wrote:
>> On Fri, Oct 11, 2013 at 4:59 PM, Prabhakar Lad
>> wrote:
>>> On 10/11/13, Linus Walleij wrote:
On Fri, Oct 4, 2013 at 6:03 PM, Prabhakar Lad
wrote:
>>
> +- ti,davinci-gpio-irq-base: Base
Hi Linus,
On 10/11/13, Linus Walleij wrote:
> On Fri, Oct 11, 2013 at 4:59 PM, Prabhakar Lad
> wrote:
>> On 10/11/13, Linus Walleij wrote:
>>> On Fri, Oct 4, 2013 at 6:03 PM, Prabhakar Lad
>>> wrote:
>
+- ti,davinci-gpio-irq-base: Base from where GPIO interrupt numbering
starts.
>>>
* Joel Fernandes [131010 08:31]:
> On 10/10/2013 10:20 AM, Joel Fernandes wrote:
> >
> > Adding 6 lines of identical code for every platform seems redundant, I'd
> > just
> > define an omap_common_late_init for all platforms for now, and then fork
> > off for
> > the future differences. That wa
On Fri, Oct 11, 2013 at 09:37:45AM +0200, Boris BREZILLON wrote:
> This patch moves at91_pmc.h header from machine specific directory
> (arch/arm/mach-at91/include/mach/at91_pmc.h) to clk include directory
> (include/linux/clk/at91_pmc.h).
> We need this to avoid reference to machine specific heade
* Linus Walleij [131011 09:05]:
> On Fri, Oct 11, 2013 at 5:43 PM, Tony Lindgren wrote:
> > * Linus Walleij [131011 03:40]:
> >> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
> >>
> >> > The register handling is fine. But how do we deal with resource handling?
> >> > e.g. the block tha
Hi,
On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
> Hi Naveen,
>
> On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
> >
> > Hi,
> >
> > All patches (#1-#3) look good to me, FWIW you can add:
> >
> > Reviewed-by: Bartlomiej Zolnierkiewicz
> >
> > Please note that (
On Fri, Oct 11, 2013 at 5:43 PM, Tony Lindgren wrote:
> * Linus Walleij [131011 03:40]:
>> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
>>
>> > The register handling is fine. But how do we deal with resource handling?
>> > e.g. the block that has the deep-core registers might need to b
On Fri, Oct 11, 2013 at 07:06:43PM +0530, Pekon Gupta wrote:
> "Managed Device Resource" or devm_xx calls takes care of automatic freeing
> of the resource in case of:
> - failure during driver probe
> - failure during resource allocation
> - detaching or unloading of driver module (rmmod)
> Refere
On Fri, Oct 11, 2013 at 07:06:40PM +0530, Pekon Gupta wrote:
> OMAP NAND driver support multiple ECC scheme, which can used in following
> different flavours, depending on in-build Hardware engines supported by SoC.
>
> +---+---+---+
> |
On Fri, Oct 11, 2013 at 07:06:39PM +0530, Pekon Gupta wrote:
> OMAP NAND driver support multiple ECC scheme, which can used in following
> different flavours, depending on in-build Hardware engines supported by SoC.
>
> +---+---+---+
> |
On Fri, Oct 11, 2013 at 07:06:41PM +0530, Pekon Gupta wrote:
> This patch adds following two flavours of BCH4 ECC scheme in omap2-nand driver
> - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
> - uses GPMC H/W engine for calculating ECC.
> - uses software library (lib/bch.h & nand_bch.h) for error
On Fri, Oct 11, 2013 at 07:06:42PM +0530, Pekon Gupta wrote:
> Updated DTS to replace deprecated binding with newer values
> Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
>
> Signed-off-by: Pekon Gupta
Reviewed-by: Felipe Balbi
> ---
> arch/arm/boot/dts/am335x-evm.dts | 3 +--
>
On Fri, Oct 11, 2013 at 07:06:38PM +0530, Pekon Gupta wrote:
> OMAP NAND driver currently supports multiple flavours of 1-bit Hamming
> ecc-scheme, like:
> - OMAP_ECC_HAMMING_CODE_DEFAULT
> 1-bit hamming ecc code using software library
> - OMAP_ECC_HAMMING_CODE_HW
> 1-bit hamming ecc-co
On Fri, Oct 11, 2013 at 4:59 PM, Prabhakar Lad
wrote:
> On 10/11/13, Linus Walleij wrote:
>> On Fri, Oct 4, 2013 at 6:03 PM, Prabhakar Lad
>> wrote:
>>> +- ti,davinci-gpio-irq-base: Base from where GPIO interrupt numbering
>>> starts.
>>
>> What is this?
>>
>> If I have ever ACKed this I have b
* Balaji T K [131011 08:51]:
> On Friday 11 October 2013 09:06 PM, Tony Lindgren wrote:
> >>>What the pin control driver should do is control the pins. Whether the
> >>>registers
> >>>are spread out in the entire IO-memory does not matter. We did have one
> >>>system
> >>>which placed the IO-mux
On Fri, Oct 11, 2013 at 4:53 PM, Jonas Jensen wrote:
> I agree it is a bit strange GPIO control is divided in two
> separate registers. Unfortunately I can't offer an explanation
> because the documentation is not publicly available.
>
> The register responsible for doing enable/d
On Friday 11 October 2013 09:06 PM, Tony Lindgren wrote:
What the pin control driver should do is control the pins. Whether the registers
are spread out in the entire IO-memory does not matter. We did have one system
which placed the IO-muxing together with each peripheral (!) and I did
still wan
* Linus Walleij [131011 03:40]:
> On Fri, Oct 11, 2013 at 10:56 AM, Roger Quadros wrote:
>
> > The register handling is fine. But how do we deal with resource handling?
> > e.g. the block that has the deep-core registers might need to be clocked or
> > powered
> > before the registers can be ac
* Roger Quadros [131011 02:04]:
> On 10/11/2013 11:00 AM, Linus Walleij wrote:
> > On Thu, Oct 10, 2013 at 6:20 PM, Tony Lindgren wrote:
> >> * Linus Walleij [131010 09:19]:
> >>> On Thu, Oct 10, 2013 at 6:00 PM, Tony Lindgren wrote:
> * Roger Quadros [131010 06:32]:
> >
> > I tri
This adds a driver for hardware random number generator present
on Qualcomm MSM SoC's.
Signed-off-by: Stanimir Varbanov
---
drivers/char/hw_random/Kconfig | 12 +++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/msm-rng.c | 195 +++
3 file
This adds Qualcomm PRNG driver device tree binding documentation
to use as an example in dts trees.
Signed-off-by: Stanimir Varbanov
---
Documentation/devicetree/bindings/rng/qcom,prng.txt | 17 +
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindi
Here is the second version of RNG driver for MSM SoC's.
During the time since first version I've made some tests using
rng tools this is the result:
# cat /dev/hw_random | rngtest -c 10
Copyright (c) 2004 by Henrique de Moraes Holschuh
This is free software; see the source for copying condit
* Roger Quadros [131011 07:07]:
> On 10/11/2013 11:49 AM, Roger Quadros wrote:
> > On 10/10/2013 07:00 PM, Tony Lindgren wrote:
> >>
> >> Well the irq_set_wake() should only be needed for suspend and resume. For
> >> runtime PM
> >> the wake-events should be always enabled by default as pointed o
On 10/11/2013 06:47 PM, Mark Rutland wrote:
On Fri, Oct 11, 2013 at 11:54:52AM +0100, Valentine wrote:
On 10/11/2013 01:41 PM, Mark Rutland wrote:
On Fri, Oct 11, 2013 at 02:00:35AM +0100, Simon Horman wrote:
[ CCed devicetree@vger.kernel.org as this involves DT compatibility strings ]
Cheer
Hi Naveen,
On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> All patches (#1-#3) look good to me, FWIW you can add:
>
> Reviewed-by: Bartlomiej Zolnierkiewicz
>
> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
> fixup patchset:
>
> https:/
Hi,
On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
> Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
> power_on and power_off the following APIs are used phy_init(), phy_exit(),
> phy_power_on() and phy_power_off().
>
> However using the old USB phy library wont be r
On 09/16/2013 10:37 AM, Roger Quadros wrote:
> On 09/16/2013 06:01 AM, Kishon Vijay Abraham I wrote:
>> On Thursday 12 September 2013 04:49 PM, Roger Quadros wrote:
>>> Hi Kishon,
>>>
>>> On 09/02/2013 06:43 PM, Kishon Vijay Abraham I wrote:
Adapted omap-usb3 PHY driver to Generic PHY Framewor
Hi Linus ,
On 10/11/13, Linus Walleij wrote:
> On Fri, Oct 4, 2013 at 6:03 PM, Prabhakar Lad
> wrote:
>
>> This patch adds OF parser support for davinci gpio
>> driver and also appropriate documentation in gpio-davinci.txt
>> located at Documentation/devicetree/bindings/gpio/.
>>
>> Signed-off-b
Add GPIO driver for MOXA ART SoCs.
Signed-off-by: Jonas Jensen
---
Notes:
Thanks for the replies,
I agree it is a bit strange GPIO control is divided in two
separate registers. Unfortunately I can't offer an explanation
because the documentation is not publicly available.
On Fri, Oct 11, 2013 at 11:54:52AM +0100, Valentine wrote:
> On 10/11/2013 01:41 PM, Mark Rutland wrote:
> > On Fri, Oct 11, 2013 at 02:00:35AM +0100, Simon Horman wrote:
> >> [ CCed devicetree@vger.kernel.org as this involves DT compatibility
> >> strings ]
> >
> > Cheers!
> >
>
> Hi Mark,
>
>
Hi,
On 10/10/2013 01:49 PM, Kishon Vijay Abraham I wrote:
> From: George Cherian
>
> Added dr_mode property in dwc3 and set its default mode to device.
If there is a specific reason why this is not set to "otg", we need
to explain it here.
AFAIK the port is meant to be used as OTG port.
>
>
On Fri, Oct 11, 2013 at 3:10 PM, Jiří Prchal wrote:
> Dne 11.10.2013 14:49, Linus Walleij napsal(a):
>> If the GPIOs are actually connected to LEDs you should be
>> using drivers/leds/leds-gpio.c and not export the GPIOs.
>
> I know that, just don't like /sys/class/leds/out15/brightness.
Hm, the
On Fri, Oct 4, 2013 at 6:03 PM, Prabhakar Lad
wrote:
> This patch adds OF parser support for davinci gpio
> driver and also appropriate documentation in gpio-davinci.txt
> located at Documentation/devicetree/bindings/gpio/.
>
> Signed-off-by: KV Sujith
> Signed-off-by: Philip Avinash
> Acked-by
On 10/11/2013 11:49 AM, Roger Quadros wrote:
> On 10/10/2013 07:00 PM, Tony Lindgren wrote:
>> * Roger Quadros [131010 06:32]:
>>>
>>> I tried testing this with the USB EHCI driver, but I'm not getting wake up
>>> interrupts
>>> while the system is still running and only the EHCI controller is ru
On Thu, Oct 3, 2013 at 12:44 PM, wrote:
> From: Tien Hock Loh
>
> Add driver support for Altera GPIO soft IP, including interrupts and I/O.
> Tested on Altera CV SoC board using dipsw and LED using LED framework.
>
> Signed-off-by: Tien Hock Loh
> ---
> .../devicetree/bindings/gpio/gpio-alter
On 10/10/2013 11:31 AM, Felipe Balbi wrote:
Hi,
On Mon, Oct 07, 2013 at 06:12:30AM -0400, Matt Porter wrote:
Broadcom BCM281xx parts have a PHY control block that
operates in conjunction with the DWC2 USB OTG. This driver
exposes an API that allows control of power/reset for a
connected USB PHY
Hi,
On Fri, Oct 11, 2013 at 12:03:40PM +0100, Jiri Prchal wrote:
> Add export possibility to sysfs with given name in device tree.
> Rebased from older unapplyed patch: [PATCH] owrt: GPIO: add
> gpio_export_with_name.
>
> Signed-off-by: Jiri Prchal
> ---
> Documentation/devicetree/bindings/gpi
"Managed Device Resource" or devm_xx calls takes care of automatic freeing
of the resource in case of:
- failure during driver probe
- failure during resource allocation
- detaching or unloading of driver module (rmmod)
Reference: Documentation/driver-model/devres.txt
Though OMAP NAND driver handl
Updated DTS to replace deprecated binding with newer values
Refer: Documentation/devicetree/bindings/mtd/gpmc-nand.txt
Signed-off-by: Pekon Gupta
---
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/omap3430-sdp.dts | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --gi
Hi,
On Thu, Oct 10, 2013 at 11:21:30PM -0400, Matt Porter wrote:
> On 10/10/2013 03:07 PM, Matt Porter wrote:
> >On 10/10/2013 01:57 PM, Paul Zimmerman wrote:
> >>>From: Felipe Balbi [mailto:ba...@ti.com]
> >>>Sent: Thursday, October 10, 2013 10:46 AM
> >>>
> >>>On Thu, Oct 10, 2013 at 12:54:40PM
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