On Sat, Nov 2, 2013 at 2:54 AM, Grant Likely wrote:
>
> That one was broken. Try this instead.
>
> From bcbffc3d16f49451ef505dc021480aa061465a15 Mon Sep 17 00:00:00 2001
> From: Grant Likely
> Date: Fri, 1 Nov 2013 10:50:50 -0700
> Subject: [PATCH] of: Fixup interrupt parsing failure.
>
> Signed-
On Fri, Nov 1, 2013 at 5:08 PM, Stephen Boyd wrote:
> From: Rohit Vaswani
>
> Scorpion and Krait are Qualcomm cpus. These cpus don't use the
> spin-table enable-method. Instead they rely on mmio register
> accesses to enable power and clocks to bring CPUs out of reset.
>
> Cc:
> Signed-off-by: R
On Fri, Nov 1, 2013 at 5:08 PM, Stephen Boyd wrote:
> From: Rohit Vaswani
>
> According to the ePAPR CPUs should have an enable method. On ARM
> the enable-method property has not been used so far, so document
> this property as an optional property and add the spin-table
> method as one value
>
On Fri, Nov 1, 2013 at 5:49 AM, Wolfram Sang wrote:
> On Wed, Oct 16, 2013 at 03:01:46PM -0700, Tim Kryger wrote:
>> Introduce support for Broadcom Serial Controller (BSC) I2C bus found
>> in the Kona family of Mobile SoCs. FIFO hardware is utilized but only
>> standard mode (100kHz), fast mode (
On Sat, 02 Nov 2013 10:10:25 +1100 Benjamin Herrenschmidt
wrote:
> On Fri, 2013-11-01 at 13:47 -0700, Greg Kroah-Hartman wrote:
>
> > > > On my device I seem to have some platform devices registered through
> > > > device-tree, and some registered through platform_device_add (e.g.
> > > > 'alarm
On Fri, 1 Nov 2013 10:16:44 -0700 Mark Rutland wrote:
> Hi Neil,
>
> While I'm not fundamentally opposed to this binding, I have some issues with
> its current form and would not want to see this version hit mainline.
>
Thanks for the review.
> On Fri, Nov 01, 2013 at 09:50:05AM +, NeilBr
On Fri, 2013-11-01 at 13:47 -0700, Greg Kroah-Hartman wrote:
> > > On my device I seem to have some platform devices registered through
> > > device-tree, and some registered through platform_device_add (e.g.
> > > 'alarmtimer'). Guaranteeing they remain disjoint sets if the kernel is
> > > allow
On Fri, 2013-11-01 at 13:47 -0700, Greg Kroah-Hartman wrote:
> > > On my device I seem to have some platform devices registered through
> > > device-tree, and some registered through platform_device_add (e.g.
> > > 'alarmtimer'). Guaranteeing they remain disjoint sets if the kernel is
> > > allow
Hi Rob,
On Friday 01 of November 2013 16:52:44 Rob Herring wrote:
> On 10/14/2013 10:08 AM, Vyacheslav Tyrtov wrote:
> > From: Tarek Dakhran
> >
> > EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> > Add initial support for this SoC.
>
> I think this entire patch is mostly unnecessary and t
On Tue, Oct 15, 2013 at 11:03:28PM +0100, Rostislav Lisovy wrote:
> Enable UART1 and FEC
>
> Signed-off-by: Rostislav Lisovy
>
> create mode 100644 arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
>
> diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
> b/arch/arm/boot/dts/imx53-voipac-dmm-6
On Fri, Nov 01, 2013 at 09:54:10PM +0100, Arend van Spriel wrote:
> On 11/01/2013 08:45 PM, Matt Porter wrote:
> >Add a binding that describes the Broadcom Kona USB2 PHY found
> >on the BCM281xx family of SoCs.
> >
> >Signed-off-by: Matt Porter
> >---
> > .../devicetree/bindings/phy/bcm-kona-usb2
On Fri, Nov 01, 2013 at 11:56:33PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 11/01/2013 10:45 PM, Matt Porter wrote:
>
> >Adds USB OTG/PHY and clock support to BCM281xx and enables
> >UDC support on the bcm11351-brt and bcm28155-ap boards.
>
> >Signed-off-by: Matt Porter
> >Reviewed-by: Mar
On Fri, Nov 1, 2013 at 5:13 AM, Ian Campbell wrote:
> GICv2 (Cortex A15/GIC 400) have CPU interface registers up to offset 0x1004
> (the 32-bit GICC_DIR register a 0x1000). The GIC 400 documentation specifies
> the CPU interface region as being 0x2000 in size.
>
> Update all DTS entries claiming "
The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.
Cc:
Signed-off-by: Stephen Boyd
---
.../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/binding
This is a rework of patches sent a few months back by Rohit[1].
The goal of these patches is to add support for SMP and (basic)
hotplug on MSM based SoCs. To get there, we add support for a
generic way to add SMP/hotplug support code in the kernel. To
show how it's used, we convert the MSM8660 SMP
From: Rohit Vaswani
According to the ePAPR CPUs should have an enable method. On ARM
the enable-method property has not been used so far, so document
this property as an optional property and add the spin-table
method as one value
Cc:
Signed-off-by: Rohit Vaswani
[sboyd: Split off into separat
From: Rohit Vaswani
Scorpion and Krait are Qualcomm cpus. These cpus don't use the
spin-table enable-method. Instead they rely on mmio register
accesses to enable power and clocks to bring CPUs out of reset.
Cc:
Signed-off-by: Rohit Vaswani
[sboyd: Split off into separate patch, renamed method
The saw2 binding describes the SPM/AVS wrapper hardware used to
control the regulator supplying voltage to the Krait CPUs.
Cc:
Signed-off-by: Stephen Boyd
---
When a SAW is for a CPU it is put behind the CPU alias region similar
to the ACC and timers. I haven't documented that here because I'm
The goal of multi-platform kernels is to remove the need for mach
directories and machine descriptors. To further that goal,
introduce CPU_METHOD_OF_DECLARE() to allow cpu hotplug/smp
support to be separated from the machine descriptors.
Implementers should specify an enable-method property in thei
On 10/14/2013 10:08 AM, Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran
>
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
I think this entire patch is mostly unnecessary and this information
should all be coming from DT. I'll leave it to arm-soc maintainer
On 11/01/2013 03:59 AM, Hiroshi Doyu wrote:
...
> One idea is that, rather than inserting a hook(function) per
> subsystems in driver core, if we invent a new /special section/ which
> collects all hooks in sequence like initcalls, the subsystem just
> would declare a hook function for that special
On 11/01/2013 12:49 AM, Hiroshi Doyu wrote:
> On Thu, 31 Oct 2013 18:53:22 +0100
> Stephen Warren wrote:
> ...
>> We're talking about memory-mapped on-SoC devices here, that generally
>> only exist inside Tegra SoCs.
>>
>> Even ignoring that (i.e. expanding the argument to arbitrary modules),
>> h
On 10/31/2013 08:55 AM, Nishanth Menon wrote:
> On 10/31/2013 04:10 AM, Tero Kristo wrote:
>> On 10/30/2013 10:10 PM, Nishanth Menon wrote:
>>> On 10/30/2013 10:00 AM, Nishanth Menon wrote:
On 10/30/2013 03:23 AM, Tero Kristo wrote:
> On 10/29/2013 06:19 PM, Nishanth Menon wrote:
>> On
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
> diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
> new file mode 100644
> index 000..c555443
> --- /dev/null
> +++ b/arch/arm/boot/dts/am3517.dtsi
> @@ -0,0 +1,31 @@
> +/*
> + * Device Tree Source for AM3517 SoC
> + *
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
> diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
> index 974d103..1fb3ac2 100644
> --- a/arch/arm/boot/dts/am4372.dtsi
> +++ b/arch/arm/boot/dts/am4372.dtsi
> @@ -67,6 +67,8 @@
> ranges;
> ti,hw
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
> diff --git a/arch/arm/mach-omap2/prm_common.c
> b/arch/arm/mach-omap2/prm_common.c
> index 228b850..6fa74c6 100644
> --- a/arch/arm/mach-omap2/prm_common.c
> +++ b/arch/arm/mach-omap2/prm_common.c
[...]
> +/*
> + * XXX: implementation for the reg
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
> diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
> new file mode 100644
> index 000..9c5259a
> --- /dev/null
> +++ b/drivers/clk/ti/mux.c
[...]
> +/**
> + * of_mux_clk_setup() - Setup function for simple mux rate clock
> + */
> +static
On 11/01/2013 08:45 PM, Matt Porter wrote:
Add a binding that describes the Broadcom Kona USB2 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter
---
.../devicetree/bindings/phy/bcm-kona-usb2-phy.txt | 15 +++
1 file changed, 15 insertions(+)
create mo
On Fri, Nov 01, 2013 at 11:04:59AM -0700, Grant Likely wrote:
> Second, I expect there is going to be userspace breakage to move them.
> I've considered moving them before, but so far have felt that being
> tidier hasn't been worth the potential breakage. Userspace /shouldn't/
> be relying on the n
On Fri, Nov 01, 2013 at 04:08:36PM +1100, Benjamin Herrenschmidt wrote:
> On Fri, 2013-11-01 at 16:03 +1100, NeilBrown wrote:
>
> > Do you mean we could allow multiple devices on the one bus to have the same
> > name, but get sysfs to notice and de-duplicate by mangling one name? I
> > don't
> >
On Fri, 2013-11-01 at 11:04 -0700, Grant Likely wrote:
> There are two problems here. First, making the change moves all the DT
> populated devices under the /sys/devices/platform tree, not just
> platform devices.
All DT populated *platform* devices. There are others that have their
own location
On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
> diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
> new file mode 100644
> index 000..1b3099e
> --- /dev/null
> +++ b/drivers/clk/ti/clockdomain.c
> @@ -0,0 +1,58 @@
> +/*
> + * OMAP clockdomain support
> + *
> + * Copyri
On 10/25/2013 10:57 AM, Tero Kristo wrote:
> This patch adds support for TI specific gate clocks. These behave as basic
> gate-clock, but have different ops / hw-ops for controlling the actual
> gate, for example waiting until the clock is ready. Several sub-types
> are supported:
> - ti,gate-clock
Hi Tony,
> From: Tony Lindgren
> > * Brian Norris [131029 21:00]:
> > Tony, you mentioned the DTS update in patch 8 going in via an ARM
> > tree? This patch is not urgent, and it should probably wait until we
> > know what release the rest of the series makes it into. This may
> > depend on David
Hello.
On 11/01/2013 10:45 PM, Matt Porter wrote:
Adds USB OTG/PHY and clock support to BCM281xx and enables
UDC support on the bcm11351-brt and bcm28155-ap boards.
Signed-off-by: Matt Porter
Reviewed-by: Markus Mayer
Reviewed-by: Tim Kryger
---
arch/arm/boot/dts/bcm11351-brt.dts | 6 +
Remove unused Samsung-specific machine include and Kconfig
dependency on S3C.
Signed-off-by: Matt Porter
Reviewed-by: Markus Mayer
Reviewed-by: Tim Kryger
---
drivers/usb/gadget/Kconfig | 7 +++
drivers/usb/gadget/s3c-hsotg.c | 2 --
2 files changed, 3 insertions(+), 6 deletions(-)
di
This adds a pair of APIs that allows the generic PHY subsystem to
provide information on the PHY bus width. The PHY provider driver may
use phy_set_bus_width() to set the bus width that the PHY supports.
The controller driver may then use phy_get_bus_width() to fetch the
PHY bus width in order to p
dwc2/s3c-hsotg require a single clock to be specified and optionally
a generic phy. On the s3c-hsotg driver old style USB phy support is
present as a fallback so the generic phy properties are optional.
Signed-off-by: Matt Porter
---
Documentation/devicetree/bindings/staging/dwc2.txt | 12 ++
Enable support for the dwc2 binding.
Signed-off-by: Matt Porter
---
drivers/usb/gadget/s3c-hsotg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 258bc73..3e0c124 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/
Adds support for the generic PHY subsystem. Generic PHY
support is probed and then the driver falls back to checking
for an old style USB PHY and pdata if not found.
Signed-off-by: Matt Porter
---
drivers/usb/gadget/s3c-hsotg.c | 54 --
1 file changed, 36
Adds USB OTG/PHY and clock support to BCM281xx and enables
UDC support on the bcm11351-brt and bcm28155-ap boards.
Signed-off-by: Matt Porter
Reviewed-by: Markus Mayer
Reviewed-by: Tim Kryger
---
arch/arm/boot/dts/bcm11351-brt.dts | 6 ++
arch/arm/boot/dts/bcm11351.dtsi| 18 ++
Add a driver for the internal Broadcom Kona USB 2.0 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter
---
drivers/phy/Kconfig | 6 ++
drivers/phy/Makefile| 2 +
drivers/phy/phy-bcm-kona-usb2.c | 161
3 files
Adds support for querying the phy bus width from the generic phy
subsystem. Configure UTMI bus width in GUSBCFG based on this value.
Signed-off-by: Matt Porter
---
drivers/usb/gadget/s3c-hsotg.c | 14 +-
drivers/usb/gadget/s3c-hsotg.h | 1 +
2 files changed, 14 insertions(+), 1 dele
Changes since v1:
- Convert USB phy driver to generic phy subsystem
- Add phy bus width apis
- Drop dwc2 phy bus width DT property in favor of querying the
phy provider for bus width
- Add generic phy/clock properties to dwc2 DT binding
- Add generi
Add a binding that describes the Broadcom Kona USB2 PHY found
on the BCM281xx family of SoCs.
Signed-off-by: Matt Porter
---
.../devicetree/bindings/phy/bcm-kona-usb2-phy.txt | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/
On 11/01/2013 04:54 AM, Tero Kristo wrote:
> On 11/01/2013 11:48 AM, Tero Kristo wrote:
>> On 10/31/2013 08:02 PM, Nishanth Menon wrote:
>>> On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
new file mode 100644
index 0
On Fri, Nov 1, 2013 at 1:21 AM, Seungwon Jeon wrote:
> On Fri, November 01, 2013, zhangfei gao wrote:
>> Dear Seungwon
>>
>> Thanks for giving suggestion.
>>
>> On Thu, Oct 31, 2013 at 11:24 PM, Seungwon Jeon wrote:
>> > Hi Zhangfei,
>>
>> >> +static void dw_mci_k3_set_ios(struct dw_mci *host, st
On 11/01/2013 04:35 AM, Tero Kristo wrote:
> On 10/31/2013 06:27 PM, Nishanth Menon wrote:
>> On 10/25/2013 10:57 AM, Tero Kristo wrote:
[..]
>>> diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
>>> new file mode 100644
>>> index 000..9ce7e54
>>> --- /dev/null
>>> +++ b/dri
On 11/01/2013 04:18 AM, Tero Kristo wrote:
> On 10/31/2013 06:05 PM, Nishanth Menon wrote:
>> On 10/25/2013 10:57 AM, Tero Kristo wrote:
[...]
>>> diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
>>> new file mode 100644
>>> index 000..efa2a3e
>>> --- /dev/null
>>> +++ b/driv
On 11/01/2013 04:12 AM, Tero Kristo wrote:
> On 10/31/2013 05:42 PM, Nishanth Menon wrote:
>> On 10/25/2013 10:57 AM, Tero Kristo wrote:
>>> ti_dt_clk_init_provider() can now be used to initialize the contents of
>>> a single clock IP block. This parses all the clocks under the IP block
>>> and cal
On 11/01/2013 11:53 AM, Grant Likely wrote:
> On Thu, 31 Oct 2013 11:57:14 -0700, Olof Johansson wrote:
>> On Wed, Oct 30, 2013 at 02:25:21PM -0700, Grant Likely wrote:
>>> (Sorry for HTML mail)
>>>
>>> Can you put #define DEBUG at the top of drivers/of/irq.c and send me the
>>> log output from be
On Fri, 01 Nov 2013 10:53:17 -0700, Grant Likely
wrote:
> On Thu, 31 Oct 2013 11:57:14 -0700, Olof Johansson wrote:
> > On Wed, Oct 30, 2013 at 02:25:21PM -0700, Grant Likely wrote:
> > > (Sorry for HTML mail)
> > >
> > > Can you put #define DEBUG at the top of drivers/of/irq.c and send me the
On Fri, Nov 01, 2013 at 03:04:52PM +0800, Xiubo Li wrote:
> On VF610 series there are no regulators used, and now whether the
> CONFIG_REGULATOR mirco is enabled or not, for the VF610 audio
> patch series, the board cannot be probe successfully.
> And this patch will solve this issue.
I don't unde
On Fri, Nov 01, 2013 at 03:04:53PM +0800, Xiubo Li wrote:
> Conflicts:
> sound/soc/fsl/Makefile
Ahem.
> + /* TODO: The SAI driver should figure this out for us */
> + switch (channels) {
> + case 2:
> + snd_soc_dai_set_tdm_slot(cpu_dai, 0xfffc, 0xfffc, 2, 0)
On Fri, Nov 01, 2013 at 03:04:48PM +0800, Xiubo Li wrote:
> +static int fsl_sai_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
> + int div_id, int div)
> +{
> + struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
> + u32 tcr2, rcr2;
> +
> + if (div_id == FSL_SAI_TX_DIV) {
On Fri, 01 Nov 2013 16:08:36 +1100, Benjamin Herrenschmidt
wrote:
> On Fri, 2013-11-01 at 16:03 +1100, NeilBrown wrote:
>
> > Do you mean we could allow multiple devices on the one bus to have the same
> > name, but get sysfs to notice and de-duplicate by mangling one name? I
> > don't
> > thi
On Thu, 31 Oct 2013 11:57:14 -0700, Olof Johansson wrote:
> On Wed, Oct 30, 2013 at 02:25:21PM -0700, Grant Likely wrote:
> > (Sorry for HTML mail)
> >
> > Can you put #define DEBUG at the top of drivers/of/irq.c and send me the
> > log output from before and after the commit?
>
> Here you go, q
On 11/01/2013 10:42 AM, Soren Brinkmann wrote:
> Drivers like clocksource/cadence_ttc and net/macb already use the 'cdns'
> prefix for Cadence IP.
>
> Signed-off-by: Soren Brinkmann
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Applied. Th
Hi Jonas,
On Friday 01 November 2013 08:24 PM, Jonas Jensen wrote:
The MOXA UC-711X hardware(s) has an ethernet controller that seem
to be developed internally. The IC used is "RTL8201CP".
This patch adds an MDIO driver and also patches realtek to include
RTL8201CP PHY driver.
Signed-off-by:
Hi Neil,
While I'm not fundamentally opposed to this binding, I have some issues with
its current form and would not want to see this version hit mainline.
On Fri, Nov 01, 2013 at 09:50:05AM +, NeilBrown wrote:
>
> As this device is not vendor specific, I haven't included any "vendor,"
> pre
On Monday 14 of October 2013 19:08:25 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran
>
> Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> ---
> arch/arm/boot/dts/Makefile| 1 +
> arch/a
On Monday 14 of October 2013 19:08:22 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran
>
> EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
> Add initial support for this SoC.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> ---
> arch/arm/mach-exynos/Kconfig
On 11/01/2013 10:34 AM, Will Deacon wrote:
> On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
>> On 10/31/2013 01:39 PM, Will Deacon wrote:
>>> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
> Hmm. That's interes
On 11/01/2013 10:34 AM, Will Deacon wrote:
> On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
>> On 10/31/2013 01:39 PM, Will Deacon wrote:
>>> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
On 10/31/2013 01:16 PM, Stephen Warren wrote:
> Hmm. That's interes
Hello Jonas,
2013/11/1 Jonas Jensen :
> The MOXA UC-711X hardware(s) has an ethernet controller that seem
> to be developed internally. The IC used is "RTL8201CP".
>
> This patch adds an MDIO driver and also patches realtek to include
> RTL8201CP PHY driver.
>
> Signed-off-by: Jonas Jensen
> ---
Hi,
On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran
>
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> ---
> .../
On 10/31/2013 02:17 AM, Hiroshi Doyu wrote:
> Stephen Warren wrote @ Wed, 30 Oct 2013 23:33:32
> +0100:
...
> Right.
> "memory client ID" is used to find out MC_SMMU__ASID_0
> register. This register is used to associate to address
> space(AS). == H/W. can be attached to any AS.
>
>> Is "swgr
On Fri, Nov 01, 2013 at 04:08:52PM +, Stephen Warren wrote:
> On 10/31/2013 01:39 PM, Will Deacon wrote:
> > On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
> >> On 10/31/2013 01:16 PM, Stephen Warren wrote:
> >>> Hmm. That's interesting. I see that the ARM SMMU has a list of th
The Krait L1/L2 error reporting device is made up of two
interrupts, one per-CPU interrupt for the L1 caches and one
interrupt for the L2 cache.
Cc: Mark Rutland
Acked-by: Kumar Gala
Cc:
Signed-off-by: Stephen Boyd
---
Documentation/devicetree/bindings/arm/cpus.txt | 49 ++
This patchset adds support for the Krait L1/L2 cache error detection
hardware. The first patch fixes a generic framework bug. The next
two patches lay the groundwork for this driver to be added by
exporting percpu irq functions as well as adding the Krait l2 indirection
register code. The next two
Nevermind, didn't read the clk-pll.c properly..
pll_35xx and pl_2550 will default to the same code.
Best Regards,
Mauro
On Fri, Nov 1, 2013 at 1:53 PM, Mauro Ribeiro wrote:
> Is the PLL35xx driver compatible with the ones used on 5410?
>
> +static struct samsung_pll_clock exynos5410_plls[nr_pll
On Thu, Oct 31, 2013 at 5:58 PM, Mark Rutland wrote:
>> + plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
>> + if (!plat)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + of_property_read_u8(np, "keypad,num-columns", &plat->kcol);
>> + of_property_read_u8(np, "keypad,num-r
On 10/31/2013 01:39 PM, Will Deacon wrote:
> On Thu, Oct 31, 2013 at 07:25:25PM +, Stephen Warren wrote:
>> On 10/31/2013 01:16 PM, Stephen Warren wrote:
>>> Hmm. That's interesting. I see that the ARM SMMU has a list of the
>>> clients it affects, whereas this Tegra series puts information int
On 11/01/2013 02:06 AM, Hiroshi Doyu wrote:
> On Thu, 31 Oct 2013 18:46:06 +0100
> Mark Rutland wrote:
>
>> On Thu, Oct 31, 2013 at 08:19:42AM +, Hiroshi Doyu wrote:
>>> Stephen Warren wrote @ Wed, 30 Oct 2013 23:48:38
>>> +0100:
>>>
On 10/18/2013 04:26 AM, Hiroshi Doyu wrote:
> Cr
Is the PLL35xx driver compatible with the ones used on 5410?
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fo
Drivers like clocksource/cadence_ttc and net/macb already use the 'cdns'
prefix for Cadence IP.
Signed-off-by: Soren Brinkmann
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Do
On Fri, 1 Nov 2013, Christophe Leroy wrote:
diff -urN a/drivers/net/wan/pef2256.c b/drivers/net/wan/pef2256.c
[..]
+static int pef2256_remove(struct platform_device *pdev)
+{
+ struct net_device *ndev = dev_get_drvdata(&pdev->dev);
+ struct pef2256_dev_priv *priv = dev_to_hdlc(nd
The patch adds WAN support for Infineon FALC56 - PEF2256 E1 Chipset.
Signed-off-by: Jerome Chantelauze
Acked-by: Christophe Leroy
diff -urN a/drivers/net/wan/pef2256.c b/drivers/net/wan/pef2256.c
--- a/drivers/net/wan/pef2256.c 1970-01-01 01:00:00.0 +0100
+++ b/drivers/net/wan/pef2256.c
The MOXA UC-711X hardware(s) has an ethernet controller that seem
to be developed internally. The IC used is "RTL8201CP".
This patch adds an MDIO driver and also patches realtek to include
RTL8201CP PHY driver.
Signed-off-by: Jonas Jensen
---
Notes:
The hardware does not use a separate IRQ
On Thu, Oct 31, 2013 at 03:13:46PM -0600, Stephen Warren wrote:
> On 10/28/2013 04:17 AM, David Gibson wrote:
> > On Fri, Oct 25, 2013 at 03:44:09PM +0100, Stephen Warren wrote:
> >> On 10/25/2013 12:43 AM, Grant Likely wrote:
> >>> On Thu, 24 Oct 2013 22:51:28 +0100, Stephen Warren
> >>> wrote:
>
On Fri, 01 Nov 2013 14:10:47 +0100, Joerg Roedel wrote:
> Hi Cho,
>
> On Fri, Nov 01, 2013 at 09:37:45PM +0900, Cho KyongHo wrote:
> > I am preparing next patches to apply Alex Williamson's comment that
> > description of IOMMU's masters must be aligned with ARM SMMU.
> >
> > It is delayed due to
On 11/01/2013 03:36 AM, Thierry Reding wrote:
On Thu, Oct 24, 2013 at 08:18:53AM -0700, Guenter Roeck wrote:
On Wed, Oct 23, 2013 at 11:07:16PM +0200, Thierry Reding wrote:
[ ... ]
Was this just a matter of enabling OF on this platform, or do you have an
out-of-tree set of patches ? If the lat
Hi Cho,
On Fri, Nov 01, 2013 at 09:37:45PM +0900, Cho KyongHo wrote:
> I am preparing next patches to apply Alex Williamson's comment that
> description of IOMMU's masters must be aligned with ARM SMMU.
>
> It is delayed due to my jobs in the office.
>
> I will post the next patche series in two
On Wed, Oct 16, 2013 at 03:01:47PM -0700, Tim Kryger wrote:
> Add support for I2C high-speed mode (3.4 MHz).
>
> Signed-off-by: Tim Kryger
> Reviewed-by: Matt Porter
> Reviewed-by: Markus Mayer
Mostly good as well:
> +enum hs_bus_speed_index {
> + BCM_SPD_3P4MHZ = 0,
> +};
I just realize
On 28/10/13 15:02, Maxime Coquelin wrote:
>>
>> 6> IMHO, the compatible string should be "vendor,-"
>> rather than first SoC.
> I agree.
> In this case, we add support to revision 4 of SSC IP.
Its not the revision its name of the new IP which is SSC4. However this
driver is also compatible with ol
On Wed, Oct 16, 2013 at 03:01:46PM -0700, Tim Kryger wrote:
> Introduce support for Broadcom Serial Controller (BSC) I2C bus found
> in the Kona family of Mobile SoCs. FIFO hardware is utilized but only
> standard mode (100kHz), fast mode (400kHz), and fast mode plus (1MHz)
> bus speeds are suppor
On Fri, 01 Nov 2013 12:42:24 +0100, Joerg Roedel wrote:
> On Mon, Oct 07, 2013 at 10:52:12AM +0900, Cho KyongHo wrote:
> > Patch summary:
> > [PATCH 01/20] iommu/exynos: do not include removed header
> > [PATCH 02/20] iommu/exynos: add missing cache flush for removed page table
> > entries
> > [PA
On Fri, Nov 01, 2013 at 06:28:05PM +0800, Nicolin Chen wrote:
> > sound/soc/fsl/fsl-sgtl5000-vf610.c | 208
> > +
>
> I just doubt if this file naming is appropriate. Even if we might not have
> rigor rule for the file names, according to existing ones, they ar
On Mon, Oct 07, 2013 at 10:52:12AM +0900, Cho KyongHo wrote:
> Patch summary:
> [PATCH 01/20] iommu/exynos: do not include removed header
> [PATCH 02/20] iommu/exynos: add missing cache flush for removed page table
> entries
> [PATCH 03/20] iommu/exynos: change error handling when page table updat
Hi,
On Mon, Oct 14, 2013 at 02:46:49PM +0200, Maxime COQUELIN wrote:
> This patch adds support to SSC (Synchronous Serial Controller)
> I2C driver. This IP also supports SPI protocol, but this is not
> the aim of this driver.
>
> This IP is embedded in all ST SoCs for Set-top box platorms, and
>
Not that it would improve functionality, but:
On Fri, Nov 01, 2013 at 15:04:53 +0800, Xiubo Li wrote:
[...]
> diff --git a/sound/soc/fsl/fsl-sgtl5000-vf610.c
> b/sound/soc/fsl/fsl-sgtl5000-vf610.c
> new file mode 100644
> index 000..f535b42
> --- /dev/null
> +++ b/sound/soc/fsl/fsl-sgtl5000-v
Hi Xiubo,
On Fri, Nov 01, 2013 at 03:04:53PM +0800, Xiubo Li wrote:
> This is the SGTL5000 codec based audio driver supported with both
> playback and capture dai link implemention.
>
> This implementation is only compatible with device tree definition.
>
> Signed-off-by: Alison Wang Signed-off
At least one platform (APM Storm) places the two pages of the GIC cpu interface
(and the vcpu side) at non-contiguous locations. Document two additional
regions to cover this split and update the corresponding dtsi. Note that Linux
(including KVM) does not use any registers in the second page so th
GICv2 (Cortex A15/GIC 400) have CPU interface registers up to offset 0x1004
(the 32-bit GICC_DIR register a 0x1000). The GIC 400 documentation specifies
the CPU interface region as being 0x2000 in size.
Update all DTS entries claiming "arm,cortex-a15-gic" compatibility. Of these I
only have person
On Thu, Oct 24, 2013 at 08:18:53AM -0700, Guenter Roeck wrote:
> On Wed, Oct 23, 2013 at 11:07:16PM +0200, Thierry Reding wrote:
> [ ... ]
> > >
> > > Was this just a matter of enabling OF on this platform, or do you have an
> > > out-of-tree set of patches ? If the latter, is it available somewhe
On Fri, Nov 01, 2013 at 03:04:52PM +0800, Xiubo Li wrote:
> On VF610 series there are no regulators used, and now whether the
> CONFIG_REGULATOR mirco is enabled or not, for the VF610 audio
micro? or macro?
> patch series, the board cannot be probe successfully.
> And this patch will solve this i
On Fri, Nov 01, 2013 at 08:37:23AM +0900, Jingoo Han wrote:
> On Wednesday, October 23, 2013 5:02 AM, Thierry Reding wrote:
> > On Tue, Oct 22, 2013 at 05:34:45PM +0200, Jean-Christophe PLAGNIOL-VILLARD
> > wrote:
> > > On 09:23 Tue 22 Oct , Thierry Reding wrote:
> > > > On Tue, Oct 22, 2013 a
Several existing platforms which sport an A15 compatible GIC to not
include the extended GIC cpu interface regisiters in their device tree.
Fix these.
Also extend the bindings to cope with cpu intefface registers which are
not in contiguous pages.
Ian.
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Thierry Reding wrote @ Fri, 1 Nov 2013 10:53:50
+0100:
> * PGP Signed by an unknown key
>
> On Thu, Oct 31, 2013 at 10:37:40AM -0600, Stephen Warren wrote:
> > On 10/31/2013 02:14 AM, Hiroshi Doyu wrote:
> > > Thierry Reding wrote @ Wed, 30 Oct 2013
> > > 23:41:09 +0100:
> > >
> > >> My earl
Thierry Reding wrote @ Fri, 1 Nov 2013 10:52:24
+0100:
> * PGP Signed by an unknown key
>
> On Fri, Nov 01, 2013 at 08:49:09AM +0200, Hiroshi Doyu wrote:
> > On Thu, 31 Oct 2013 18:53:22 +0100
> > Stephen Warren wrote:
> > ...
> > > We're talking about memory-mapped on-SoC devices here, that g
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