Hi,
Jean-Christophe PLAGNIOL-VILLARD wrote:
On 14:17 Fri 08 Nov , Denis Carikli wrote:
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell
Hi Jean Christophe,
Le Thu, 21 Nov 2013 06:05:44 +0100,
Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com a écrit :
+Optional properties:
+- gpios: the interrupt gpio the chip is connected to (trough the penirq
pin).
nack use interrupt property this a non-sense that we do today to
Le Thu, 21 Nov 2013 06:09:22 +0100,
Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com a écrit :
+ tsc2007: tsc2007@48 {
+ compatible = ti,tsc2007;
+ reg = 0x48;
+ interrupt-parent = gpio3;
+ interrupts = 0x2 0x8;
+ gpios = gpio3
On Wed, Nov 20, 2013 at 17:50 -0600, Rob Herring wrote:
On Wed, Nov 20, 2013 at 3:34 PM, Gerhard Sittig g...@denx.de wrote:
re-format and re-word the device tree binding documentation for MPC8xxx
and compatibles, reference the common document for interrupt controllers
and remove outdated
On Thu, Nov 21, 2013 at 01:49 +0100, Arnd Bergmann wrote:
On Wednesday 20 November 2013, Gerhard Sittig wrote:
re-format and re-word the device tree binding documentation for MPC8xxx
and compatibles, reference the common document for interrupt controllers
and remove outdated duplicate SoC
re-format and re-word the device tree binding documentation for MPC8xxx
and compatibles, reference the common document for interrupt controllers
and remove outdated duplicate SoC specific information
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Rob Herring@ rob.herr...@calxeda.com
Cc: Pawel Moll
On 20/11/2013 18:27, Jean-Christophe PLAGNIOL-VILLARD :
On 17:31 Wed 20 Nov , boris brezillon wrote:
On 20/11/2013 16:02, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 14:37 Wed 28 Aug , Boris BREZILLON wrote:
Add a new at91rm9200ek_mmc board (based on at91rm9200ek board) which enables
On Wed, 20 Nov 2013 17:30:35 +0100
Stephen Warren swar...@wwwdotorg.org wrote:
...
Does the above mean the following?
int of_iommu_attach(struct device *dev)
{
int i;
struct of_phandle_args args;
of_property_for_each_phandle_with_args(dev-of_node, iommus,
On Wed, 2013-11-20 at 15:31 +, Mark Brown wrote:
On Wed, Nov 20, 2013 at 03:12:08PM +0100, Krzysztof Kozlowski wrote:
+static irqreturn_t max14577_irq_thread(int irq, void *data)
+{
+ struct max14577 *max14577 = data;
+ u8 irq_reg[MAX14577_IRQ_REGS_NUM] = {0};
+ u8
snip
+/**
+ * After resuming from suspend it may happen that IRQ is signalled but
+ * IRQ GPIO is not high. Also the interrupt registers won't have any data
+ * (all of them equal to 0x00).
+ *
+ * In such case retry few times reading the interrupt registers.
+ */
+#define
When kernel is booted using DT, there is no guarantee that Davinci
NAND device has been created already at the time when driver init
function is executed. Therefore, platform_driver_probe() can't be used
because this may result the Davinci NAND driver will never be probed.
The driver probing has
These patches introduce Async External Memory Interface (EMIF16/AEMIF)
controller driver for Davinci/Keystone archs.
v1..v2:
- added ti.cs-chipselect property instead to represent chipselect
number in cs node name.
Ivan Khoronzhuk (2):
memory: ti-aemif: introduce AEMIF driver
memory:
The problem that the set timings code contains the call of Davinci
platform function davinci_aemif_setup_timing() which is not
accessible if kernel is built for Keystone only.
The Keysone platform is going to use TI AEMIF driver.
If TI AEMIF is used we don't need to set timings and bus width.
It
Extend bindings for davinci_nand driver to be more clear.
This is clarification only, without semantic changes.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
.../devicetree/bindings/mtd/davinci-nand.txt | 77
There is not needed to use a lot of names for err handling.
It complicates code support and reading.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
Add new AEMIF driver for EMIF16 Texas Instruments controller.
The EMIF16 module is intended to provide a glue-less interface to
a variety of asynchronous memory devices like ASRA M, NOR and NAND
memory. A total of 256M bytes of any of these memories can be
accessed at any given time via four chip
Move bindings under mtd. Do this in order to make davinci-nand
driver usable by keystone architecture.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
.../{arm/davinci/nand.txt
This series contains fixes and updates of Davinci nand driver in
order to reuse it for Keystone platform.
The series is combination of two following series:
- Davinci nand driver fixes and updates:
https://lkml.org/lkml/2013/11/20/271
- Reuse davinci-nand driver for Keystone arch
In case when memory allocation is failed the driver should return
ENOMEM instead of ENODEV.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/mtd/nand/davinci_nand.c |5 -
1 file changed, 4 insertions(+), 1
The property ti,davinci-chipselect is required. So we have to check
if it is set.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
Reviewed-by: Grygorii Strashko grygorii.stras...@ti.com
---
drivers/mtd/nand/davinci_nand.c |3 +++
1 file changed, 3 insertions(+)
diff --git
On Thu, 2013-11-21 at 10:34 +, Lee Jones wrote:
snip
+/**
+ * After resuming from suspend it may happen that IRQ is signalled but
+ * IRQ GPIO is not high. Also the interrupt registers won't have any data
+ * (all of them equal to 0x00).
+ *
+ * In such case retry few times
On Thursday 21 November 2013, Loc Ho wrote:
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible : Shall be apm,xgene-ahci
+- reg:
Thanks for pointing these out however after using regmap_irq_chip whole
file won't be needed anymore.
That's fine.
+static int max14577_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ struct max14577 *max14577;
+ struct
On Tue, 19 Nov 2013 12:12:26 +0100, Geert Uytterhoeven ge...@linux-m68k.org
wrote:
Let early_init_dt_scan() fall-back to the built-in DT if no DT was passed,
or if it's invalid, so architectures don't have to duplicate this logic.
Suggested-by: Rob Herring rob.herr...@calxeda.com
On Thu, Nov 21, 2013 at 10:51:09AM -0800, Olof Johansson wrote:
An ack from Russell would be appreciated, or we'd need to set up a
shared branch given the Tegra dependencies that would go on top.
Either is ok with me.
Note that I'm *not* looking at anything new until after the merge window
has
On Thu, Oct 31, 2013 at 1:15 PM, Vivek Gautam gautam.vi...@samsung.com wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Signed-off-by: Vivek Gautam
On Thu, 2013-11-21 at 12:20 +, Lee Jones wrote:
(...)
+struct max14577_regulator_platform_data {
+ int id;
+ struct regulator_init_data *initdata;
+ struct device_node *of_node;
Do you ever set this? What's the point of it is it's set in the device?
From: Lad, Prabhakar prabhakar.cse...@gmail.com
Signed-off-by: Lad, Prabhakar prabhakar.cse...@gmail.com
[grygorii.stras...@ti.com:
- switch to use one irq-domain per all GPIO banks
- keep irq_create_mapping() call in gpio_to_irq_banked() as it
simply transformed to irq_find_mapping() if
On Nov 20, 2013, at 5:56 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Nov 20, 2013 at 11:55 AM, Grant Likely
grant.lik...@secretlab.ca wrote:
To help keep track of what is going on, I would like to have a short
stand up meeting once a week. Looking at my calendar, I can make
On 21 November 2013 15:20, Balaji T K balaj...@ti.com wrote:
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4
This provides the info about which swgroups a device belongs to. This
info is passed from DT. This is necessary for the unified SMMU driver
among Tegra SoCs since each has different H/W accelerators.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6:
- Explained #iommu-cells in the binding
From: Lad, Prabhakar prabhakar.cse...@gmail.com
This patch replaces the __raw_readl/writel with
readl and writel, Altough the code runs on ARMv5
based SOCs, changing this will help copying the code
for other uses.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Lad, Prabhakar
On Thu, Nov 21, 2013 at 6:47 AM, Grant Likely grant.lik...@linaro.org wrote:
On Wed, 30 Oct 2013 01:12:50 -0500, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Introduce a helper to match, create and probe a platform device. This
is for drivers such as
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
On Tue, 19 Nov 2013 11:30:15 +, Mark Rutland mark.rutl...@arm.com wrote:
On Fri, Nov 15, 2013 at 05:52:41PM +, Olof Johansson wrote: On Fri,
Nov 15, 2013 at 09:57:17AM +, Mark Rutland wrote:
On Fri, Nov 15, 2013
NETGEAR ReadyNAS 104 has a NXP PCA9554 I2C to GPIO chip. Among the 8 GPIO
lines the chip makes available, four are used on the device to control
the SATA LEDs (the four remaining ones are used for SATA disk presence).
This patch adds DT entries for NXP PCA9554 and the four SATA GPIO LEDs.
Mux mode for wlan/sdmmc5 should be MODE0 in pinmux_wl12xx_pins and
Enable Pull up on sdmmc5_clk to detect SDIO card.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/boot/dts/omap4-sdp.dts | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git
ops-{bound,unbind}_driver() functions are called at
BUS_NOTIFY_{BOUND,UNBIND}_DRIVER respectively.
This is necessary to control the device population order. IOMMU master
devices depend on an IOMMU device instanciation. IOMMU master devices
can be registered to an IOMMU only after it's
:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/180267.html
Available in the git repository at:
git://g...@nv-tegra.nvidia.com/user/hdoyu/linux.git smmu-upstreaming@20131121
Hiroshi Doyu (13):
of: introduce of_property_for_earch_phandle_with_args()
iommu/of: introduce
Without that fix, at the end of the shutdown process, the board is
still powered (led glowing, fan running, ...).
Signed-off-by: Arnaud Ebalard a...@natisbad.org
---
Hi,
I have prepared some cleanup patches for existing ReadyNAS .dts files
which I intend to send for review in the next fex days.
On 20-11-2013 08:32, Pavel Machek wrote:
HI!
This patch changes the dtsi entry on omap4430 to contain
the thermal data. This data will enable the passive
cooling with CPUfreq cooling device at 100C and the
system will do a thermal shutdown at 125C.
Cc: Benoît Cousson bcous...@baylibre.com
On Thu, 21 Nov 2013 16:33:13 -0600, Rob Herring robherri...@gmail.com wrote:
On Thu, Nov 21, 2013 at 6:47 AM, Grant Likely grant.lik...@linaro.org wrote:
On Wed, 30 Oct 2013 01:12:50 -0500, Rob Herring robherri...@gmail.com
wrote:
From: Rob Herring rob.herr...@calxeda.com
Introduce a
On Thu, 21 Nov 2013 14:42:27 +0100, Geert Uytterhoeven ge...@linux-m68k.org
wrote:
On Thu, Nov 21, 2013 at 1:21 PM, Grant Likely grant.lik...@secretlab.ca
wrote:
bool __init early_init_dt_scan(void *params)
{
- if (!params)
- return false;
-
/* Setup flat
On Thu, Nov 21, 2013 at 10:54 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Nov 21, 2013 at 09:58:22AM -0800, Olof Johansson wrote:
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
We are pushing a lot of boundaries and doing things on ACPI that have
never
Hi Tony,
On Thu, Nov 21, 2013 at 10:51:06AM -0800, Tony Lindgren wrote:
Looks like we need to configure the regulators and use the pdata
quirk to make eMMC work with device tree.
It seems that mostly vmmc2 is used, and only some earlier revisions
like the macro board used vaux3.
Note
On Wed, 30 Oct 2013 15:02:40 -0500, Rob Herring robherri...@gmail.com wrote:
On Wed, Oct 30, 2013 at 3:26 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Wed, Oct 30, 2013 at 01:12:49AM -0500, Rob Herring wrote:
From: Rob Herring rob.herr...@calxeda.com
This series adds a couple of
On Thu, Nov 21, 2013 at 6:50 AM, Grant Likely grant.lik...@linaro.org wrote:
On Wed, 30 Oct 2013 01:12:51 -0500, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Add boilerplate helpers to create initcalls which are conditional on
matching on devicetree
On Fri, 15 Nov 2013 23:21:09 +, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Nov 15, 2013 at 08:56:47PM +0100, Arnd Bergmann wrote:
On Friday 15 November 2013, Russell King - ARM Linux wrote:
On Fri, Nov 15, 2013 at 09:52:41AM -0800, Olof Johansson wrote:
If we
On Thursday 21 November 2013, Olof Johansson wrote:
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
We are pushing a lot of boundaries and doing things on ACPI that have
never been done before. SPI, GPIOs, Clocks, Regulators, composite
devices, key-value properties. All brand
On Thu, Nov 21, 2013 at 09:58:22AM -0800, Olof Johansson wrote:
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
We are pushing a lot of boundaries and doing things on ACPI that have
never been done before. SPI, GPIOs, Clocks, Regulators, composite
devices, key-value
On Nov 21, 2013, at 1:35 PM, Jason Cooper ja...@lakedaemon.net wrote:
Unlike other build products in the Linux kernel, there is no 'make
*install' mechanism to put devicetree blobs in a standard place.
This patch is an attempt to fix this problem. Akin to 'make install',
this creates a
remove pbias workaround
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 20 +---
1 files changed, 1 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 0a390f8..0f0aa5d 100644
---
On Thu, Nov 21, 2013 at 11:20 AM, Hiroshi Doyu hd...@nvidia.com wrote:
Grant Likely grant.lik...@linaro.org wrote @ Thu, 21 Nov 2013 16:56:49
+0100:
On Thu, 21 Nov 2013 15:12:18 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
On Thu, 21 Nov 2013 13:43:28 +0100
Grant Likely
IOMMU devices on the bus need to be poplulated first, then iommu
master devices are done later.
With CONFIG_OF_IOMMU, iommus= DT binding would be used to identify
whether a device can be an iommu msater or not. If a device can, we'll
defer to populate that device till an iommu device is
On Thu, Nov 21, 2013 at 3:31 PM, Kumar Gala ga...@codeaurora.org wrote:
On Nov 21, 2013, at 1:35 PM, Jason Cooper ja...@lakedaemon.net wrote:
Unlike other build products in the Linux kernel, there is no 'make
*install' mechanism to put devicetree blobs in a standard place.
This patch is an
On Thu, 17 Oct 2013 13:12:28 +0100, Dave Martin dave.mar...@arm.com wrote:
On Mon, Oct 14, 2013 at 03:52:27PM +0530, Majunath Goudar wrote:
This patch adds a inline dummy implementations of_find_matching_node()
in #ifdef CONFIG_OF else part. Without this patch,build system can
lead to
On Thu, Nov 21, 2013 at 12:46:55PM -0800, Tony Lindgren wrote:
* Sebastian Reichel s...@debian.org [131120 18:22]:
On Wed, Nov 20, 2013 at 05:38:59PM -0800, Tony Lindgren wrote:
In the public documentation of the omaps all SSI related stuff is
missing and memory areas are marked as
On 11/21/2013 10:20 AM, Hiroshi Doyu wrote:
Grant Likely grant.lik...@linaro.org wrote @ Thu, 21 Nov 2013 16:56:49
+0100:
On Thu, 21 Nov 2013 15:12:18 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
On Thu, 21 Nov 2013 13:43:28 +0100
Grant Likely grant.lik...@linaro.org wrote:
On Tue, 19 Nov
This driver adds support for digital audio (I2S)
for the BCM2835 SoC that is used by the
Raspberry Pi. External audio codecs can be
connected to the Raspberry Pi via P5 header.
It relies on cyclic DMA engine support for BCM2835.
Signed-off-by: Florian Meier florian.me...@koalo.de
---
Minor
Grant Likely grant.lik...@linaro.org wrote @ Thu, 21 Nov 2013 16:56:49 +0100:
On Thu, 21 Nov 2013 15:12:18 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
On Thu, 21 Nov 2013 13:43:28 +0100
Grant Likely grant.lik...@linaro.org wrote:
On Tue, 19 Nov 2013 11:33:05 +0200, Hiroshi Doyu
Enable REGULATOR_PBIAS needed for SD card on most OMAPs.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/configs/omap2plus_defconfig |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig
b/arch/arm/configs/omap2plus_defconfig
index
Add pbias-supply to mmc1/sd card.
Signed-off-by: Balaji T K balaj...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts|1 +
arch/arm/boot/dts/omap3-beagle-xm.dts |1 +
arch/arm/boot/dts/omap3-beagle.dts|1 +
arch/arm/boot/dts/omap3-devkit8000.dts|1 +
This allows to inquire if SMMU is populated or not.
Suggested by Thierry Reding and copied his example code.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
Cc: Thierry Reding thierry.red...@gmail.com
---
v6:
New for v6.
---
drivers/iommu/tegra-smmu.c | 55
On Fri, Oct 4, 2013 at 3:25 PM, Linus Walleij linus.wall...@linaro.org wrote:
The Versatile FPGA interrupt controller supports cascading interrupts,
i.e. that its output is connected to the input of another interrupt
controller. This makes it possible to pass a parent interrupt from
the
* Sebastian Reichel s...@debian.org [131120 18:22]:
On Wed, Nov 20, 2013 at 05:38:59PM -0800, Tony Lindgren wrote:
In the public documentation of the omaps all SSI related stuff is
missing and memory areas are marked as reserved. I could not find
out how to receive the NDA version, so the
On Thu, Nov 21, 2013 at 4:53 PM, Grant Likely grant.lik...@secretlab.ca wrote:
My changes don't change the current behavior much: currently
early_init_dt_scan() is already called with __dtb_start in several places.
If this is broken, it's already broken.
Yes, but it is called on platforms
On 11/21/2013 10:58 AM, Tony Lindgren wrote:
* Balaji T K balaj...@ti.com [131121 05:51]:
pin mux wl12xx_gpio and wl12xx_pins should be part of omap4_pmx_core
and not omap4_pmx_wkup. So, move wl12xx_* to omap4_pmx_core.
Fix the following error message:
pinctrl-single 4a31e040.pinmux: mux
On Mon, 18 Nov 2013 15:19:01 +, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
They are using strings which are the same as the DT properties, but
without the vendor prefix - but yes, to only retrieve things like
booleans, u32s and such like. They also have support for fixed-rate
On Tue, 19 Nov 2013 11:33:05 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
The following pattern of code is tempting:
for (i = 0; !of_parse_phandle_with_args(np, list, cells, i, args); i++)
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
That's a very minimal commit message. Can you elaborate
iommus binding implies that a device can be attached to IOMMU
devices. An iommu device needs to set #iommus-cells in it. iommus
can have multiple iommu device phandles as below if needed.
iommus = smmu arg1 arg2,
gart arg1 arg2;
Not yet ready for merge. Need to add iommus for other
* Balaji T K balaj...@ti.com [131121 06:21]:
Add pbias-supply to mmc1/sd card.
...
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -261,6 +261,7 @@
mmc1 {
status = okay;
vmmc-supply = ldo1_reg;
+ pbias-supply = pbias_regulator;
From: KV Sujith sujit...@ti.com
Add GPIO DT node and pinmux entries for DA850 EVM. GPIO is
configurable differently on different boards. So add GPIO
pinmuxing in dts file.
Signed-off-by: KV Sujith sujit...@ti.com
Signed-off-by: Philip Avinash avinashphi...@ti.com
Signed-off-by: Lad, Prabhakar
On Thu, 21 Nov 2013 17:01:22 +, Matthew Garrett mj...@srcf.ucam.org wrote:
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
Personally, I think the issue of ACPI support should be taken on a
patch-by-patch basis. A lot of the things that need to be done are quite
discrete
Linus
On Thu, 21 Nov 2013, Linus Walleij wrote:
On Fri, Oct 4, 2013 at 3:25 PM, Linus Walleij linus.wall...@linaro.org
wrote:
The Versatile FPGA interrupt controller supports cascading interrupts,
i.e. that its output is connected to the input of another interrupt
controller. This
On 11/21/2013 12:35 PM, Jason Cooper wrote:
Unlike other build products in the Linux kernel, there is no 'make
*install' mechanism to put devicetree blobs in a standard place.
This patch is an attempt to fix this problem. Akin to 'make install',
this creates a new make target, dtbs_install.
On Wed, 30 Oct 2013 01:12:50 -0500, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Introduce a helper to match, create and probe a platform device. This
is for drivers such as cpuidle or cpufreq that typically don't have a
bus device node and need to match
On 11/21/2013 06:15 AM, Grant Likely wrote:
On Tue, 19 Nov 2013 11:33:06 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
IOMMU devices on the bus need to be poplulated first, then iommu
master devices are done later.
With CONFIG_OF_IOMMU, iommus= DT binding would be used to identify
whether a
On Thu, 21 Nov 2013 15:12:18 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
On Thu, 21 Nov 2013 13:43:28 +0100
Grant Likely grant.lik...@linaro.org wrote:
On Tue, 19 Nov 2013 11:33:05 +0200, Hiroshi Doyu hd...@nvidia.com wrote:
The following pattern of code is tempting:
for (i = 0;
On Wed, Nov 20, 2013 at 07:40:57AM +0100, Richard Cochran wrote:
Now, I never saw any proclamation or discussion about DT is in flux
on the arm list. If I had, I surely would have complained, and loudly.
AFAICT, this decision was made in rather private circles, but you talk
as if this was
On 11/21/2013 12:00 PM, Russell King - ARM Linux wrote:
On Thu, Nov 21, 2013 at 10:51:09AM -0800, Olof Johansson wrote:
An ack from Russell would be appreciated, or we'd need to set up a
shared branch given the Tegra dependencies that would go on top.
Either is ok with me.
Note that I'm
This enables to find an populated IOMMU device via a device node. This
can be used to see if an dependee IOMMU is populated or not to keep
correct device population order. Client devices need to wait an IOMMU
to be populated.
Suggested by Thierry Reding and copied his example code.
On Thu, Nov 21, 2013 at 04:29:44PM +, Grant Likely wrote:
Personally, I think the issue of ACPI support should be taken on a
patch-by-patch basis. A lot of the things that need to be done are quite
discrete and fairly well contained. If the patches don't look that way
then push back on
On Wed, 2013-11-20 at 18:58 +0100, Bartlomiej Zolnierkiewicz wrote:
Err..
I'm missing something obvious info is redundant and can be removed
altogether.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung RD Institute Poland
Samsung Electronics
+ for (i = 0; i
On Thu, 21 Nov 2013 14:23:22 +0100
Grant Likely grant.lik...@linaro.org wrote:
+static int smmu_iommu_add_device(struct device *dev)
+{
+ int err = -EPROBE_DEFER;
+ u32 swgroups = dev-platform_data;
+ struct dma_iommu_mapping *map = NULL;
+
+ if (test_bit(TEGRA_SWGROUP_PPCS,
On 21-11-2013 10:57, Tomasz Figa wrote:
On Friday 15 of November 2013 09:19:02 Eduardo Valentin wrote:
Hello Tomasz,
On 14-11-2013 09:40, Tomasz Figa wrote:
On Thursday 14 of November 2013 07:31:04 Eduardo Valentin wrote:
On 13-11-2013 12:57, Tomasz Figa wrote:
Hi Eduardo,
Hello Tomaz
Looks like we need to configure the regulators and use the pdata
quirk to make eMMC work with device tree.
It seems that mostly vmmc2 is used, and only some earlier revisions
like the macro board used vaux3.
Note that we can add support for the macro board later as needed
by including the common
From: Lad, Prabhakar prabhakar.cse...@gmail.com
As the davinci-gpio driver is migrated to use irqdomain
there is no need to pass the irq base for the gpio driver.
This patch removes this variable from davinci_gpio_platform_data
and also the refrences from the machine file.
Signed-off-by: Lad,
ASID register offset is caclulated by SWGROUP ID so that we can get
rid of old SoC specific MACROs. This ID conversion is needed for the
unified SMMU driver over Tegra SoCs. We use dt-bindings MACRO instead
of SoC dependent MACROs. The formula is:
MC_SMMU_swgroup name_ASID_0 =
Hi Mark,
Sorry for the delay, but I was somehow removed from the recipients in
your reply. As I am not subscribed to rtc-linux, can you keep me in Cc:
next time?
On Mon, Nov 18, 2013 at 09:51:27PM +0100, Arnaud Ebalard wrote:
+/* Block read. Returns 0 on success, or a negative errno. */
On Wed, 2013-11-20 at 11:56 +, Grant Likely wrote:
On Wed, Nov 20, 2013 at 11:55 AM, Grant Likely
grant.lik...@secretlab.ca wrote:
To help keep track of what is going on, I would like to have a short
stand up meeting once a week. Looking at my calendar, I can make
14:00UTC on Tuesday,
Hello,
On ODROID-XU XOMCCI is connected to VDD.
Best Regards,
Mauro
On Wed, Nov 20, 2013 at 10:54 PM, Tarek Dakhran t.dakh...@samsung.com wrote:
Hi,
On 20.11.2013 03:23, Tomasz Figa wrote:
Hi,
On Thursday 07 of November 2013 12:12:45 Vyacheslav Tyrtov wrote:
The series of patches
On Thursday 21 November 2013, Grant Likely wrote:
This too should look transparent to device drivers. DT and ACPI have
different mechanism for doing cross tree references, but the concept is
the same. A driver calling something like platform_get_my_gpio_resource()
should do the right thing
On Tue, 19 Nov 2013 11:30:15 +, Mark Rutland mark.rutl...@arm.com wrote:
On Fri, Nov 15, 2013 at 05:52:41PM +, Olof Johansson wrote: On Fri,
Nov 15, 2013 at 09:57:17AM +, Mark Rutland wrote:
On Fri, Nov 15, 2013 at 01:44:10AM +, Olof Johansson wrote:
The UEFI spec pulls in
On Thursday 21 November 2013, Loc Ho wrote:
+struct xgene_ahci_context {
+ struct ahci_host_priv hpriv;
+ struct device *dev;
+ int irq;/* IRQ */
+ void __iomem *csr_base; /* CSR base address of IP */
+ u64 csr_phys; /* Physical address of CSR
Hi Linus,
On 21/11/2013 10:48, Linus Walleij wrote:
On Wed, Nov 20, 2013 at 5:14 PM, boris brezillon
b.brezil...@overkiz.com wrote:
On 20/11/2013 15:59, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 13:06 Wed 28 Aug , Boris BREZILLON wrote:
mmc0_slot0_switch-0 {
+
On Thu, Nov 21, 2013 at 6:28 AM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On 11/20/2013 10:48 PM, Alan Tull wrote:
From: Jamie Iles ja...@jamieiles.com
The Synopsys DesignWare block is used in some ARM devices (picoxcell)
and can be configured to provide multiple banks of
Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
binding. swgroup is a group of H/W clients which a Tegra SoC
supports. This unique ID can be used to calculate MC_SMMU_swgroup
name_ASID_0 register offset and MC_swgroup name_HOTRESET_*_0
register bit. This will allow the same
Iterating over a property containing a list of phandles with arguments
is a common operation for device drivers. This patch adds a new
of_property_for_each_phandle_with_args() macro to make the iteration
simpler.
Signed-off-by: Hiroshi Doyu hd...@nvidia.com
---
v6+:
Use the description, which
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c
On Thu, Nov 21, 2013 at 10:59:41AM -0800, Olof Johansson wrote:
On Thu, Nov 21, 2013 at 10:54 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
This depends what you want from ACPI, and what market ACPI is being
targetted at.
We're talking ACPI on servers here.
Now read the rest
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