On Thu, Jan 09, 2014 at 08:09:09PM +0800, Zhou Zhu wrote:
Sascha/Jingoo,
Thank you for your review!
On 01/09/2014 03:43 PM, Jingoo Han wrote:
On Thursday, January 09, 2014 4:32 PM, Sascha Hauer wrote:
On Thu, Jan 09, 2014 at 01:13:14PM +0800, Zhou Zhu wrote:
add device tree support for mmp
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299a (kbuild: create an include chroot for DT bindings)
merged in v3.10-rc1 for
Hi,
Pankaj Dubey wrote:
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299a (kbuild: create an include chroot for DT bindings)
On 01/10/2014 01:15 AM, Felipe Balbi wrote:
Hi,
On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
So, bad luck number release for this, as v12 wasn't sufficient still.
Changes compared to previous version:
- Dropped any changes to generic clock drivers, as it seems impossible
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
controller that supports:
- 12 channels playback and 8 channels record.
[ Some of the inner transmitters and receivers are sharing same group of
pins. So the maxmium 12 output or 8 input channels are only valid if
Replace /include/ (dtc) with #include (C pre-processor) for all ARM64
based SoC dts files.
Pankaj Dubey (2):
arm64: dts: use #include for all AppliedMicro device tree files
arm64: dts: use #include for all ARM fast model device tree file
arch/arm64/boot/dts/apm-mustang.dts|2 +-
convert /include/ (dtc) with #include (C pre-processor) for
device tree files of AppliedMicro boards.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm64/boot/dts/apm-mustang.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
convert /include/ (dtc) with #include (C pre-processor) for
device tree file of ARM fast model.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
---
arch/arm64/boot/dts/rtsm_ve-aemv8a.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add the necessary entries required for S2MPA01 multi-function
device. While at it also convert whitespaces to tabs in core.h.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
* Fixed nits pointed out by Lee.
---
drivers/mfd/sec-core.c | 45 +++-
Russell,
On Thu, Jan 09, 2014 at 03:01:41PM +, Russell King - ARM Linux wrote:
Sascha, your messages have the Mail-Followup-To: header...
Mail-Followup-To: Nicolin Chen guangyu.c...@freescale.com,
shawn@linaro.org, ker...@pengutronix.de,
On Thu, 09 Jan 2014, Roger Quadros wrote:
The omap-usb-host driver expects certained named clocks.
Add this information to the DT binding document.
Use clock names as per function for reference clocks.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Use devm_clk_get() instead of clk_get().
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/mfd/omap-usb-host.c | 81
+
1 file changed, 16 insertions(+), 65
Hi,
On 01/09/2014 09:36 PM, Alan Stern wrote:
On Thu, 9 Jan 2014, Hans de Goede wrote:
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree, and enabling / disabling
those on power_on / off.
This should allow using
On 10 January 2014 15:33, Lee Jones lee.jo...@linaro.org wrote:
Add the necessary entries required for S2MPA01 multi-function
device. While at it also convert whitespaces to tabs in core.h.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
* Fixed nits pointed out by Lee.
---
Hi Thomas,
The Exynos4210 specific cpufreq driver performs read/write operations
of clock controller registers bypassing the Exynos common clock
framework driver. This could lead to potential issues if CCF and
cpufreq driver modify the clock registers independently of each other.
In addition
Not all revisions have all the clocks so get the necessary clocks
based on hardware revision.
This should avoid un-necessary clk_get failure messages that were
observed earlier.
Be more strict and always fail on clk_get() error.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz
Hi Thomas,
In order to use the cpufreq-cpu0 driver on Exynos4 based platforms,
statically add the platform device for cpufreq-cpu0 platform driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/mach-exynos4-dt.c |6 ++
1 files changed, 6
On Fri, 10 Jan 2014, Sachin Kamat wrote:
On 10 January 2014 15:33, Lee Jones lee.jo...@linaro.org wrote:
Add the necessary entries required for S2MPA01 multi-function
device. While at it also convert whitespaces to tabs in core.h.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
On 01/10/2014 06:22 PM, Lothar Waßmann wrote:
Hi,
Pankaj Dubey wrote:
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299a (kbuild:
Hi Thomas,
Add CPU nodes for Exynos4210 SoC and also properties required by the
cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6 ++
arch/arm/boot/dts/exynos4210-trats.dts |6 ++
Hi Thomas,
I've investigated the topic for a while, so if you don't mind I will
share my thoughts :-)
The patch series removes the use of Exynos4210 specific cpufreq driver
and enables to use the cpufreq-cpu0 driver for Exynos4210 based
platforms. This is being done for few reasons.
(a)
On Thu, Jan 09, 2014 at 08:52:21PM +, Stephen Boyd wrote:
On 01/08/14 02:05, Lorenzo Pieralisi wrote:
On Tue, Jan 07, 2014 at 08:12:39PM +, Stephen Boyd wrote:
On 01/07, Lorenzo Pieralisi wrote:
I have a problem with the cache level definition, and in
particular the numbering,
Hi,
Pankaj Dubey wrote:
On 01/10/2014 06:22 PM, Lothar Waßmann wrote:
Hi,
Pankaj Dubey wrote:
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant
On Thu, Jan 09, 2014 at 07:57:12PM +, Stephen Boyd wrote:
(Adding DT reviewers)
On 01/09/14 03:04, Will Deacon wrote:
On Wed, Jan 08, 2014 at 10:59:40PM +, Stephen Boyd wrote:
+static int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ u32 id = read_cpuid_id() 0xff00;
+
On Thu, Jan 09, 2014 at 04:49:03PM +, Vladimir Barinov wrote:
Add Maxim ModelGauge ICs gauge driver for MAX17040/41/43/44/48/49/58/59 chips
Signed-off-by: Vladimir Barinov vladimir.bari...@cogentembedded.com
---
drivers/power/Kconfig|8
Hi Arnd,
Am Mittwoch, den 08.01.2014, 17:08 +0100 schrieb Arnd Bergmann:
On Wednesday 08 January 2014, Philipp Zabel wrote:
+= GPIO Reset consumers =
+
+For the common case of reset lines controlled by GPIOs, the GPIO binding
+documented in devicetree/bindings/gpio/gpio.txt should be
On Fri, Jan 10, 2014 at 11:01:06AM +1000, Ben Peddell wrote:
It appears the initrd address in the devicetree structure (which is
filled in from what is passed by the bootloader when
CONFIG_ARM_ATAG_DTB_COMPAT is set) is processed _after_ the address in
the initrd= kernel parameter is
On Wed, Jan 08, 2014 at 02:51:46PM +, Balaji T K wrote:
On Tuesday 07 January 2014 05:53 PM, Balaji T K wrote:
On Tuesday 07 January 2014 04:27 PM, Mark Rutland wrote:
On Tue, Jan 07, 2014 at 10:18:15AM +, Balaji T K wrote:
On Monday 06 January 2014 11:49 PM, Mark Rutland wrote:
Hi Lukasz,
On Fri, Jan 10, 2014 at 4:02 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
I've investigated the topic for a while, so if you don't mind I will
share my thoughts :-)
Sure. Thanks for having a look at this patch series.
The patch series removes the use of
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary
among Exynos SoCs. A CPU clock provider can be composed of clock mux,
dividers and gates. This patch defines a new clock type for CPU clock
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core, div_core,
div_core2, div_corem0, div_corem1, div_periph, div_atb, div_pclk_dbg,
div_copy and div_hpm. This composition of mutiple components into
a single
Hi Thomas,
On some platforms such as the Samsung Exynos, changing the frequency
of the CPU clock requires changing the frequency of the PLL that is
supplying the CPU clock. To change the frequency of the PLL, the CPU
clock is temporarily reparented to another parent clock.
Please look into
Hi Lukasz,
On Fri, Jan 10, 2014 at 4:02 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Add CPU nodes for Exynos4210 SoC and also properties required by the
cpufreq-cpu0 driver.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary
among Exynos SoCs. A CPU clock provider can be
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core, div_core,
div_core2, div_corem0, div_corem1, div_periph, div_atb,
On 2013-11-08 15:01, Denis Carikli wrote:
Without that fix, drivers using the fb_videomode_from_videomode
function will not be able to get certain information because
some DISPLAY_FLAGS_* have no corresponding FB_SYNC_*.
diff --git a/include/linux/fb.h b/include/linux/fb.h
index
On Fri, Jan 10, 2014 at 02:37:40PM +0200, Tomi Valkeinen wrote:
I don't think this is better than the previous version where
FB_SYNC_DE_HIGH_ACT and FB_SYNC_PIXDAT_HIGH_ACT were in
include/uapi/linux/fb.h. Now those flag defines are not visible to the
userspace, but the actual flags are still
On Fri, Jan 10, 2014 at 05:54:06PM +0800, Nicolin Chen wrote:
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
controller that supports:
Applied, thanks.
signature.asc
Description: Digital signature
I just received the 'applied' mail. But still want to confirm this topic to
see how to refine the driver in the step ahead.
On Fri, Jan 10, 2014 at 12:04:39PM +, Mark Brown wrote:
On Fri, Jan 10, 2014 at 10:35:39AM +0800, Nicolin Chen wrote:
Resent this because of losing attached file.
Hi Dinh,
On Fri, January 10, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
The CPU clock provider supplies the clock to the CPU clock domain.
The composition and organization of the CPU clock provider could
vary among Exynos SoCs. A CPU clock
On Fri, Jan 10, 2014 at 09:03:39PM +0800, Nicolin Chen wrote:
On Fri, Jan 10, 2014 at 12:04:39PM +, Mark Brown wrote:
This is about what I'd expect but then surely the next step is for the
driver to choose a defualt BCLK ratio - that's how most drivers work,
they try to generate the
Hi,
On 10.01.2014 03:41, Olof Johansson wrote:
On Thu, Jan 9, 2014 at 6:41 PM, Shawn Guo shawn@linaro.org wrote:
On Sat, Jan 04, 2014 at 09:10:58AM +0800, Shawn Guo wrote:
On Fri, Jan 03, 2014 at 11:29:35AM -0800, Olof Johansson wrote:
On Thu, Jan 2, 2014 at 7:04 PM, Shawn Guo
Hi Zhangfei,
On Thursday, January 09, 2014, Zhangfei Gao wrote:
Add dw_mmc-k3.c for k3v2, support sd/emmc
Signed-off-by: Zhangfei Gao zhangfei@linaro.org
Signed-off-by: Zhigang Wang brooke.wangzhig...@huawei.com
---
.../devicetree/bindings/mmc/k3-dw-mshc.txt | 60 +
Hello,
thank you for the review.
On 01/10/2014 02:56 PM, Mark Rutland wrote:
On Thu, Jan 09, 2014 at 04:49:04PM +, Vladimir Barinov wrote:
These bindings can be used to register Maxim ModelGauge ICs fuel gauge
(MAX17040/41/43/44/48/49/58/59)
Signed-off-by: Vladimir
On 01/10/2014 09:39 PM, Seungwon Jeon wrote:
+static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
+{
+struct dw_mci_k3_priv_data *priv = host-priv;
+u32 rate = priv-clk_table[ios-timing];
First, sorry for quick review even though your effort.
But I still worry
On 10/01/14 21:28, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 11:01:06AM +1000, Ben Peddell wrote:
It appears the initrd address in the devicetree structure (which is
filled in from what is passed by the bootloader when
CONFIG_ARM_ATAG_DTB_COMPAT is set) is processed _after_ the
On Friday 10 January 2014, Lee Jones wrote:
- need_logic_fck = false;
+ /* Set all clocks as invalid to begin with */
+ omap-ehci_logic_fck = omap-init_60m_fclk = ERR_PTR(-EINVAL);
+ omap-utmi_p1_gfclk = omap-utmi_p2_gfclk = ERR_PTR(-EINVAL);
+ omap-xclk60mhsp1_ck
Hi Thomas,
Hi Lukasz,
On Fri, Jan 10, 2014 at 5:34 PM, Lukasz Majewski
l.majew...@samsung.com wrote:
Hi Thomas,
Add a new clock provider for ARM clock domain. This clock provider
is composed of multiple components which include mux_core,
div_core, div_core2, div_corem0, div_corem1,
From: Lars Poeschel poesc...@lemonage.de
This adds interrupt functionality for i2c chips to the driver.
They can act as a interrupt-controller and generate interrupts, if
the inputs change.
This is tested with a mcp23017 chip on an arm based platform.
v2:
- some more word about irq-mirror
On Thursday 09 January 2014 04:26 PM, Roger Quadros wrote:
From: Balaji T K balaj...@ti.com
Some platforms have a PHY hooked up to the
SATA controller. The PHY needs to be initialized
and powered up for SATA to work. We do that
using the PHY framework.
[Roger Q] Cleaned up.
CC: Tejun
On Fri, 10 Jan 2014, Arnd Bergmann wrote:
On Friday 10 January 2014, Lee Jones wrote:
- need_logic_fck = false;
+ /* Set all clocks as invalid to begin with */
+ omap-ehci_logic_fck = omap-init_60m_fclk = ERR_PTR(-EINVAL);
+ omap-utmi_p1_gfclk =
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
On 10/01/14 21:28, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 11:01:06AM +1000, Ben Peddell wrote:
It appears the initrd address in the devicetree structure (which is
filled in from what is passed by the bootloader
Hello,
On 01/10/2014 03:11 PM, Mark Rutland wrote:
On Thu, Jan 09, 2014 at 04:49:03PM +, Vladimir Barinov wrote:
Add Maxim ModelGauge ICs gauge driver for MAX17040/41/43/44/48/49/58/59 chips
Signed-off-by: Vladimir Barinovvladimir.bari...@cogentembedded.com
---
drivers/power/Kconfig
On 01/10/14 15:25, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
** MARVELL BOARD: Synology Disk Station LE
U-Boot 1.1.4 (Jul 6 2010 - 19:26:08) Marvell version: 3.4.4
U-Boot code: 0060 - 0067FFF0 BSS: - 0068B43C
Soc: 88F6281 A1 (DDR2)
CPU running @
On Sat, Jan 11, 2014 at 12:38:25AM +1000, Ben Peddell wrote:
On 11/01/14 00:25, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
On 10/01/14 21:28, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 11:01:06AM +1000, Ben Peddell wrote:
It appears the
On 11/01/14 00:25, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
On 10/01/14 21:28, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 11:01:06AM +1000, Ben Peddell wrote:
It appears the initrd address in the devicetree structure (which is
filled in
On Fri, Jan 10, 2014 at 03:25:48PM +0100, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
Bytes transferred = 1954736 (1dd3b0 hex)
Marvell setenv bootargs console=ttyS0,115200 ip=off
initrd=0x00800040,0x0013FFC0 root=/dev/md0 rw syno_hw_version=DS211j
Hi Yuvaraj,
In general this version looks pretty good, but I have some questions inline.
On 10.01.2014 08:00, Yuvaraj Kumar C D wrote:
[snip]
diff --git a/drivers/phy/phy-exynos5250-sata-i2c.c
b/drivers/phy/phy-exynos5250-sata-i2c.c
new file mode 100644
index 000..206e337
--- /dev/null
Cc: Richard Purdie rpur...@rpsys.net
Cc: Jingoo Han jg1@samsung.com
Cc: Laurent Pinchart laurent.pinch...@ideasonboard.com
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell
On 11/01/14 00:43, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:38:25AM +1000, Ben Peddell wrote:
On 11/01/14 00:25, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
On 10/01/14 21:28, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 11:01:06AM +1000,
On Fri, 10 Jan 2014, Hans de Goede wrote:
+static struct usb_ohci_pdata ohci_platform_defaults = {
+ .power_on = ohci_platform_power_on,
+ .power_suspend =ohci_platform_power_off,
+ .power_off =ohci_platform_power_off,
};
I wonder if these
On Fri, Jan 10, 2014 at 7:28 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi,
On 10.01.2014 03:41, Olof Johansson wrote:
On Thu, Jan 9, 2014 at 6:41 PM, Shawn Guo shawn@linaro.org wrote:
On Sat, Jan 04, 2014 at 09:10:58AM +0800, Shawn Guo wrote:
On Fri, Jan 03, 2014 at 11:29:35AM -0800,
Hi,
Denis Carikli wrote:
Cc: Richard Purdie rpur...@rpsys.net
Cc: Jingoo Han jg1@samsung.com
Cc: Laurent Pinchart laurent.pinch...@ideasonboard.com
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren
On Friday 10 January 2014 16:08:36, Gerhard Sittig wrote:
On Fri, Jan 10, 2014 at 15:22 +0100, Lars Poeschel wrote:
--- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
@@ -38,12 +38,37 @@ Required device specific
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Stephen Warren swar...@wwwdotorg.org
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer ker...@pengutronix.de
Cc: Shawn Guo
The following devices/functionalities were added:
* Main and secondary UARTs.
* i2c and the pcf8563 device.
* Ethernet.
* NAND.
* The BP1 button.
* The LED.
* Watchdog
* SD.
Cc: Rob Herring rob.herr...@calxeda.com
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc:
On 11/01/14 00:58, Russell King - ARM Linux wrote:
On Fri, Jan 10, 2014 at 03:25:48PM +0100, Andrew Lunn wrote:
On Sat, Jan 11, 2014 at 12:09:11AM +1000, Ben Peddell wrote:
Bytes transferred = 1954736 (1dd3b0 hex)
Marvell setenv bootargs console=ttyS0,115200 ip=off
Hi Seungwong,
On Fri, 2014-01-10 at 22:19 +0900, Seungwon Jeon wrote:
Hi Dinh,
On Fri, January 10, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare
On Thursday 09 January 2014 08:48 PM, Felipe Balbi wrote:
Hi,
On Thu, Jan 09, 2014 at 08:20:56PM +0530, Balaji T K wrote:
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren
hi,
On Fri, Jan 10, 2014 at 09:25:20PM +0530, Balaji T K wrote:
On Thursday 09 January 2014 08:48 PM, Felipe Balbi wrote:
Hi,
On Thu, Jan 09, 2014 at 08:20:56PM +0530, Balaji T K wrote:
Use devm_regulator API, while at it use
devm_regulator_get_optional for optional vmmc_aux supply
On Fri, Jan 10, 2014 at 01:26:42PM +, Mark Brown wrote:
On Fri, Jan 10, 2014 at 09:03:39PM +0800, Nicolin Chen wrote:
On Fri, Jan 10, 2014 at 12:04:39PM +, Mark Brown wrote:
This is about what I'd expect but then surely the next step is for the
driver to choose a defualt BCLK
pbias register controls internal power supply to sd card i/o pads
in most OMAPs (OMAP2-5, DRA7).
Control bits for selecting voltage level and
enabling/disabling are in the same PBIAS register.
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
v9:
use syscon
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git
handle vcc and vcc_aux independently to reduce indent.
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c | 54 +++--
1 files changed, 25 insertions(+), 29 deletions(-)
diff --git
remove pbias workaround
Signed-off-by: Balaji T K balaj...@ti.com
Acked-by: Tony Lindgren t...@atomide.com
---
drivers/mmc/host/omap_hsmmc.c | 20 +---
1 files changed, 1 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
Hi
On Fri, Jan 10, 2014 at 6:30 PM, Balaji T K balaj...@ti.com wrote:
In DT case, PBAIS registers are programmed via regulator,
use regulator APIs to control PBIAS.
Signed-off-by: Balaji T K balaj...@ti.com
---
drivers/mmc/host/omap_hsmmc.c | 39 +++
Grant,
On Sun, Dec 01, 2013 at 11:56:28PM +, Jason Cooper wrote:
Unlike other build products in the Linux kernel, there is no 'make
*install' mechanism to put devicetree blobs in a standard place.
This patch is an attempt to fix this problem. Akin to 'make install',
this creates a new
Grant,
On Tue, Dec 17, 2013 at 04:59:40PM +, Jason Cooper wrote:
Signed-off-by: Jason Cooper ja...@lakedaemon.net
---
Changes from RFC:
- incorporated Grant's language
- split patches/ABI into two documents
Documentation/devicetree/bindings/ABI.txt | 39
On Fri, Jan 10, 2014 at 7:30 AM, Rob Herring robherri...@gmail.com wrote:
On Fri, Jan 10, 2014 at 7:28 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi,
On 10.01.2014 03:41, Olof Johansson wrote:
On Thu, Jan 9, 2014 at 6:41 PM, Shawn Guo shawn@linaro.org wrote:
On Sat, Jan 04, 2014 at
* Tero Kristo t-kri...@ti.com [140110 08:32]:
On 01/10/2014 06:13 PM, Felipe Balbi wrote:
On Fri, Jan 10, 2014 at 11:52:49AM +0200, Tero Kristo wrote:
On 01/10/2014 01:15 AM, Felipe Balbi wrote:
On Thu, Jan 09, 2014 at 03:22:03PM -0600, Nishanth Menon wrote:
conflicts with be changes on
* Mike Turquette mturque...@linaro.org [140109 14:25]:
Quoting Tero Kristo (2014-01-09 06:00:11)
Hi,
So, bad luck number release for this, as v12 wasn't sufficient still.
Changes compared to previous version:
- Dropped any changes to generic clock drivers, as it seems impossible
On 01/10, Will Deacon wrote:
On Thu, Jan 09, 2014 at 07:57:12PM +, Stephen Boyd wrote:
(Adding DT reviewers)
On 01/09/14 03:04, Will Deacon wrote:
On Wed, Jan 08, 2014 at 10:59:40PM +, Stephen Boyd wrote:
+static int krait_pmu_init(struct arm_pmu *cpu_pmu)
+{
+
On Friday 10 January 2014, Dinh Nguyen wrote:
diff --git a/arch/arm/boot/dts/socfpga.dtsi
b/arch/arm/boot/dts/socfpga.dtsi
index f936476..e776512 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -413,6 +413,7 @@
Add device tree binding support for the QCOM BAM DMA driver.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 52 ++
1 file changed, 52 insertions(+)
create mode 100644
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the
This patch set introduces the dmaengine driver for the Qualcomm Bus Access
Manager (BAM) DMA controller present on MSM 8x74 devices. A number of the
on-chip devices have their own BAM DMA controller and use it to move data
between system memory and peripherals or between two peripherals.
The
Loc Ho wrote:
This patch adds support for the APM X-Gene SoC SATA host controller driver.
It requires the corresponding APM X-Gene SoC PHY driver.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/ata/Kconfig
Hi!
On Fri, Jan 10, 2014 at 10:49:59AM -0600, Vince Bridgers wrote:
This change adds a parameter for the Synopsys 10/100/1000
stmmac Ethernet driver to configure the maximum MTU supported
by the EMAC instance. Synopsys allows the FIFO sizes to
be configured when the cores are built for a
Loc Ho wrote:
This patch adds support for the APM X-Gene SoC SATA host controller driver.
It requires the corresponding APM X-Gene SoC PHY driver.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/ata/Kconfig
On Fri, 2014-01-10 at 10:29 +0800, Tang Yuantian wrote:
+- reg: Offset and length of the clock register set
offset into what? The containing node is not within the scope of this
binding.
I know that plenty of other bindings are worded this way, and I wouldn't
hold up acceptance if this were
Hello.
On 01/10/2014 12:47 PM, Hans de Goede wrote:
Hi,
I would like to know why you dropped me from the To: list when replying. I
have hardly noticed your reply.
Add support for ohci-platform instantiation from devicetree, including
optionally getting clks and a phy from devicetree,
Gregory,
On Wed, Jan 08, 2014 at 04:06:29PM +0100, Gregory CLEMENT wrote:
The first variants of Armada XP SoCs (A0 stepping) have issues related
to the i2c controller which prevent to use the offload mechanism and
ead to a kernel hang during boot.
I'll fixup s/ead/lead/ here.
The commit
On Sun, Jan 5, 2014 at 12:48 PM, Ravi Patel rapa...@apm.com wrote:
On Sun, Jan 5, 2014 at 10:11 AM, Arnd Bergmann a...@arndb.de wrote:
On Sunday 05 January 2014, Ravi Patel wrote:
On Sat, Dec 21, 2013 at 11:03 PM, Arnd Bergmann a...@arndb.de wrote:
Please describe here what the purpose of
Hi All,
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
Changes since v3:
-Address all of Alan Stern's review comments
-Properly use put_clk in probe error path
-Don't do hcd_put until after power_off as
Hello.
On 01/11/2014 01:46 AM, Hans de Goede wrote:
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
I see you've decided to completely ignore my opinion. NAK, FWIW.
Changes since v3:
-Address all of Alan
Hans de Goede hdego...@redhat.com writes:
On 01/11/2014 12:50 AM, Sergei Shtylyov wrote:
Hello.
On 01/11/2014 01:46 AM, Hans de Goede wrote:
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
I see you've
On 01/11/2014 01:52 AM, Hans de Goede wrote:
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
I see you've decided to completely ignore my opinion. NAK, FWIW.
I'm sorry but the whole prefix thing has
Hello.
On 01/11/2014 02:08 AM, Bjørn Mork wrote:
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
I see you've decided to completely ignore my opinion. NAK, FWIW.
I'm sorry but the whole prefix thing
Hi,
On 01/11/2014 01:10 AM, Sergei Shtylyov wrote:
On 01/11/2014 01:52 AM, Hans de Goede wrote:
Here is v4 of my ohci and ehci-platform clks, phy and dt support patch-set,
this version should be 100% ready for merging upstream.
I see you've decided to completely ignore my opinion. NAK,
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