On Sat, Jan 18, 2014 at 3:56 AM, Matt Porter mpor...@linaro.org wrote:
I wonder if Linus would accept a rename at this point (too late for 3.14
presumably, but for 3.15) of s/capri/bcm281xx throughout, bcm11351 for
the compatible string, as we have for the machine compatible, and also
On 01/09/2014 05:00 PM, Tejun Heo wrote:
On Thu, Jan 09, 2014 at 05:07:29PM +0530, Roger Quadros wrote:
I know it is pointless functionally, but it is just my preference
aesthetically.
Is it much of an issue if left as is?
Yes.
OK. I'll send a v5.
cheers,
-roger
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On Sun, Jan 19, 2014 at 12:48:50AM +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/ata/ahci_platform.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/drivers/ata/ahci_platform.c
Hi,
On 01/20/2014 09:24 AM, Sascha Hauer wrote:
On Sun, Jan 19, 2014 at 12:48:50AM +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/ata/ahci_platform.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
On Fri, Jan 17, 2014 at 02:04:44PM +0800, Jingchang Lu wrote:
Add Freescale enhanced direct memory(eDMA) controller support.
This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jingchang Lu b35...@freescale.com
Acked-by: Arnd
On 20 January 2014 04:56, Olof Johansson o...@lixom.net wrote:
This patch enables support for power-on sequencing of SDIO peripherals
through DT.
In general, it's quite common that wifi modules and other similar
peripherals have several signals in addition to the SDIO interface that
needs
-Original Message-
From: Vinod Koul [mailto:vinod.k...@intel.com]
Sent: Monday, January 20, 2014 3:40 PM
To: Lu Jingchang-B35083
Cc: dan.j.willi...@intel.com; a...@arndb.de; shawn@linaro.org;
pawel.m...@arm.com; mark.rutl...@arm.com; swar...@wwwdotorg.org; linux-
On 01/10/2014 04:26 PM, Lee Jones wrote:
On Fri, 10 Jan 2014, Arnd Bergmann wrote:
On Friday 10 January 2014, Lee Jones wrote:
- need_logic_fck = false;
+ /* Set all clocks as invalid to begin with */
+ omap-ehci_logic_fck = omap-init_60m_fclk = ERR_PTR(-EINVAL);
+
On 01/10/2014 12:11 PM, Lee Jones wrote:
On Thu, 09 Jan 2014, Roger Quadros wrote:
The omap-usb-host driver expects certained named clocks.
Add this information to the DT binding document.
Use clock names as per function for reference clocks.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel
Hi,
On 01/20/2014 10:09 AM, Sascha Hauer wrote:
On Mon, Jan 20, 2014 at 09:35:06AM +0100, Hans de Goede wrote:
Hi,
On 01/20/2014 09:24 AM, Sascha Hauer wrote:
+
+static const struct ahci_platform_data *ahci_get_pdata(struct device *dev)
+{
+ struct ahci_platform_data *pdata;
+
On Sun, Jan 19, 2014 at 08:16:42PM +, Laurent Pinchart wrote:
Hi Valentine,
Thank you for the patch.
On Friday 17 January 2014 02:07:42 Valentine Barshak wrote:
Now that the clocks are available in the R-Car Gen2 DT,
add clocks property description to the sata_rcar bindings.
The
On Sun, 19 Jan 2014 20:06:09 -0800
Olof Johansson o...@lixom.net wrote:
Hi,
On Sun, Jan 19, 2014 at 10:58 AM, Jean-Francois Moine moin...@free.fr wrote:
Signed-off-by: Jean-Francois Moine moin...@free.fr
---
.../devicetree/bindings/drm/i2c/tda998x.txt| 24
Good day. I am Mark Reyes Guus, I work with Abn Amro Bank as an auditor. I have
a proposition to discuss with you. Should you be interested, please e-mail back
to me.
Private Email: markreyesg...@abnmrob.co.uk OR markguus.reye...@yahoo.nl
Yours Sincerely,
Mark Reyes Guus.
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On Sun, Jan 19, 2014 at 07:34:22PM -0800, Olof Johansson wrote:
I'm guessing this is going to mess up Shawn's cleanup patches, but
time has ran out for 3.14 for those so they will need to be respun
anyway, most likely.
We can apply them to arm-soc's dt branch. I think it's better if we
On Mon, Jan 20, 2014 at 10:17:24AM +0100, Hans de Goede wrote:
Hi,
I'm currently working on a slightly different implementation of a more
generic ahci_platform.c where ahci_platform.c exports some standard platform
related functionality as library functions.
Drivers which need to override
Add Freescale enhanced direct memory(eDMA) controller support.
This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jingchang Lu b35...@freescale.com
Acked-by: Arnd Bergmann a...@arndb.de
---
changes in v11:
Add dma device_slave_caps
On Mon, Jan 20, 2014 at 09:06:43AM +, Jingchang Lu wrote:
-Original Message-
From: Vinod Koul [mailto:vinod.k...@intel.com]
Sent: Monday, January 20, 2014 3:40 PM
To: Lu Jingchang-B35083
Cc: dan.j.willi...@intel.com; a...@arndb.de; shawn@linaro.org;
On 18/01/14 19:25, Sergei Shtylyov wrote:
Hello.
On 18-01-2014 19:03, Ben Dooks wrote:
Add initial documentation for the pci-rcar-gen2 driver device tree
bindings.
This is not yet complete and needs work on the sub-nodes for the PCI bus.
Why do you think there's a need to document PCI
On 18/01/14 19:19, Sergei Shtylyov wrote:
Hello.
On 18-01-2014 19:03, Ben Dooks wrote:
Add support for the phy-rcar-gen2-usb driver to be probed from device
tree.
Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
Reviewed-by: Ian Molton ian.mol...@codethink.co.uk
---
Cc:
-Original Message-
From: Vinod Koul [mailto:vinod.k...@intel.com]
Sent: Monday, January 20, 2014 5:36 PM
To: Lu Jingchang-B35083
Cc: dan.j.willi...@intel.com; a...@arndb.de; shawn@linaro.org;
pawel.m...@arm.com; mark.rutl...@arm.com; swar...@wwwdotorg.org; linux-
Hello.
On 20-01-2014 14:49, Ben Dooks wrote:
Add support for the phy-rcar-gen2-usb driver to be probed from device
tree.
Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
Reviewed-by: Ian Molton ian.mol...@codethink.co.uk
---
Cc: linux-...@vger.kernel.org (open list:USB PHY LAYER)
Cc:
On Mon, Jan 20, 2014 at 11:05:03AM +, Jingchang Lu wrote:
+ struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
+ struct dma_slave_config *cfg = (void *)arg;
+ unsigned long flags;
+ LIST_HEAD(head);
+
+ switch (cmd) {
+ case
Some gpio-leds need retain the state even in suspend, such as charger led.
But this property missed in devicetree, add it.
Signed-off-by: Robin Gong b38...@freescale.com
---
drivers/leds/leds-gpio.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git
Update the binding doc for new property: retain-state-suspended
Signed-off-by: Robin Gong b38...@freescale.com
---
.../devicetree/bindings/leds/leds-gpio.txt | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git
On Monday 20 January 2014, Srikanth Thokala wrote:
On Fri, Jan 17, 2014 at 9:43 PM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 16 January 2014, Srikanth Thokala wrote:
I also assume that some of the properties should just go away:
* xlnx,device-id should be the argument in the handle
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
v6:
* no changes since v5, respin for updated net-next
v5:
* Simplify use notes for max-frame-size in stmmac.txt, in the
devicetree patch. No change to the stmmac driver patch
from v4.
v4:
* Address inconsistent comment with use, add comments about inconsistency
of max-frame-size
This change adds a parameter for the Synopsys 10/100/1000
stmmac Ethernet driver to configure the maximum frame
size supported by the EMAC driver. Synopsys allows the FIFO
sizes to be configured when the cores are built for a particular
device, but do not provide a way for the driver to read
These changes correct the following issues with jumbo frames on the
stmmac driver:
1) The Synopsys EMAC can be configured to support different FIFO
sizes at core configuration time. There's no way to query the
controller and know the FIFO size, so the driver needs to get this
information from the
On Mon, Jan 20, 2014 at 07:42:33PM +0800, Anson Huang wrote:
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |6 +++---
1 file
Hi, Sascha
Thanks for the reminder, will improve it in V2.
Best Regards.
Anson huang 黄勇才
Freescale Semiconductor Shanghai
上海浦东新区亮景路192号A座2楼
201203
Tel:021-28937058
-Original Message-
From: Sascha Hauer [mailto:s.ha...@pengutronix.de]
Sent: Monday, January 20, 2014 7:54 PM
To:
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
Add DT support for this codec. The bindings differ a bit from the aic3x
codec bindings, so I created a new binding documentation.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar
Add support for a master clock passed through DT. The master clock of
the codec is only active when the codec is in use.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian Campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala
Hey,
On Sun, Jan 19, 2014 at 08:52:21PM +0100, Hans de Goede wrote:
And having ahci_resume in ahci_platform.c still doing the clk and power
enabling
before calling into ahci_platform_resume, and drivers overriding the resume
method
need to do their own clk + regulator + whatever setup
On Sun, Jan 19, 2014 at 08:56:09PM +0100, Hans de Goede wrote:
Ok, asking the obvious here I guess, but you would accept a patch moving
drivers/ata/ahci.h
to include/linux as part of this patch-set ?
Wouldn't creating a minimal file which only contains the necessary
bits make more sense?
On 20/01/14 12:18, Sergei Shtylyov wrote:
Hello.
On 18-01-2014 19:03, Ben Dooks wrote:
Add support for the phy-rcar-gen2-usb driver to be probed from device
tree.
Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
Reviewed-by: Ian Molton ian.mol...@codethink.co.uk
---
Cc:
On Thu, Dec 26, 2013 at 06:25:41PM +0100, Andrew Lunn wrote:
Some Marvell SoCs have a SATA PHY which can be powered off, in order
to save power. Make use of the generic phy framework to control these
phys.
Signed-off-by: Andrew Lunn and...@lunn.ch
Applied to libata/for-3.14. It's late but
Am Montag, den 20.01.2014, 13:05 +0100 schrieb Markus Pargmann:
Add DT support for this codec. The bindings differ a bit from the aic3x
codec bindings, so I created a new binding documentation.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland
On Mon, Jan 20, 2014 at 01:54:57PM +0100, Philipp Zabel wrote:
Am Montag, den 20.01.2014, 13:05 +0100 schrieb Markus Pargmann:
Add DT support for this codec. The bindings differ a bit from the aic3x
codec bindings, so I created a new binding documentation.
Cc: Rob Herring
Jensen jonas.jen...@gmail.com
---
Notes:
Applies to next-20140120
.../devicetree/bindings/net/moxa,moxart-mac.txt| 47 ++-
drivers/net/ethernet/moxa/moxart_ether.c | 92 +-
drivers/net/ethernet/moxa/moxart_ether.h | 2 +
3 files changed
Hi Arnd,
Sorry for the duplication. Ccing others.
On Mon, Jan 20, 2014 at 5:09 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 20 January 2014, Srikanth Thokala wrote:
On Fri, Jan 17, 2014 at 9:43 PM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 16 January 2014, Srikanth Thokala wrote:
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Thereby, removing old phy-samsung-usb3 driver and related code
used untill now which was based on usb/phy
Hi Kishon,
[...]
Right.
While 3.0 block(PIPE3) can be used for Super Speed, 2.0
block(UTMI+)
can be used for High speed.
It should then come under *single IP muliple PHY* category similar
to what
Sylwester has done.
[...]
The idea is to model the driver as close to the hardware
On Fri, Jan 17, 2014 at 7:05 PM, Sergei Shtylyov
sergei.shtyl...@cogentembedded.com wrote:
This patch is an attempt to gather the Ethernet related bindings in one file,
like it's done in the MMC and some other subsystems. It should save the
trouble
of documenting several properties over and
On Fri, Jan 17, 2014 at 5:03 PM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
The Qualcomm Universal Peripherial (QUP) wraps I2C mini-core and
provide input and output FIFO's for it. I2C controller can operate
as master with supported bus
Hi Benoit Tony,
This patchset brings up USB Host ports and Ethernet port on
the OMAP5 uEVM board.
It depends on the TI Clock DT conversion patches [1] and is based
on 3.13
[1] - http://article.gmane.org/gmane.linux.ports.arm.kernel/293147
Tested on:
- OMAP5 uEVM
- Pandaboard ES Rev. B1
-
The omap-usb-tll driver needs one clock for each TLL channel.
Add this information to the DT binding document.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/mfd/omap-usb-tll.txt | 10
The omap-usb-host driver expects certained named clocks.
Add this information to the DT binding document.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
---
.../devicetree/bindings/mfd/omap-usb-host.txt | 23
The HS USB 2 PHY gets its clock from AUXCLK1. Provide this
information.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
The omap-usb-host driver expects a certain name for internal
and external reference clocks. Provide these clocks.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/omap5.dtsi
The necessary clock phandle for the EHCI clock is now provided
via device tree so we no longer need this legacy method.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/mach-omap2/pdata-quirks.c | 16
1 file changed, 16 deletions(-)
diff --git
The omap-usb-host driver expects a certain name for internal
and external reference clocks. Provide these clocks.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap4.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/omap4.dtsi
The USB PHY gets its clock from AUXCLK3. Provide this
information.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap4-panda-common.dtsi | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi
Not all revisions have all the clocks so get the necessary clocks
based on hardware revision.
This should avoid un-necessary clk_get failure messages that were
observed earlier.
Be more strict and always fail on clk_get() error.
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz
Use devm_clk_get() instead of clk_get().
CC: Lee Jones lee.jo...@linaro.org
CC: Samuel Ortiz sa...@linux.intel.com
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Lee Jones lee.jo...@linaro.org
---
drivers/mfd/omap-usb-host.c | 81 +
1 file
Am Freitag, 20. Dezember 2013, 16:26:47 schrieb Heiko Stübner:
It seems I forgot to add the vendor prefix for rockchip to the vendor-prefix
list. Therefore add it now.
Signed-off-by: Heiko Stuebner he...@sntech.de
not sure, where this should go through
arm-soc? or is there a special dt-tree
From: Vinod Koul vinod.k...@intel.com
Sent: Monday, January 20, 2014 6:20 PM
To: Lu Jingchang-B35083
Cc: dan.j.willi...@intel.com; a...@arndb.de; shawn@linaro.org;
pawel.m...@arm.com; mark.rutl...@arm.com; swar...@wwwdotorg.org;
Hi Bartlomiej,
Thanks for the review.
Yes you are right. I didn't add the users for this driver.
Once the driver gets merged, I will send more patches with the users.
Already this driver merge is pending on DT maintainers ack and I
don't want to complex it more by adding DT patches :)
Hi,
Some platforms have a PHY hooked up to the SATA controller.
The PHY needs to be initialized and powered up for SATA to work.
We do that using the Generic PHY framework in PATCH 3.
In order to support SATA on the OMAP platforms we need to runtime
resume the device before use. PATCH 4 takes
From: Balaji T K balaj...@ti.com
Some platforms have a PHY hooked up to the
SATA controller. The PHY needs to be initialized
and powered up for SATA to work. We do that
using the PHY framework.
[Roger Q] Cleaned up.
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros
On OMAP platforms the device needs to be runtime resumed before
it can be accessed. The OMAP HWMOD framework takes care of
enabling the module and its resources based on the
device's runtime PM state.
In this patch we runtime resume during .probe() and runtime suspend
during .remove() (i.e.
Add compatible string snps,dwc-ahci, which should be used
for Synopsis Designware SATA cores. e.g. on TI OMAP5 and DRA7 platforms.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
drivers/ata/ahci_platform.c | 1 +
1 file changed, 1
The ahci_platform driver supports snps,exynos5440-ahci, ibm,476gtr-ahci
and snps,dwc-ahci. Add this to the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
---
On Mon, Jan 20, 2014 at 8:41 AM, Roger Quadros rog...@ti.com wrote:
The ahci_platform driver supports snps,exynos5440-ahci, ibm,476gtr-ahci
and snps,dwc-ahci. Add this to the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
Reviewed-by: Bartlomiej Zolnierkiewicz
On Mon, Jan 20, 2014 at 8:23 AM, Heiko Stübner he...@sntech.de wrote:
Am Freitag, 20. Dezember 2013, 16:26:47 schrieb Heiko Stübner:
It seems I forgot to add the vendor prefix for rockchip to the vendor-prefix
list. Therefore add it now.
Signed-off-by: Heiko Stuebner he...@sntech.de
not
On Mon, Jan 20, 2014 at 5:13 AM, Jonas Jensen jonas.jen...@gmail.com wrote:
The kernel now has a MDIO bus driver and a phy_driver (RTL8201CP),
connect to this PHY using OF.
Signed-off-by: Jonas Jensen jonas.jen...@gmail.com
---
Notes:
Applies to next-20140120
.../devicetree/bindings
Hi Mark,
On Monday 20 January 2014 09:31:19 Mark Rutland wrote:
On Sun, Jan 19, 2014 at 08:16:42PM +, Laurent Pinchart wrote:
On Friday 17 January 2014 02:07:42 Valentine Barshak wrote:
Now that the clocks are available in the R-Car Gen2 DT,
add clocks property description to the
Some SoCs need parts of their sram for special purposes. So while being part
of the peripheral, it should not be part of the genpool controlling the sram.
Therefore add an option mmio-sram-reserved to keep arbitrary portions of the
sram from general usage.
Suggested-by: Rob Herring
The need to know the number of array elements in a property is
a common pattern. To prevent duplication of open-coded implementations
add a helper static function that also centralises strict sanity
checking and DTB format details, as well as a set of wrapper functions
for u8, u16, u32 and u64.
This adds the device-node and config select to enable the
scu in all Rockchip Cortex-A9 SoCs.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
arch/arm/boot/dts/rk3xxx.dtsi |5 +
arch/arm/mach-rockchip/Kconfig |1 +
2 files
The pmu is needed to bring up the cores during smp operations and later
also other system parts. Therefore add a node and documentation for it.
Signed-off-by: Heiko Stuebner he...@sntech.de
Tested-by: Ulrich Prinz ulrich.pr...@googlemail.com
---
This adds the necessary smp-operations and startup code to use
additional cores on Rockchip SoCs.
We currently hog the power management unit in the smp code, as it is
necessary to control the power to the cpu core and nothing else is
currently using it, so a generic implementation can be done
Some ahci_platform_data-init methods need access to the ahci_host_priv data.
When calling ahci_platform_data-init the ata_host has not been allocated yet,
so access to ahci_host_priv through the dev argument is not possible.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
The allwinner-sun4i AHCI controller needs 2 clocks to be enabled and the
imx AHCI controller needs 3 clocks to be enabled.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 +
drivers/ata/ahci_platform.c| 97
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 +
drivers/ata/ahci_platform.c| 35 --
include/linux/ahci.h | 2 ++
3 files changed, 36 insertions(+), 2
With the ahci-platform.c changes later in this patch-set, some
arch/arm/mach-foo/*.c sata drivers need access to ahci_host_priv, so move
its declaration outside of drivers/ata.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/ata/ahci.h | 20 +---
From: Olliver Schinagl oli...@schinagl.nl
This patch adds support for the ahci sata controler found on Allwinner A10
and A20 SoCs to the ahci_platform driver.
Orignally written by Olliver Schinagl using the approach of having a platform
device which probe method creates a new child platform
Split suspend / resume code into host suspend / resume functionality and
resource enable / disabling phases, and export the new suspend_ / resume_host
functions.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/ata/ahci_platform.c | 55 +++
This avoids the ugliness of creating a nested platform device from probe.
Note untested, I've ordered a wandboard to be able to test these changes.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
.../devicetree/bindings/ata/ahci-platform.txt | 8 +-
drivers/ata/ahci_imx.c
Hi,
On 01/20/2014 03:41 PM, Roger Quadros wrote:
Hi,
Some platforms have a PHY hooked up to the SATA controller.
The PHY needs to be initialized and powered up for SATA to work.
We do that using the Generic PHY framework in PATCH 3.
In order to support SATA on the OMAP platforms we need to
On Sun, Jan 19, 2014 at 07:56:53PM -0800, Olof Johansson wrote:
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt
b/Documentation/devicetree/bindings/mmc/mmc.txt
index 458b57f..962e0ee 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++
On Mon, Jan 20, 2014 at 2:48 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
So far so good. Now, what about this external oscillator which has its
own separate power control. My immediate thought is that this can be
specified via card_ext_clock - I would simply need to declare a
On Mon, Jan 20, 2014 at 06:21:35AM +, Gupta, Pekon wrote:
[..]
Pekon, do you think this binding proposal is good enough to describe OMAP
NAND
ECC mode?
I'm not implying we should deprecate the recently added ti-nand-ecc-opt,
but just want to know it's eventually possible.
Yes,
This patch allows to set independantly SCL and SDA falling times.
The tLOW period is computed by taking into account the SCL falling time.
The tHIGH period is computed by taking into account the SDA falling time.
For instance in case the margin on tLOW is considered too small, it can
be increased
Some legacy devices support ony I2C standard mode at 100kHz.
This patch allows to select the standard mode through the DTS
with the use of the existing clock-frequency parameter.
When clock-frequency parameter is not set, the fast mode is selected.
Only when the parameter is set at 10, the
On Mon, Jan 20, 2014 at 03:03:50PM -0200, Fabio Estevam wrote:
On Mon, Jan 20, 2014 at 2:48 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
So far so good. Now, what about this external oscillator which has its
own separate power control. My immediate thought is that this can
Hi Lorenzo,
On 16.01.2014 17:34, Lorenzo Pieralisi wrote:
Hi Tomasz,
thank you for posting this series. I would like to use the DT bindings
for power domains in the bindings for C-states on ARM:
http://comments.gmane.org/gmane.linux.power-management.general/41012
and in particular link a
On 01/17/2014 07:20 PM, Nishanth Menon wrote:
[...]
I am running a defconfig set check on next-20140117 and will do one
with next-20140118 once that is ready for comparison results
baseline next-20140120
modified as follows:
multi_v7_defconfig - added CONFIG_SOC_DRA7XX
omap2plus_defconfig
On ARM systems the cache topology cannot be probed at runtime, in
particular, it is impossible to probe which CPUs share a given cache
level. Power management software requires this knowledge to implement
optimized power down sequences, hence this patch adds a document that
defines the DT cache
This is v2 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-December/215544.html
This patchset depends on the following bindings to be approved and augmented
to cater for hierarchical power domains in DT:
ARM based platforms implement a variety of power management schemes that
allow processors to enter at run-time low-power states, aka C-states
in ACPI jargon. The parameters defining these C-states vary on a per-platform
basis forcing the OS to hardcode the state parameters in platform
specific
Hi,
I just found some time to update my SSI driver adding DT clock
support. It works, but I wonder if the alias of the ssi clocks
can be changed to something like the following:
/* omap3430es1-clocks.dtsi */
ssi_ick: ssi_ick_3430es1 {};
ssi_ssr_fck: ssi_ssr_fck_3430es1 {};
ssi_sst_fck:
On Monday 20 January 2014, Srikanth Thokala wrote:
* data width should be a property of the slave driver that is configured
through dma_slave_config(), unless you can have dma engines that only
support certain a width.
Yes, this VDMA engine soft IP support only certain widths,
On Mon, Jan 20, 2014 at 3:16 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Not as far as I can see. fixed-clock appears to have two properies:
clock-frequency
clock-output-names
and nothing else. See of_fixed_clk_setup in drivers/clk/clk-fixed-rate.c.
You'll
On Monday 20 January 2014, Olof Johansson wrote:
+Card power and reset control:
+The following properties can be specified for cases where the MMC
+peripheral needs additional reset, regulator and clock lines. It is for
+example common for WiFi/BT adapters to have these separate from the
On Mon, Jan 20, 2014 at 10:58 AM, Arnd Bergmann a...@arndb.de wrote:
On Monday 20 January 2014, Olof Johansson wrote:
+Card power and reset control:
+The following properties can be specified for cases where the MMC
+peripheral needs additional reset, regulator and clock lines. It is for
On Monday 20 January 2014 11:04:26 Olof Johansson wrote:
I'd expect most usage of this to be through gpios, since we're talking
about external independent modules here. I would prefer not to bring
in the reset controller stuff here -- it just adds another layer of
abstraction that seems
On Mon, Jan 20, 2014 at 1:56 AM, Olof Johansson o...@lixom.net wrote:
+Card power and reset control:
+The following properties can be specified for cases where the MMC
+peripheral needs additional reset, regulator and clock lines. It is for
+example common for WiFi/BT adapters to have these
On Mon, Jan 20, 2014 at 11:14 AM, Fabio Estevam feste...@gmail.com wrote:
On Mon, Jan 20, 2014 at 1:56 AM, Olof Johansson o...@lixom.net wrote:
+Card power and reset control:
+The following properties can be specified for cases where the MMC
+peripheral needs additional reset, regulator and
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