Please apply this. It's way overdue. It fixes customer kernel crashes
we've seen in the field.
I'd also advocate for seeing this be applied to stable kernels.
thanks,
grant
On Thu, Mar 13, 2014 at 10:02 PM, Cho KyongHo wrote:
> This commit adds cache flush for removed small and large page entr
Thanks for the review and comments. I will incorporate the comments
from you and Jingoo Han in next version.
-Tanmay
On Fri, Mar 14, 2014 at 5:18 AM, Arnd Bergmann wrote:
> On Thursday 06 March 2014, Tanmay Inamdar wrote:
>
>> +static inline void xgene_pcie_cfg_out16(void __iomem *addr, u16 val)
On Fri, Mar 14, 2014 at 5:07 AM, Arnd Bergmann wrote:
> On Thursday 06 March 2014, Tanmay Inamdar wrote:
>> + pcie0: pcie@1f2b {
>> + status = "disabled";
>> + device_type = "pci";
>> + compatible = "apm,xgene-storm-pcie",
Hi Rajendra,
On 03/14/2014 04:20 AM, Nayak, Rajendra wrote:
The only difference from the dra75x devices is the missing .smp entry.
Signed-off-by: Rajendra Nayak
---
arch/arm/mach-omap2/board-generic.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/mach-om
Hi Ohad,
On 03/14/2014 03:10 PM, Ohad Ben-Cohen wrote:
Hi Suman, Mark,
On Mon, Feb 24, 2014 at 8:14 PM, Suman Anna wrote:
Mark, Ohad,
...
Gentle reminder, can you provide your acks/comments?
Sorry for the late jump in.
I have a few comments:
Thanks for the comments. It probably covers
On Fri, Mar 14, 2014 at 04:50:23PM +, Julien Grall wrote:
> On 02/24/2014 08:49 PM, Stefano Stabellini wrote:
> > On Mon, 24 Feb 2014, gre...@linuxfoundation.org wrote:
> > Julien is proposing to store the list of "safe" devices on an hash table
> > in the Xen specific code (in arch/arm/xen/en
This patch adds APM X-Gene SoC AHCI SATA host controller DTS entries.
Signed-off-by: Loc Ho
Signed-off-by: Tuan Phan
Signed-off-by: Suman Tripathi
---
arch/arm64/boot/dts/apm-storm.dtsi | 80
1 files changed, 80 insertions(+), 0 deletions(-)
diff --git a
This patch adds support for the APM X-Gene SoC AHCI SATA host controller
driver. It requires the corresponding APM X-Gene SoC PHY driver. This
initial version only supports Gen3 speed.
Signed-off-by: Loc Ho
Signed-off-by: Tuan Phan
Signed-off-by: Suman Tripathi
---
drivers/ata/Kconfig |
This patch adds the DTS entries for the APM X-Gene SoC 15Gbps Multi-purpose
PHY driver. The PHY for SATA controller 2 and 3 are enabled by default.
Signed-off-by: Loc Ho
Signed-off-by: Tuan Phan
Signed-off-by: Suman Tripathi
---
arch/arm64/boot/dts/apm-storm.dtsi | 72 +++
This patch adds support for the APM X-Gene SoC AHCI SATA host controller. In
order for the host controller to work, the corresponding PHY driver
musts also be available. Currently, only Gen3 disk is supported with this
initial version.
v18:
* Remove clock-name properity from dts nodes
* Update b
This patch adds documentation for the APM X-Gene SoC SATA host controller DTS
binding.
Signed-off-by: Loc Ho
Signed-off-by: Tuan Phan
Signed-off-by: Suman Tripathi
---
.../devicetree/bindings/ata/apm-xgene.txt | 76
1 files changed, 76 insertions(+), 0 deletions
Tomasz Figa writes:
> This patch introduces generic code to perform power domain look-up using
> device tree and automatically bind devices to their power domains.
> Generic device tree binding is introduced to specify power domains of
> devices in their device tree nodes.
>
> Backwards compatibi
On Mar 14, Guenter Roeck wrote:
> On 03/12/2014 02:11 PM, Ezequiel Garcia wrote:
> >Third round of the patchset adding support for watchdog on Armada 375 and
> >Armada 38x SoCs.
> >
> >The new Armada 375/385 SoCs have two registers for the watchdog RSTOUT:
> >
> > 1. It has a dedicated register (s
On 03/12/2014 02:11 PM, Ezequiel Garcia wrote:
Third round of the patchset adding support for watchdog on Armada 375 and
Armada 38x SoCs.
The new Armada 375/385 SoCs have two registers for the watchdog RSTOUT:
1. It has a dedicated register (similar to the one in A370/XP)
2. Also has a bit
On Fri, Mar 14, 2014 at 12:11 PM, Grant Likely wrote:
> Make of_find_node_by_path() handle aliases as prefixes. To make this
> work the name search is refactored to search by path component instead
> of by full string. This should be a more efficient search, and it makes
> it possible to start a s
Hi
>> >> > gets called. Can you clarify what this register access does?
>> >> > If it's just setting a index into a mux output, would it make
>> >> > sense to have an optional DT property containing an integer with
>> >> > the mux setting you want to set? That way you wouldn't even
>> >> > have to
On Thu, Feb 27, 2014 at 07:53:34AM +0100, Zhang Rui wrote:
> On Wed, 2014-02-05 at 17:43 -0800, Courtney Cavin wrote:
> > This driver is a generic method for using IIO ADC channels as thermal
> > sensors.
> >
> > Signed-off-by: Courtney Cavin
>
> Eduardo,
>
> what do you think of this patch?
A
On Friday 14 March 2014, Loc Ho wrote:
> Hi,
>
> >> > gets called. Can you clarify what this register access does?
> >> > If it's just setting a index into a mux output, would it make
> >> > sense to have an optional DT property containing an integer with
> >> > the mux setting you want to set? Th
On Fri, Mar 14, 2014 at 2:25 PM, Dave Gerlach wrote:
> Driver to read from a register and depending on either set bits or
> a specific known selectively enable or disable OPPs based on DT node.
>
> Can support opp-modifier-reg-bit where single bits within the register
> determine the availability
While reviewing an i2c driver for efm32 that needs a similar property
Wolfram Sang pointed out that "location" is a too generic name for something
that is efm32 specific. So add an appropriate namespace and fall back to the
generic name in case of failure.
Signed-off-by: Uwe Kleine-König
---
Chan
On Fri, Mar 14, 2014 at 09:34:22PM +0100, Uwe Kleine-König wrote:
> While reviewing an i2c driver for efm32 that needs a similar property
> Wolfram Sang pointed out that "location" is a too generic name for
> something that is efm32 specific. So add an appropriate namespace and
> fall back to the g
While reviewing an i2c driver for efm32 that needs a similar property
Wolfram Sang pointed out that "location" is a too generic name for
something that is efm32 specific. So add an appropriate namespace and
fall back to the generic name in case of failure.
Signed-off-by: Uwe Kleine-König
---
Chan
Hi,
>> > gets called. Can you clarify what this register access does?
>> > If it's just setting a index into a mux output, would it make
>> > sense to have an optional DT property containing an integer with
>> > the mux setting you want to set? That way you wouldn't even
>> > have to have two comp
Hi Suman, Mark,
On Mon, Feb 24, 2014 at 8:14 PM, Suman Anna wrote:
> Mark, Ohad,
...
> Gentle reminder, can you provide your acks/comments?
Sorry for the late jump in.
I have a few comments:
- Hardware spinlocks must have global and system-wide id numbers;
these numbers cannot be maintained in
On Fri, Mar 14, 2014 at 7:33 PM, Alexander Holler wrote:
> Am 14.03.2014 14:54, schrieb Linus Walleij:
>
>> On Fri, Mar 14, 2014 at 1:38 PM, Alexander Holler
>> wrote:
>>
In that case it is hardly a fix that we need to rush out to the entire
world.
>>>
>>>
>>> And I thought the reason f
On Fri, Mar 14, 2014 at 05:34:29PM +0200, Roger Quadros wrote:
> On 03/14/2014 04:54 PM, Kishon Vijay Abraham I wrote:
> >
> >
> > On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
> >> On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
> >>> Hi Roger,
> >>>
> >>> On Friday 07 March 2014
Add a hook inside opp_init_cpufreq_table to allow all cpufreq drivers
to utilize OPP modifier functionality. Hook will return success if no
phandle is present for devices that do not use opp-modifier.
Signed-off-by: Dave Gerlach
---
drivers/base/power/opp.c | 8
1 file changed, 8 insert
Add an entry for opp-modifier which configures OPPs on 43xx. Within
this, nodes are defined with the opp-modifier propety that are defined as
a list of frequency, offset from base register, and efuse value.
The CPU node passes a phandle to the appropriate child node to get the
correct table.
This
Introduce framework to allow an OPP modifier driver to selectively
determine which possible OPPs for an SoC are available based on
register values found in SoC through a common API.
Three functions are exported, a register and unregister function for
the opp modifier drivers to notify the API of t
Add an entry for opp_modifier which configures OPPs on omap443x. Within
this, nodes are defined with the opp-modifier propety that are defined as
a list of frequency, offset from base register, and register value. The
CPU node passes a phandle to the appropriate child node to get the correct
table.
Add an entry for opp_modifier which configures OPPs on imx6q. Within
this nodes are defined with opp-modifier propety that are defined as a list
of frequency, offset from base register, and efuse value.
This is an untested example patch to show how opp-modifier could be used
for this platform.
Si
Driver to read from a register and depending on either set bits or
a specific known selectively enable or disable OPPs based on DT node.
Can support opp-modifier-reg-bit where single bits within the register
determine the availability of an OPP or opp-modifier-reg-val where a
certain value inside
On Fri, Mar 14, 2014 at 05:01:28PM +0100, Uwe Kleine-König wrote:
> While reviewing an i2c driver for efm32 that needs a similar property
> Wolfram Sang pointed out that "location" is a too generic name for something
> that is efm32 specific. So add an appropriate namespace and fall back to the
> g
Add an entry for opp_modifier which configures OPPs on AM4372. Within
this, nodes are defined with the opp-modifier propety that are defined as
a list of frequency, offset from base register, and efuse value.
The CPU node passes a phandle to the appropriate child node to get the
correct table.
Thi
Add an entry for opp_modifier which configures OPPs on am33xx. Within this
nodes are defined with opp-modifier propety that are defined as a list
of frequency, offset from base register, and efuse value. The CPU node
passes a phandle to the appropriate child node of the efuse node.
This patch also
There are many SoCs that can have different operating points supported
depending on different conditions even for otherwise identical parts.
It does not make sense to define many different iterations of a device tree
file for each possible permutation of the same device especially when this data
m
Add an entry for opp_modifier which configures OPPs on omap4460. Within
this, nodes are defined with the opp-modifier propety that are defined
as a list of frequency, offset from base register, and register value.
The CPU node passes a phandle to the appropriate child node to get the
correct table.
On Fri, Mar 14, 2014 at 05:35:57PM +0800, Hou Zhiqiang wrote:
> Get the spi_master's bus_num from DTS to make the spi_master's name
> static. So "mtdparts=spi.bus_num.chip_select:..." in cmdline can be
> used to asign mtd partions of spi flash.
If we are going to do this it shouldn't be device spe
On Friday 14 March 2014, Liviu Dudau wrote:
> On Fri, Mar 14, 2014 at 06:46:23PM +, Arnd Bergmann wrote:
> > On Friday 14 March 2014, Liviu Dudau wrote:
> >
> > > +int of_pci_range_to_resource(struct of_pci_range *range,
> > > + struct device_node *np, struct resource *res)
> > > +{
> >
From: David Miller
Date: Fri, 14 Mar 2014 15:07:20 -0400 (EDT)
> From: Vince Bridgers
> Date: Fri, 14 Mar 2014 09:04:38 -0500
>
>> This is the version 5 submission for the Altera Triple Speed Ethernet (TSE)
>> driver. All comments received during the version 2, 3, and 4 submissions
>> have
>>
On Friday 14 March 2014, Liviu Dudau wrote:
> >
>
> I haven't seen any reaction from Bjorn on this, so I threaded carefully on
> that
> subject. I'm new to this so I don't know how to handle this.
>
> To my mind, and looking at the way every architecture has been setup, the
> pcibios_*
> funct
From: Vince Bridgers
Date: Fri, 14 Mar 2014 09:04:38 -0500
> This is the version 5 submission for the Altera Triple Speed Ethernet (TSE)
> driver. All comments received during the version 2, 3, and 4 submissions have
> been accepted. Please find the change log and a description of the submission
On Friday 14 March 2014, Loc Ho wrote:
> > On Wednesday 12 March 2014, Loc Ho wrote:
> > gets called. Can you clarify what this register access does?
> > If it's just setting a index into a mux output, would it make
> > sense to have an optional DT property containing an integer with
> > the mux s
From: Richard Cochran
Date: Fri, 14 Mar 2014 15:39:18 +0100
> This could use a call to skb_tx_timestamp() somewhere around here.
This can happen in a follow-up patch, I won't block the initial
submission just for this.
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t
On Fri, Mar 14, 2014 at 06:46:23PM +, Arnd Bergmann wrote:
> On Friday 14 March 2014, Liviu Dudau wrote:
> > You are right, that was lazy of me. What about this version?
>
> Yes, that seems better. Thanks for fixing it up.
>
> But back to the more important question that I realized we have
>
On Friday 14 March 2014, Liviu Dudau wrote:
> You are right, that was lazy of me. What about this version?
Yes, that seems better. Thanks for fixing it up.
But back to the more important question that I realized we have
not resolved yet:
You now have two completely independent allocation functio
Hi Richard,
On Fri, Mar 14, 2014 at 9:39 AM, Richard Cochran
wrote:
> On Fri, Mar 14, 2014 at 09:04:44AM -0500, Vince Bridgers wrote:
>> +static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
>> +{
>> + struct altera_tse_private *priv = netdev_priv(dev);
>> + unsigned int
Hi,
> On Wednesday 12 March 2014, Loc Ho wrote:
> > This patch adds support for the APM X-Gene SoC AHCI SATA host controller
> > driver. It requires the corresponding APM X-Gene SoC PHY driver. This
> > initial version only supports Gen3 speed.
> >
> > Signed-off-by: Loc Ho
> > Signed-off-by: Tua
Hi,
On 03/14/2014 12:35 PM, Thomas Gleixner wrote:
> On Thu, 13 Mar 2014, Hans de Goede wrote:
>
>> Since sun4i and sun5i are single core SOCs there is no need to mask non
>> oneshot IRQs, to achieve this we use handle_fasteoi_irq with a dummy eoi.
>
> This is slightly wrong :)
>
> Even on a SM
Am 14.03.2014 14:54, schrieb Linus Walleij:
On Fri, Mar 14, 2014 at 1:38 PM, Alexander Holler wrote:
In that case it is hardly a fix that we need to rush out to the entire
world.
And I thought the reason for -rc is actually to fix bugs. But I never
understood the magical ways and timings pat
On Fri, Mar 14, 2014 at 05:38:08PM +, Arnd Bergmann wrote:
> On Friday 14 March 2014, Catalin Marinas wrote:
> > On Fri, Mar 14, 2014 at 03:34:18PM +, Liviu Dudau wrote:
> > > --- /dev/null
> > > +++ b/arch/arm64/kernel/pci.c
> > [...]
> > > +int pci_register_io_range(phys_addr_t address, r
On Thu, Mar 13, 2014 at 07:07:43PM -0700, Bjorn Andersson wrote:
> This bus driver supports the QUP i2c hardware controller in the Qualcomm SOCs.
> The Qualcomm Universal Peripheral Engine (QUP) is a general purpose data path
> engine with input/output FIFOs and an embedded i2c mini-core. The drive
On Fri, Mar 14, 2014 at 04:34:19PM +, Tomi Valkeinen wrote:
> On 14/03/14 18:04, Felipe Balbi wrote:
> > On Fri, Mar 14, 2014 at 02:07:45PM +, Mark Rutland wrote:
> >> On Fri, Mar 14, 2014 at 11:07:05AM +, Tomi Valkeinen wrote:
> >>> On 14/03/14 12:19, Tomi Valkeinen wrote:
> On 14
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patchset support devicetree and use common ppmu driver instead of
individual code of exynos4_bus.c to remove duplicate code. Also this patchset
get the resources for busfreq from dt data by using DT helper function.
- PPMU register addres
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patch disable ppmu clocks before entering suspend state to remove
power-leakage and enable ppmu clocks on resume function.
I don't think there is any need for this, because all the clocks are
stopped anyway in SLEEP mode.
Best regard
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
This patch fix bug about resource leak when happening probe fail and code clean
to add debug message.
Signed-off-by: Chanwoo Choi
---
drivers/devfreq/exynos/exynos4_bus.c | 32 ++--
1 file changed, 26 insertion
Hi Chanwoo,
On 13.03.2014 09:17, Chanwoo Choi wrote:
There are not the clock controller of ppmudmc0/1. This patch control the clock
of ppmudmc0/1 which is used for monitoring memory bus utilization.
Also, this patch code clean about regulator control and free resource
when calling exit/remove f
On Friday 14 March 2014, Catalin Marinas wrote:
> On Fri, Mar 14, 2014 at 03:34:18PM +, Liviu Dudau wrote:
> > --- /dev/null
> > +++ b/arch/arm64/kernel/pci.c
> [...]
> > +int pci_register_io_range(phys_addr_t address, resource_size_t size)
> [...]
> > +unsigned long pci_address_to_pio(phys_add
Hi Chanwoo, Mark,
On 14.03.2014 11:56, Chanwoo Choi wrote:
Hi Mark,
On 03/14/2014 07:35 PM, Mark Rutland wrote:
On Fri, Mar 14, 2014 at 07:14:37AM +, Chanwoo Choi wrote:
Hi Mark,
On 03/14/2014 02:53 AM, Mark Rutland wrote:
On Thu, Mar 13, 2014 at 08:17:29AM +, Chanwoo Choi wrote:
T
On Friday 14 March 2014, Rob Herring wrote:
> On Wed, Mar 12, 2014 at 11:58 AM, Arnd Bergmann wrote:
> > On Wednesday 12 March 2014 15:19:48 Grygorii Strashko wrote:
> >> > Isn't the question here how do we handle restrictions added by the
> >> > bus? It seems while this series adds support for ha
Hi Robert,
On 14.03.2014 11:13, Robert Baldyga wrote:
This patch adds device tree node for IRQ used by max8997.
Generally, this patch does not add just a node, but rather "IRQ line
specification for the MAX8997 PMIC chip and necessary pinctrl group to
configure pull-up and driver strength o
On Fri, Mar 14, 2014 at 05:05:28PM +, Arnd Bergmann wrote:
> On Friday 14 March 2014, Liviu Dudau wrote:
> > +int of_pci_range_to_resource(struct of_pci_range *range,
> > + struct device_node *np, struct resource *res)
> > +{
> > + res->flags = range->flags;
> > + if (res->fla
Hi Yuvaraj,
On 14.03.2014 09:26, Yuvaraj Kumar wrote:
Any comments on this?
On Mon, Mar 3, 2014 at 4:45 PM, Yuvaraj Kumar C D wrote:
Commit 275dcd2 "ARM: dts: add max77686 pmic node for smdk5250" added
required LDO's for SMDK5250 boards.Currently LDO10 is turned off.As LDO10,
enable/disable t
Hi Yuvaraj,
On 14.03.2014 09:25, Yuvaraj Kumar wrote:
kgene,
Please pick this patch.
On Tue, Mar 4, 2014 at 7:02 PM, Kishon Vijay Abraham I wrote:
On Tuesday 04 March 2014 04:40 PM, Yuvaraj Kumar C D wrote:
This patch adds dt entry for ahci sata controller and its
corresponding phy contro
On Fri, Mar 14, 2014 at 03:34:18PM +, Liviu Dudau wrote:
> --- /dev/null
> +++ b/arch/arm64/kernel/pci.c
[...]
> +int pci_register_io_range(phys_addr_t address, resource_size_t size)
[...]
> +unsigned long pci_address_to_pio(phys_addr_t address)
[...]
> +void pcibios_fixup_bus(struct pci_bus *b
Add a testcase for the find_node_by_path() function to make sure it
handles all the valid scenarios.
Signed-off-by: Grant Likely
---
drivers/of/selftest.c | 39 +
drivers/of/testcase-data/tests-phandle.dtsi | 6 -
2 files changed, 44 inserti
The strchrnul() variant helpfully returns a the end of the string
instead of a NULL if the requested character is not found. This can
simplify string parsing code since it doesn't need to expicitly check
for a NULL return. If a valid string pointer is passed in, then a valid
null terminated string
Make of_find_node_by_path() handle aliases as prefixes. To make this
work the name search is refactored to search by path component instead
of by full string. This should be a more efficient search, and it makes
it possible to start a search at a subnode of a tree.
Signed-off-by: David Daney
Sign
Searching for a node by path should also take into account an /aliases
reference. This series reworks the of_find_node_by_path() code to handle
that use-case easily. It also makes it possible to start a search at a
child node, which Pantelis needs for the FDT overlay work.
I've done some simple te
On Friday 14 March 2014, Liviu Dudau wrote:
> +int of_pci_range_to_resource(struct of_pci_range *range,
> + struct device_node *np, struct resource *res)
> +{
> + res->flags = range->flags;
> + if (res->flags & IORESOURCE_IO) {
> + unsigned long port = -1;
> +
Hi KyongHo,
On 14 March 2014 19:13, Tomasz Figa wrote:
> Hi KyongHo,
>
>
> On 14.03.2014 06:09, Cho KyongHo wrote:
>>
>> exynos-iommu driver must care about master H/W's gate clock as well as
>> System MMU's gate clock. To enhance readability of the source code,
>> macros to gate/ungate those cl
On Wed, Mar 12, 2014 at 09:14:39AM -0400, Matt Porter wrote:
> The BCM28155-AP board has a bootloader that expects the camldo1
> regulator to be enabled on entry. Currently, the camldo1 regulator
> is disabled when no longer in use as is the case during a reboot /
> warm reset. This causes the earl
On Wed, Mar 12, 2014 at 10:07:17AM -0400, Matt Porter wrote:
> Add a dtsi to support the BCM590xx PMUs used by the BCM281xx family
> of SoCs. Enable regulators for use with the dwc2 and sdhci on
> bcm28155-ap.
>
> Signed-off-by: Tim Kryger
> Signed-off-by: Matt Porter
> Reviewed-by: Markus Mayer
On Thu, Mar 06, 2014 at 09:45:55AM -0800, Florian Fainelli wrote:
> Low-level debugging using the Broadcom Kona UART only makes sense on the
> ARCH_BCM_MOBILE platform and would otherwise prevent ARCH_BCM_63XX from
> picking up the right UART implementation by default.
>
> Signed-off-by: Florian F
On Thu, Mar 06, 2014 at 05:18:11PM +0800, Markus Mayer wrote:
> This series adds initial support for the Broadcom BCM21664 mobile SoC.
>
> The series depends on the series "ARM: bcm281xx: Consolidate code":
> https://lkml.org/lkml/2014/2/25/548
>
> Changes since v1:
>
> - Fixed typo ("21644"
On 02/24/2014 08:49 PM, Stefano Stabellini wrote:
> On Mon, 24 Feb 2014, gre...@linuxfoundation.org wrote:
> Julien is proposing to store the list of "safe" devices on an hash table
> in the Xen specific code (in arch/arm/xen/enlighten.c, see
> http://marc.info/?l=linux-kernel&m=139291370526082&w=
On 14/03/14 18:04, Felipe Balbi wrote:
> On Fri, Mar 14, 2014 at 02:07:45PM +, Mark Rutland wrote:
>> On Fri, Mar 14, 2014 at 11:07:05AM +, Tomi Valkeinen wrote:
>>> On 14/03/14 12:19, Tomi Valkeinen wrote:
On 14/03/14 12:14, Mark Rutland wrote:
> I can't see anything obviousl
On Fri, Mar 14, 2014 at 5:08 PM, Alan Tull wrote:
> From: Alan Tull
>
> Fix size-cells to show use of OF_GPIO_ACTIVE_LOW flag.
>
> Signed-off-by: Alan Tull
OK patch applied.
Yours,
Linus Walleij
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On Fri, Mar 14, 2014 at 04:14:03PM +, Mark Rutland wrote:
> On Fri, Mar 14, 2014 at 08:55:26AM +, Steffen Trumtrar wrote:
> > +Optional properties:
> > +- num-chipselects : The number of chipselects.
> If this is optional, when wuold I need to set this? What's the default
> assumption?
>
From: Alan Tull
Fix size-cells to show use of OF_GPIO_ACTIVE_LOW flag.
Signed-off-by: Alan Tull
---
.../devicetree/bindings/gpio/snps-dwapb-gpio.txt |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
b/Docume
On Fri, Mar 14, 2014 at 04:14:03PM +, Mark Rutland wrote:
> > +Synopsys DesignWare SPI master controller.
> > +
> > +Required properties:
> > +- compatible : "snps,dw-spi-mmio"
> Is there not a better name than "dw-spi-mmio"?
> What's the full name of the device, as on a datasheet? Is there
Hi KyongHo,
On 14.03.2014 06:10, Cho KyongHo wrote:
Some master device descriptor like fimc-is which is an abstraction
of very complex H/W may have multiple System MMUs. For those devices,
the design of the link between System MMU and its master H/W is needed
to be reconsidered.
A link structur
On Fri, Mar 14, 2014 at 08:55:26AM +, Steffen Trumtrar wrote:
> Allow probing the dw-mmio from devicetree.
>
> Signed-off-by: Steffen Trumtrar
> ---
> This was tested on Socfpga and v3.14-rc6
>
> .../devicetree/bindings/spi/spi-dw-mmio.txt| 25
> ++
> drivers/sp
On Fri, Mar 14, 2014 at 05:01:28PM +0100, Uwe Kleine-König wrote:
> While reviewing an i2c driver for efm32 that needs a similar property
> Wolfram Sang pointed out that "location" is a too generic name for something
> that is efm32 specific. So add an appropriate namespace and fall back to the
> g
Hi KyongHo,
On 14.03.2014 06:10, Cho KyongHo wrote:
This adds support for Suspend to RAM and Runtime Power Management.
Since System MMU is located in the same local power domain of its
master H/W, System MMU must be initialized before it is working if
its power domain was ever turned off. TLB i
On Fri, Mar 14, 2014 at 02:07:45PM +, Mark Rutland wrote:
> On Fri, Mar 14, 2014 at 11:07:05AM +, Tomi Valkeinen wrote:
> > On 14/03/14 12:19, Tomi Valkeinen wrote:
> > > On 14/03/14 12:14, Mark Rutland wrote:
> > >
> > >> I can't see anything obviously wrong in platform_device_del. Do you
While reviewing an i2c driver for efm32 that needs a similar property
Wolfram Sang pointed out that "location" is a too generic name for something
that is efm32 specific. So add an appropriate namespace and fall back to the
generic name in case of failure.
Signed-off-by: Uwe Kleine-König
---
dri
While reviewing an i2c driver for efm32 that needs a similar property
Wolfram Sang pointed out that "location" is a too generic name for something
that is efm32 specific. So add an appropriate namespace and fall back to the
generic name in case of failure.
Signed-off-by: Uwe Kleine-König
---
dri
I'm dropping the RFC tag now as I have the feeling that we are starting to have
something in
a good shape that can be pushed for more testing in near future.
This is v7 of my attempt to add support for a generic pci_host_bridge
controller created
from a description passed in the device tree.
Ch
From: Catalin Marinas
The patch moves the PCI I/O space (currently at 64K) before the
earlyprintk mapping and extends it to 16MB.
Signed-off-by: Catalin Marinas
---
Documentation/arm64/memory.txt | 16 ++--
arch/arm64/include/asm/io.h| 2 +-
2 files changed, 11 insertions(+),
On 03/14/2014 04:54 PM, Kishon Vijay Abraham I wrote:
>
>
> On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
>> On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
>>> Hi Roger,
>>>
>>> On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controlle
Make it easier to discover the domain number of a bus by storing
the number in pci_host_bridge for the root bus. Several architectures
have their own way of storing this information, so it makes sense
to try to unify the code. While at this, add a new function that
creates a root bus in a given dom
Hi,
This patch adds support for PCI to AArch64. It is based on my v7 patch
that adds support for creating generic host bridge structure from
device tree. With that in place, I was able to boot a platform that
has PCIe host bridge support and use a PCIe network card.
I have dropped the RFC tag fro
Use the generic host bridge functions to provide support for
PCI Express on arm64. There is no support for ISA memory.
Signed-off-by: Liviu Dudau
Tested-by: Tanmay Inamdar
---
arch/arm64/Kconfig| 19 +++-
arch/arm64/include/asm/Kbuild | 1 +
arch/arm64/include/asm/io.h | 3 +-
The inline version of ioport_map() that gets used when !CONFIG_GENERIC_IOMAP
is wrong. It returns a mapped (i.e. virtual) address that can start from
zero and completely ignores the PCI_IOBASE and IO_SPACE_LIMIT that most
architectures that use !CONFIG_GENERIC_MAP define.
Signed-off-by: Liviu Duda
This is a useful function and we should make it visible outside the
generic PCI code. Export it as a GPL symbol.
Signed-off-by: Liviu Dudau
Tested-by: Tanmay Inamdar
---
drivers/pci/host-bridge.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/host-bridge.c b/d
The ranges property for a host bridge controller in DT describes
the mapping between the PCI bus address and the CPU physical address.
The resources framework however expects that the IO resources start
at a pseudo "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.
The conversion fr
Before commit 7b5436635800 the pci_host_bridge was created before the root bus.
As that commit has added a needless dependency on the bus for
pci_alloc_host_bridge()
the creation order has been changed for no good reason. Revert the order of
creation as we are going to depend on the pci_host_bridg
Some architectures do not share x86 simple view of the PCI I/O space
and instead use a range of addresses that map to bus addresses. For
some architectures these ranges will be expressed by OF bindings
in a device tree file.
Introduce a pci_register_io_range() helper function that can be used
by t
Several platforms use a rather generic version of parsing
the device tree to find the host bridge ranges. Move the common code
into the generic PCI code and use it to create a pci_host_bridge
structure that can be used by arch code.
Based on early attempts by Andrew Murray to unify the code.
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