Exynos4412-trats2 board have light/proximity sensor.
This patch add cm36651 light/ proximity sensor node for exynos4412.
cm36651 is required properties as below.
- Use i2c-gpio for cm36651 sensor.
- Use fixed regulator for the IR LED.
It is a part of the cm36651 for proximity detection.
-
This patch fixed gpio key device node.
First, fix incorrect gpio property.
And then, add ok-key node where locate bottom center.
I have tested on exynos4412-trats2 board.
Signed-off-by: Beomho Seo beomho@samsung.com
Signed-off-by: MyungJoo Ham myungjoo@samsung.com
---
This patchset add some device node for exynos4412-trats2.
It is based on v3.15-next/dt-samsung-2 branch.
exynos4412-trats2.dts
- Fix incorrect compatible. Compatible of AK8975 are ak8975 or
asahi-kasei,ak8975.
- Add cm36651 light/proximity sensor device node.
- Change gpio-key device node. fix
The patch adds LD9040 parallel RGB panel driver with SPI control interface.
The driver uses drm_panel framework.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
v2: removed useless include
v3: added SPI dependency to Kconfig
---
drivers/gpu/drm/panel/Kconfig| 7 +
Hi,
Huang Shijie wrote:
On Fri, Mar 21, 2014 at 11:50:17AM +0100, Lothar Waßmann wrote:
With a flash-based BBT there is no reason to move the Factory Bad
Block Marker from the data area buffer (to where it is mapped by the
GPMI NAND controller) to the OOB buffer. Thus, make this feature
On Tue, Mar 25, 2014 at 06:19:24PM +, j...@ringle.org wrote:
From: Jon Ringle jrin...@gridpoint.com
This patch adds the devicetree documentation for the NXP SC16IS7XX UARTs.
Signed-off-by: Jon Ringle jrin...@gridpoint.com
---
.../devicetree/bindings/serial/nxp,sc16is7xx.txt | 35
Hi Sergei,
On: 25/03/2014 19:22, Sergei wrote:
Subject: Re: [PATCH v5 5/9] dt-bindings: pci: rcar pcie device tree
bindings
Hello.
On 03/25/2014 07:56 PM, Phil Edworthy wrote:
This patch adds the bindings for the R-Car PCIe driver. The driver
resides under
This implements basic device tree boot support for the RealView
platforms, with a basic device tree for ARM PB1176 as an example.
The implementation is done with a new DT-specific board file
using only pre-existing bindings for the basic IRQ, timer and
serial port drivers. A new compatible type
On 25 March 2014 22:45, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Mar 21, 2014 at 1:14 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
Add a node in DT for the proper regulator which means we can move away
from the mmci platform data which currently holds the corresponding OCR
mask.
On 26 March 2014 10:27, Ulf Hansson ulf.hans...@linaro.org wrote:
On 25 March 2014 22:45, Linus Walleij linus.wall...@linaro.org wrote:
On Fri, Mar 21, 2014 at 1:14 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
Add a node in DT for the proper regulator which means we can move away
from the
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
Hi,
On 03/19/2014 08:21 PM, Carlo Caione wrote:
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione ca...@caione.org
Note this breaks the kernel on sun6i / A31 since we don't have a
From: Arnd Bergmann
On Tuesday 25 March 2014 10:16:28 Florian Fainelli wrote:
Ok, well that's really unfortunate, to achieve the best of everything,
the workaround should probably look like:
- keep reclaiming TX buffers in ndo_start_xmit() in case you push more
packets to the NICs
Hi,
On 03/26/2014 10:39 AM, Maxime Ripard wrote:
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
Hi,
On 03/19/2014 08:21 PM, Carlo Caione wrote:
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione ca...@caione.org
Note this breaks
This patch adds IRQ line specification for the MAX8997 chip and necessary
pinctrl group to configure pull-up and driver strength of the pin.
It's needed for proper handling of IRQs coming from MAX8997 multifunction
device (IRQs are used by PMIC, MUIC and RTC).
Signed-off-by: Robert Baldyga
On Tue, Mar 25, 2014 at 10:12:14PM +, Tanmay Inamdar wrote:
Hello Liviu,
Thanks for taking a look. Please see inline.
On Tue, Mar 25, 2014 at 7:02 AM, Liviu Dudau liviu.du...@arm.com wrote:
On Wed, Mar 19, 2014 at 11:12:39PM +, Tanmay Inamdar wrote:
This patch adds the
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
On Wed, Mar 26, 2014 at 04:52:40AM +, Chao Xie wrote:
From: Chao Xie chao@marvell.com
MMP timer is attached to APB bus, It has the following
limitation.
1. When get count of timer counter, it need some delay
to get a stable count.
2. When set match register, it need disable the
于 2014年03月26日 16:51, Lothar Waßmann 写道:
I don't see why this should not be supported on i.MX28 (i.MX23 doesn't
do byteswapping anyway, so this wouldn't change anything for i.MX23).
The partitions used by Linux need not necessarily be accessible for the
Boot ROM code (and vice versa).
But the
On Wednesday 26 March 2014 10:27:40 Linus Walleij wrote:
This implements basic device tree boot support for the RealView
platforms, with a basic device tree for ARM PB1176 as an example.
The implementation is done with a new DT-specific board file
using only pre-existing bindings for the
On Wed, Mar 26, 2014 at 10:27:35AM +, Heiko Stübner wrote:
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko
Hi,
Huang Shijie wrote:
于 2014年03月26日 16:51, Lothar Waßmann 写道:
I don't see why this should not be supported on i.MX28 (i.MX23 doesn't
do byteswapping anyway, so this wouldn't change anything for i.MX23).
The partitions used by Linux need not necessarily be accessible for the
Boot ROM
Am Mittwoch, 26. März 2014, 11:00:24 schrieb Mark Rutland:
On Wed, Mar 26, 2014 at 10:27:35AM +, Heiko Stübner wrote:
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the
APM X-Gene Storm SoC supports 4 serial ports. This patch adds device nodes
for serial ports 1 to 3 (a device node for serial port 0 is already present
in the dts file).
This patch also sets the compatible property of serial nodes to ns16550a.
Signed-off-by: Vinayak Kale vk...@apm.com
---
On Wed, Mar 26, 2014 at 5:08 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Mar 25, 2014 at 06:19:24PM +, j...@ringle.org wrote:
+- interrupt-parent: The phandle for the interrupt controller that
+ services interrupts for this IC.
+- interrupts: Specifies the interrupt source of the
On Wed, Mar 26, 2014 at 12:49:59PM +, Jon Ringle wrote:
On Wed, Mar 26, 2014 at 5:08 AM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Mar 25, 2014 at 06:19:24PM +, j...@ringle.org wrote:
+- interrupt-parent: The phandle for the interrupt controller that
+ services interrupts
From: Jon Ringle jrin...@gridpoint.com
The SC16IS7xx is a slave I2C-bus/SPI interface to a single-channel
high performance UART. The SC16IS7xx’s internal register set is
backward-compatible with the widely used and widely popular 16C450.
The SC16IS7xx also provides additional advanced features
From: Jon Ringle jrin...@gridpoint.com
This patch adds the devicetree documentation for the NXP SC16IS7XX UARTs.
Signed-off-by: Jon Ringle jrin...@gridpoint.com
---
.../devicetree/bindings/serial/nxp,sc16is7xx.txt | 33 ++
1 file changed, 33 insertions(+)
create mode
This patch series adds support for PCIe in DRA7xx including drivers and dt
data. PCIe in DRA7xx uses desingware IP and hence this re-uses the
pcie desingware driver (pcie-designware.c) by Jingoo.
This patch series depends on a few patches that is already in -next.
Tested broadcom PCIe card and
Added dt data for PCIe PHY as a child node of ocp2scp3.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 16
1 file changed, 16 insertions(+)
diff --git
Now that we have added PCIe driver for DRA7 SOCs, enable PCI on
DRA7 SOCs.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 46f8c53..352f252
Added dt data for PCIe controller. This node contains dt data for
both the DRA7 part of designware controller and for the designware core.
The documention for this node can be found @ ../bindings/pci/ti-pci.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi
PCIe PHY uses an external pll instead of the internal pll used by SATA
and USB3. So added support in pipe3 PHY to use external pll
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt |8 +-
drivers/phy/phy-ti-pipe3.c
On Wed, Mar 26, 2014 at 4:27 AM, Linus Walleij linus.wall...@linaro.org wrote:
This implements basic device tree boot support for the RealView
platforms, with a basic device tree for ARM PB1176 as an example.
The implementation is done with a new DT-specific board file
using only pre-existing
Added dt data for PCIe PHY control module used by PCIe PHY.
The documention for this node can be found @ ../bindings/phy/ti-phy.txt
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7.dtsi |8
1 file changed, 8 insertions(+)
diff --git
Added missing 32khz clock used by PCIe PHY.
The documention for this node can be found @ ../bindings/clock/ti/gate.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |8
1 file changed, 8 insertions(+)
diff --git
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
From: Keerthy j-keer...@ti.com
Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |2 +-
1 file changed, 1
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/mach-omap2/cm2_7xx.h |4 ++
On Wednesday 26 March 2014 08:59:32 Rob Herring wrote:
On Wed, Mar 26, 2014 at 4:27 AM, Linus Walleij linus.wall...@linaro.org
wrote:
menu RealView platform type
depends on ARCH_REALVIEW
+config REALVIEW_DT
+ bool Support RealView(R) Device Tree based boot
+
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/pci/ti-pci.txt | 35 ++
drivers/pci/host/Kconfig | 10
From: Keerthy j-keer...@ti.com
Add divider table to optfclk_pciephy_div clock.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |1 +
1 file changed, 1 insertion(+)
diff --git
In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
address. So whenever the cpu issues a read/write request, the 4 most
significant bits are used by L3 to determine the target controller.
For example, the cpu reserves 0x2000_ - 0x2FFF_ for PCIe controller but
Hi,
this patch series contains some cleanups for at86rf230 driver.
The patch series contains:
- Removing of the irq_type inside the platform data and use
irq_get_trigger_type instead.
- Use of devm_* functions.
- At least we add a missed devicetree documentation. Sorry I didn't create
This patch adds devicetree bindings for the at86rf230 IEEE 802.15.4 SPI
device driver.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
.../bindings/net/ieee802154/at86rf230.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
This patch removes the platform data for the irq_type. We use instead
the irq_get_trigger_type function to get these flags which should
already configured by the interrupt controller.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
drivers/net/ieee802154/at86rf230.c | 28
This patch replace request_irq with devm_request_irq. With
devm_request_irq we don't need to care about freeing the irq.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
drivers/net/ieee802154/at86rf230.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git
This patch removes the pr_* functions and replace it with the dev_*
print functions.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
drivers/net/ieee802154/at86rf230.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ieee802154/at86rf230.c
This patch replace the gpio_request functions with devm_gpio_request_one
functions. Then we don't need to take care about freeing gpios.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
drivers/net/ieee802154/at86rf230.c | 53 +-
1 file changed, 12
We don't need to set these values at request_irq. The interrupt line is
already configured to same value like irq_get_trigger_type returned.
Signed-off-by: Alexander Aring alex.ar...@gmail.com
---
drivers/net/ieee802154/at86rf230.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
Dear Rob
On Mon, Mar 24, 2014 at 10:17 PM, Rob Herring robherri...@gmail.com wrote:
+ dma_map_single(ndev-dev, skb-data,
+ RX_BUF_SIZE, DMA_FROM_DEVICE);
This is incorrect.
buf = buffer alloc()
/* CPU owns buffer and can read/write it, device does not */
On Wed, Mar 19, 2014 at 6:12 PM, Tanmay Inamdar tinam...@apm.com wrote:
This patch adds the device tree nodes for APM X-Gene PCIe controller and
PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts
nodes are added.
[snip]
+ pcie0: pcie@1f2b {
+
Hi,
On 03/26/2014 11:04 AM, Hans de Goede wrote:
Hi,
On 03/26/2014 10:39 AM, Maxime Ripard wrote:
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
Hi,
On 03/19/2014 08:21 PM, Carlo Caione wrote:
This patch adds DTS entries for NMI controller as child of GIC.
On Wed, Mar 26, 2014 at 8:57 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
On Wednesday 26 March 2014 08:15 PM, Rob Herring wrote:
On Wed, Mar 26, 2014 at 8:57 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay
On 03/22/2014 06:28 AM, Sebastian Andrzej Siewior wrote:
On 03/21/2014 11:15 PM, delicious quinoa wrote:
snps,nr-gpios = 27;
As noted on other thread, gpio2 is 27 wide, despite what the
documentation says. When I made that change and remove your other two
patches the gpios worked for me on
On Wed, Mar 26, 2014 at 02:28:42PM +, Rob Herring wrote:
On Wed, Mar 19, 2014 at 6:12 PM, Tanmay Inamdar tinam...@apm.com wrote:
This patch adds the device tree nodes for APM X-Gene PCIe controller and
PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts
nodes are
Hi Josh,
Thank you for the patch.
On Tuesday 25 March 2014 18:45:20 Josh Wu wrote:
This patch add the DT support for Atmel ISI driver.
It use the same v4l2 DT interface that defined in video-interfaces.txt.
Signed-off-by: Josh Wu josh...@atmel.com
Cc: devicetree@vger.kernel.org
On Wed, Mar 26, 2014 at 09:28:42AM -0500, Rob Herring wrote:
Where is the right place for config space? This binding has it here
and others have it in ranges.
I think all the drivers in drivers/pci/host use 'reg', this was
discussed in the dt-bindings list and AFAIK no new drivers have used
Hello Chris, Ulf,
Do you have any comments on the patches?
The arch code that will use this driver is already in mainline. The
regulators support seem to be still on its way, but this driver also
works fine with dummy regulators.
Thanks,
Georgi
On 03/10/2014 05:37 PM, Georgi Djakov wrote:
On Wednesday 26 March 2014 11:56:30 Arnd Bergmann wrote:
+ /*
+ * Generic RealView fixup
+ * Most RealView platforms have 512MB contiguous RAM at 0x7000.
+ * Half of this is mirrored at 0.
+ */
+ else {
+#ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
+
On Mon, 24 Mar 2014 12:15:23 +0200
Jyri Sarha jsa...@ti.com wrote:
This patch is implemented on top of late patches from Jean-Francois
Moine [1].
These patches implement the main part of the simple-card changes
discussed in alsa-devel mailing list [2].
Acked-by: Jean-Francois Moine
After commit 1771b10d605d26ccee771a7fb4b08718c124097a
clk: respect the clock dependencies in of_clk_init
the order of registering clock providers and their corresponding
clocks may change. This commit currently causes a regression
on Exynos4 platforms, where fixed clocks are now being registered
...@samsung.com
Still not able to boot with this patch applied:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Booting Linux on physical CPU 0x0
Linux version 3.14.0-rc8-next-20140326+ (fabio@fabio-Latitude-E6410)
(gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-1ubuntu1) ) #948 SMP Wed
Mar 26 15
Hi Fabio,
On 03/26/2014 07:33 PM, Fabio Estevam wrote:
On Wed, Mar 26, 2014 at 3:22 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
[...]
Still not able to boot with this patch applied:
Perhaps a change as below helps ?
From 85ee85e4a92b42442354f3f2454be50c173e1c59 Mon Sep 17 00:00:00
On Wed, Mar 26, 2014 at 4:57 PM, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
Perhaps a change as below helps ?
From 85ee85e4a92b42442354f3f2454be50c173e1c59 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki s.nawro...@samsung.com
Date: Wed, 26 Mar 2014 20:54:13 +0100
Subject:
On Wed, Mar 26, 2014 at 03:38:05PM +0100, Hans de Goede wrote:
Hi,
Hi Hans,
On 03/26/2014 11:04 AM, Hans de Goede wrote:
Hi,
On 03/26/2014 10:39 AM, Maxime Ripard wrote:
On Wed, Mar 26, 2014 at 09:39:31AM +0100, Hans de Goede wrote:
Hi,
On 03/19/2014 08:21 PM, Carlo Caione wrote:
On 26/03/2014 21:14, Fabio Estevam wrote:
On Wed, Mar 26, 2014 at 4:57 PM, Sylwester Nawrocki
sylvester.nawro...@gmail.com wrote:
Perhaps a change as below helps ?
From 85ee85e4a92b42442354f3f2454be50c173e1c59 Mon Sep 17 00:00:00 2001
From: Sylwester Nawrocki s.nawro...@samsung.com
Date:
Switching to timer-based delay loop
Division by zero in kernel.
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.14.0-rc8-next-20140326+ #951
Backtrace:
[80011cd4] (dump_backtrace) from [80011e70] (show_stack+0x18/0x1c)
r6: r5: r4: r3:
[80011e58] (show_stack) from
From: Byungho An bh74...@samsung.com
Date: Tue, 25 Mar 2014 12:10:47 -0700
This is 14th posting for SAMSUNG SXGBE driver.
Series applied to net-next, thanks.
--
To unsubscribe from this list: send the line unsubscribe devicetree in
the body of a message to majord...@vger.kernel.org
More
Allwinner A20/A31 SoCs have special registers to control / (un)mask /
acknowledge NMI. This NMI controller is separated and independent from GIC.
This patch adds a new irqchip to manage NMI.
Signed-off-by: Carlo Caione ca...@caione.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
This patch adds DTS entries for NMI controller as child of GIC.
Signed-off-by: Carlo Caione ca...@caione.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 8
arch/arm/boot/dts/sun7i-a20.dtsi | 8
2 files changed, 16
Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
Three register are present to (un)mask, control and acknowledge NMI.
These two patches add a new irqchip driver in cascade with GIC.
Changes since v1:
- added binding document
Changes since v2:
- fixed
Added documentation for NMI irqchip.
Signed-off-by: Carlo Caione ca...@caione.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
.../allwinner,sun67i-sc-nmi.txt| 27 ++
1 file changed, 27 insertions(+)
create mode 100644
On Wednesday 26 March 2014, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hi,
These 3 patches are based on Arnd's patch to fix the allmodconfig for the
dwmac-socfpga implementation. I just broke the patch out into drivers,
dts, and dts documentation.
The original
On Tue, 2014-03-25 at 18:34 -0500, dingu...@altera.com wrote:
- #size-cells = 1;
- compatible = altr,socfpga-stmmac;
- altr,sysmgr-syscon = sysmgr 0x60;
+ gmac0: ethernet@ff70 {
+ compatible =
Add Capella Microsystem CM3218X family Ambient Light Sensor IIO driver.
This driver will convert raw data to lux value. Default parameters are
for reference only. It will detect ACPI table to load per-system manufacturing
parameters.
V2: Follow Jonathan Cameron's advise to separate device id.
On 26 March 2014 17:42, Georgi Djakov gdja...@mm-sol.com wrote:
Hello Chris, Ulf,
Do you have any comments on the patches?
The arch code that will use this driver is already in mainline. The
regulators support seem to be still on its way, but this driver also works
fine with dummy
On 03/26/2014 04:54 PM, Arnd Bergmann wrote:
On Wednesday 26 March 2014, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hi,
These 3 patches are based on Arnd's patch to fix the allmodconfig for the
dwmac-socfpga implementation. I just broke the patch out into drivers,
dts,
On 03/26/2014 05:12 PM, Gerhard Sittig wrote:
On Tue, 2014-03-25 at 18:34 -0500, dingu...@altera.com wrote:
- #size-cells = 1;
- compatible = altr,socfpga-stmmac;
- altr,sysmgr-syscon = sysmgr 0x60;
+ gmac0:
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
changes since v1:
- add a short
On Wednesday 26 March 2014 19:05:13 Dinh Nguyen wrote:
On 03/26/2014 04:54 PM, Arnd Bergmann wrote:
On Wednesday 26 March 2014, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hi,
These 3 patches are based on Arnd's patch to fix the allmodconfig for the
Add the binding description for the Kona PWM controller found on Broadcom's
mobile SoCs.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Alex Elder el...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
.../devicetree/bindings/pwm/bcm-kona-pwm.txt | 21
Add the device tree node for the PWM on bcm11351 SoCs.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Alex Elder el...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
arch/arm/boot/dts/bcm11351.dtsi |8
1 file changed, 8 insertions(+)
diff --git
Mark the PWM as enabled on the bcm28155 AP board.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Alex Elder el...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
arch/arm/boot/dts/bcm28155-ap.dts |4
1 file changed, 4 insertions(+)
diff --git
Add support for the six-channel Kona PWM controller found on Broadcom
mobile SoCs like bcm281xx.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Alex Elder el...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
drivers/pwm/Kconfig|9 ++
This series introduces the driver for the Kona PWM controller found in
Broadcom mobile SoCs like bcm281xx and updates the device tree and the
defconfig to enable use of this hardware on the bcm28155 AP board.
Changes since v4:
- Added in real polarity support
- Labeled trigger bits as such
Enable PWM drivers and the PWM-based backlight driver.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Alex Elder el...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
arch/arm/configs/bcm_defconfig |3 +++
1 file changed, 3 insertions(+)
diff --git
On Wed, Mar 26, 2014 at 6:41 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Wed, Mar 26, 2014 at 04:52:40AM +, Chao Xie wrote:
From: Chao Xie chao@marvell.com
MMP timer is attached to APB bus, It has the following
limitation.
1. When get count of timer counter, it need some delay
On Mon, Mar 24, 2014 at 12:15:23PM +0200, Jyri Sarha wrote:
This patch is implemented on top of late patches from Jean-Francois
Moine [1].
Applied both, thanks.
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Hi,
On Wed, Mar 26 2014, Ulf Hansson wrote:
On 26 March 2014 17:42, Georgi Djakov gdja...@mm-sol.com wrote:
Hello Chris, Ulf,
Do you have any comments on the patches?
The arch code that will use this driver is already in mainline. The
regulators support seem to be still on its way, but this
On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Hi Kishon,
Long time no see! I added trivial
From: Dinh Nguyen dingu...@altera.com
This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
.../devicetree/bindings/net/socfpga-dwmac.txt | 27
From: Dinh Nguyen dingu...@altera.com
Like the STi and sunxi series SOCs, Altera's SOCFPGA also needs a glue layer
on top of the Synopsys gmac IP.
This patch adds the platform driver for the glue layer which configures the IP
before the generic STMMAC driver takes over.
Signed-off-by: Dinh
From: Dinh Nguyen dingu...@altera.com
Add the clocks and clock-names property to the base stmmac dts bindings
document.
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
Documentation/devicetree/bindings/net/stmmac.txt |6 ++
1 file changed, 6 insertions(+)
diff --git
From: Dinh Nguyen dingu...@altera.com
Hi David,
I'm re-submitting the patch series to add the socfpga glue layer for the
stmmac ethernet driver. My original patch did not build for kernel module,
and I apologize for not testing against that.
This patch is also better aligned with the other
On Thursday 27 March 2014 09:13 AM, Jingoo Han wrote:
On Wednesday, March 26, 2014 10:58 PM, Kishon Vijay Abraham I wrote:
Added support for pcie controller in dra7xx. This driver re-uses
the designware core code that is already present in kernel.
Signed-off-by: Kishon Vijay Abraham I
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