On 04/05/2014 02:23 AM, Soren Brinkmann wrote:
Add binding documentation for the Cadence UART.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Acked-by: Rob Herring r...@kernel.org
Tested-by: Michal Simek
On 04/05/2014 02:23 AM, Soren Brinkmann wrote:
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Acked-by: Peter Crosthwaite
Acked-by : Patrice Chotard patrice.chot...@st.com
Thanks
On 04/22/2014 08:40 PM, Geert Uytterhoeven wrote:
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: Benoit Cousson bcous...@baylibre.com
Cc: Srinivas Kandagatla srinivas.kandaga...@st.com
Cc: linux-o...@vger.kernel.org
Cc:
On Wed, Apr 16, 2014 at 3:05 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
Initial support for power domains for ux500. To enable this feature we
require to use DT, thus we need to add bindings for the ux500 specific
parts as well.
The implementation of the ux500 power domains is based upon
On 04/22/2014 05:03 PM, Aaro Koskinen wrote:
Hi,
On Tue, Apr 22, 2014 at 08:21:35AM +0200, Robert Baldyga wrote:
On 04/19/2014 12:52 PM, Aaro Koskinen wrote:
On Mon, Apr 14, 2014 at 01:46:16PM +0200, Robert Baldyga wrote:
dev_info(pdev-dev,
- OMAP USB OTG controller rev %d.%d
On Wed, Apr 23, 2014 at 10:26:20AM +0900, YoungJun Cho wrote:
Hi Andrzej
Thank you for comment.
On 04/22/2014 11:02 PM, Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings
On 04/23/2014 05:45 AM, YoungJun Cho wrote:
Hi again Andrzej,
On 04/23/2014 10:01 AM, YoungJun Cho wrote:
Hi Andrzej
Thank you for comments.
On 04/22/2014 09:15 PM, Andrzej Hajda wrote:
Hi YoungJun,
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
Some phy control registers are not kept
Hi Alan,
On Tue, Apr 22, 2014 at 11:28 PM, Alan Stern st...@rowland.harvard.edu wrote:
Thanks for reviewing this. Please find my comments inline below.
On Thu, 10 Apr 2014, Vivek Gautam wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for older
Hi,
On Tue, Apr 22, 2014 at 11:29 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Tue, 22 Apr 2014, Vivek Gautam wrote:
On Thu, Apr 10, 2014 at 6:54 PM, Vivek Gautam gautam.vi...@samsung.com
wrote:
Add support to consume phy provided by Generic phy framework.
Keeping the support for
Hi Felipe,
On 20/04/2014 05:20, Felipe Balbi wrote:
On Fri, Apr 18, 2014 at 12:22:37PM +0200, Gregory CLEMENT wrote:
For the armada 38x SoCs which come with an xhci controller, specific
initialization must be done during probe, especially in relation with
the MBus windows initialization.
Hi Srini,
On Tue, 2014-04-22 at 17:05 +0100, Srinivas Kandagatla wrote:
Hi Ivan,
On 22/04/14 10:20, Ivan T. Ivanov wrote:
From: Ivan T. Ivanoviiva...@mm-sol.com
Allows MSM OTG controller to be specified via device tree.
Signed-off-by: Ivan T. Ivanoviiva...@mm-sol.com
---
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
The offset of register DSIM_PLLTMR_REG in Exynos5420 is different
from the one in Exynos4 SoC.
In case of Exynos5420 SoC, there is no frequency band bit in DSIM_PLLCTRL_REG,
and it uses DSIM_PHYCTRL_REG and DSIM_PHYTIMING*_REG instead.
So this
On Friday 14 March 2014 02:50 PM, Rajendra Nayak wrote:
DRA752 device is wrongly documented as DRA742 device. Fix the typo.
Thanks to Nishanth for pointing out that the device part number is infact
DRA742. The compatible sting infact seems to have a typo. I'll fix
that up a post a v2 of this
Jisheng,
On Wed, Apr 23, 2014 at 10:45:39AM +0800, Jisheng Zhang wrote:
On Tue, 22 Apr 2014 08:38:24 -0700
Antoine Ténart antoine.ten...@free-electrons.com wrote:
The BG2 has an AHCI SATA controller. Add the corresponding node
in its device tree.
The AHCI IP of BG2 is different with
Sebastian,
On Tue, Apr 22, 2014 at 07:35:27PM +0200, Sebastian Hesselbarth wrote:
On 04/22/2014 10:27 AM, Antoine Ténart wrote:
[…]
+ sdhci0: sdhci@ab {
+ compatible = mrvl,pxav3-mmc;
+ reg = 0xab 0x200;
+ clocks =
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by Sachin Kamat)
Changelog v3:
- Removes optional delay, size properties
DRA72x devices are single core Cortex A15 devices belonging to the
DRA7 family (Similar to the DRA74x devices which are dual core Cortex
A15 based)
The patches (based off 3.15-rc2) add minimal DT/kernel modifications to add
boot support for DRA72x devices reusing all the kernel data for DRA74x
Use the corresponding compatibles to identify the devices.
Signed-off-by: Rajendra Nayak rna...@ti.com
---
arch/arm/mach-omap2/soc.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8..b8a4834 100644
---
The only difference from the dra74x devices is the missing .smp entry.
While at it, also fix the use of __initdata (across the file) and replace them
with __initconst as reported by checkpatch
ERROR: Use of const init definition must use __initconst
+static const char *dra72x_boards_compat[]
DRA72x is a single core cortex A15 device with most infrastructure IPs otherwise
same as whats on the DRA74x devices.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc:
ti,dra752 is neither documented nor correct, since the device is actually a
dra742 device as rightly documented in dt bindings.
Signed-off-by: Rajendra Nayak rna...@ti.com
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/dra7-evm.dts |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Create an explicit of_match_table entry for MAX98095 codec. Also
add a binding Documentation for this compatible string.
Signed-off-by: Tushar Behera tushar.beh...@linaro.org
---
.../devicetree/bindings/sound/max98095.txt | 16
sound/soc/codecs/max98095.c
On Tue, Apr 22, 2014 at 02:17:30PM +0200, Hans de Goede wrote:
Hi,
On 04/22/2014 02:07 PM, Emilio López wrote:
Hi Hans,
El 22/04/14 08:01, Hans de Goede escribió:
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzendörfer and I have been
working on.
The first 2 patches
On Tue, Apr 22, 2014 at 01:01:30PM +0200, Hans de Goede wrote:
Add clk-nodes for the mmc clocks.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 32
1 file changed, 32 insertions(+)
diff --git
On Tue, Apr 22, 2014 at 01:01:27PM +0200, Hans de Goede wrote:
From: David Lanzendörfer david.lanzendoer...@o2s.ch
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc
controllers found on A13 SoCs.
Signed-off-by: David Lanzendörfer david.lanzendoer...@o2s.ch
On Wednesday 23 April 2014 14:32:54 Rajendra Nayak wrote:
#ifdef CONFIG_SOC_DRA7XX
-static const char *dra7xx_boards_compat[] __initdata = {
+static const char *dra74x_boards_compat[] __initconst = {
+ ti,dra74x,
ti,dra7xx,
ti,dra7,
NULL,
};
Hi Hans,
On Tue, Apr 22, 2014 at 01:01:20PM +0200, Hans de Goede wrote:
Hi All,
Here is v8 of the sunxi-mmc patch-set David Lanzendörfer and I have been
working on.
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
On Tue, Apr 22, 2014 at 01:01:34PM +0200, Hans de Goede wrote:
Tested on a Mele A1000G Quad.
Signed-off-by: Hans de Goede hdego...@redhat.com
This patch can be merged with the previous one.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
On Tue, Apr 22, 2014 at 01:01:31PM +0200, Hans de Goede wrote:
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 52
Hi,
On 04/23/2014 11:48 AM, Maxime Ripard wrote:
On Tue, Apr 22, 2014 at 01:01:27PM +0200, Hans de Goede wrote:
From: David Lanzendörfer david.lanzendoer...@o2s.ch
Add nodes for the 3 mmc controllers found on A10s SoCs and for the 2 mmc
controllers found on A13 SoCs.
Signed-off-by: David
Hi,
On Tuesday 22 April 2014 01:43 AM, Sergei Shtylyov wrote:
Hello.
On 04/14/2014 09:53 AM, Kishon Vijay Abraham I wrote:
This PHY, though formally being a part of Renesas USBHS controller, contains
the
UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls
them
Hi,
On 04/23/2014 11:50 AM, Maxime Ripard wrote:
On Tue, Apr 22, 2014 at 01:01:31PM +0200, Hans de Goede wrote:
Add nodes for the 4 mmc controllers found on A31 SoCs to
arch/arm/boot/dts/sun6i-a31.dtsi.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi
Hi YoungJun,
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds MIPI-DSI command mode based S6E3FA0 AMOLED LCD Panel driver.
Changelog v2:
- Declares delay, size properties in probe routine instead of DT
Changelog v3:
- Moves CPU timings relevant properties from FIMD DT
-Original Message-
From: Will Deacon [mailto:will.dea...@arm.com]
Sent: 2014年4月22日 18:37
To: Neil Zhang
Cc: li...@arm.linux.org.uk; linux-arm-ker...@lists.infradead.org;
linux-ker...@vger.kernel.org; Sudeep Holla; devicetree@vger.kernel.org
Subject: Re: [PATCH v4] ARM: perf:
Hi,
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index 889005f..230c747 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -77,4 +77,7 @@ config OF_RESERVED_MEM
help
Helpers to allow for reservation of memory regions
+config
On Wed, Apr 23, 2014 at 02:43:58PM +0530, Tushar Behera wrote:
Create an explicit of_match_table entry for MAX98095 codec. Also
add a binding Documentation for this compatible string.
Applied, thanks.
signature.asc
Description: Digital signature
On Tue, Apr 22, 2014 at 02:35:15PM +0100, Grant Likely wrote:
On Fri, 18 Apr 2014 13:59:24 +0100, Leif Lindholm leif.lindh...@linaro.org
wrote:
Hi Geert,
On Fri, Apr 18, 2014 at 10:04:15AM +0200, Geert Uytterhoeven wrote:
On Thu, Apr 17, 2014 at 7:42 PM, Leif Lindholm
On 23/04/14 00:12, Marek Belisko wrote:
static int td028ttec1_panel_probe(struct spi_device *spi)
{
struct panel_drv_data *ddata;
@@ -418,6 +436,10 @@ static int td028ttec1_panel_probe(struct spi_device *spi)
r = td028ttec1_panel_probe_pdata(spi);
if (r)
From: Josh Cartwright jo...@codeaurora.org
The Qualcomm 8941 and 8841 PMICs are components used with the Snapdragon
800 series SoC family. This driver exists largely as a glue mfd component,
it exists to be an owner of an SPMI regmap for children devices
described in device tree.
(0) This patch set depends on the patch:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053308.html
(1) This patch set tries to add the DDR quad read support for the SPI
NOR framework, and it also adds the DDR quad read support for FREESCALE
quadspi controller
The patch updates the document by adding more information to describe the
DT proporties used by the Freescale Quadspi driver and the childs nodes.
For the child node for SPI NOR flash, we add the required property
(spi-max-frequency), and refer to spi-nor-flash.txt for the optional
properties.
For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
The dummy cycles is actually 8 for SPI fast/dual/quad read.
This patch makes preparations for the DDR quad read, it fixes the wrong dummy
value for both the spi-nor.c and m25p80.c.
Signed-off-by: Huang Shijie
This patch adds the DDR quad read support by the following:
[1] add SPI_NOR_DDR_QUAD read mode.
[2] add DDR Quad read opcodes:
SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for
Check the spi-nor,ddr-quad-read-dummy DT property to get the
dummy cycles for DDR quad read.
Signed-off-by: Huang Shijie b32...@freescale.com
---
drivers/mtd/spi-nor/fsl-quadspi.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c
Hi Mark,
On Wed, Apr 23, 2014 at 12:45 PM, Mark Rutland mark.rutl...@arm.com wrote:
Does anyone have a LongTrail DT to hand, and if so does the root have a
compatible string? From grepping through the kernel I could only find a
model string (IBM,LongTrail).
It's compatible with prep:
Add the DDR quad read support for the fsl-quadspi driver.
(1) Test this patch with imx6sx-sdb board (Spansion s25fl128s)
The clock rate is 66MHz.
(2) The information of NOR flash:
---
root@imx6qdlsolo:~# mtdinfo /dev/mtd0
mtd0
We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.
This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().
Signed-off-by: Huang Shijie b32...@freescale.com
---
On Wednesday 23 April 2014 03:21 PM, Arnd Bergmann wrote:
On Wednesday 23 April 2014 14:32:54 Rajendra Nayak wrote:
#ifdef CONFIG_SOC_DRA7XX
-static const char *dra7xx_boards_compat[] __initdata = {
+static const char *dra74x_boards_compat[] __initconst = {
+ ti,dra74x,
We need a DT property to store the dummy cycles for DDR Quad read.
This is a common feature for the SPI NOR flash, such as Spansion and Micron
chips.
Add this file to describe this specific SPI NOR flash features which will
be referred by the SPI NOR flash drivers.
Signed-off-by: Huang Shijie
Hi Andrzej,
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog v2:
- Adds unit address (commented by
The tps65090 regulator allows you to specify how long you want it to
wait before detecting an overcurrent condition. Allow specifying that
through the device tree (or through platform data).
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
On Tue, 22 Apr 2014 20:20:44 -0700, Greg Kroah-Hartman
gre...@linuxfoundation.org wrote:
On Tue, Apr 22, 2014 at 06:25:25PM -0700, Frank Rowand wrote:
Create some infrastructure to aid trouble shooting device tree related
boot issues.
Add a %driver_name file to each device tree node
Hisilicon Soc hip04 has four gpio controllers, each one has 32
gpios and can be configured to be an interrupt controller.
The gpio controllers are compatible with the snps,dw-apb-gpio
driver. This patch add the corresponding device tree nodes.
Signed-off-by: Zhou Wang wangzh...@hisilicon.com
---
On Tue, 22 Apr 2014 20:40:25 +0200, Geert Uytterhoeven
geert+rene...@glider.be wrote:
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Thanks Geert,
Applied all, but squashed into a single patch. I'll send it up to Linus
as a fix for 3.15
g.
---
drivers/of/irq.c |2 +-
1
This adds ability for the arc_emac to really handle its supplying clock.
To get the needed clock-frequency either a real clock or the previous
clock-frequency property must be provided.
Signed-off-by: Heiko Stuebner he...@sntech.de
---
Documentation/devicetree/bindings/net/arc_emac.txt | 12
From: Ivan T. Ivanov iiva...@mm-sol.com
Document device tree binding information as required by
the Qualcomm USB controller.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
---
Documentation/devicetree/bindings/usb/ci-hdrc-qcom.txt | 17 +
1 file changed, 17 insertions(+)
On Tue, 22 Apr 2014, Doug Anderson wrote:
This series adds the most critical cros_ec changes for newer boards
using cros_ec. Specifically:
* Fixes timing/locking issues with the previously upstreamed (but
never used upstream) cros_ec_spi driver.
* Updates the cros_ec header file to the
On Tue, 22 Apr 2014, Doug Anderson wrote:
On ARM Chromebooks we have a few devices that are accessed by both the
AP (the main Application Processor) and the EC (the Embedded
Controller). These are:
* The battery (sbs-battery).
* The power management unit tps65090.
On the original Samsung
On Thursday 17 April 2014, Maxime Ripard wrote:
The DT are supposed to be ordered by physical address. Move the NMI node where
it belongs.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked-by: Arnd Bergmann a...@arndb.de
--
To unsubscribe from this list: send the line
On Thursday 17 April 2014, Maxime Ripard wrote:
Since we start to have a lot of clocks to protect, some of them in a few
boards
only, it becomes difficult to handle the clock protection without having to
add
per machine exceptions.
Move these where they belong, in the machine definition
On Thursday 13 March 2014, Maxime Ripard wrote:
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for the
controller and the devices supported that can use DMA.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked-by: Arnd Bergmann a...@arndb.de
But why
On 04/23/2014 01:34 PM, Laurent Pinchart wrote:
Hi Andrzej,
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources, display timings and cpu timings.
Changelog
On Thursday 17 April 2014, Maxime Ripard wrote:
This will allow to add per-SoC hooks more easily.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/mach-sunxi/Makefile | 6 +-
arch/arm/mach-sunxi/restart.c | 104 +++
Hi Andrzej,
On Wednesday 23 April 2014 14:48:31 Andrzej Hajda wrote:
On 04/23/2014 01:34 PM, Laurent Pinchart wrote:
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes
On 18/04/14 02:32, Kuninori Morimoto wrote:
Hi Ben
Thank you for your patch
Add support for R8A7790 with new device tree code.
Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
---
(snip)
static const struct of_device_id sh_dmae_of_match[] = {
- {.compatible =
On Wed, 23 Apr 2014 11:45:28 +0100, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Apr 22, 2014 at 02:35:15PM +0100, Grant Likely wrote:
On Fri, 18 Apr 2014 13:59:24 +0100, Leif Lindholm
leif.lindh...@linaro.org wrote:
Hi Geert,
On Fri, Apr 18, 2014 at 10:04:15AM +0200, Geert
On Tue, 22 Apr 2014 15:05:26 +0100, Leif Lindholm leif.lindh...@linaro.org
wrote:
On Tue, Apr 22, 2014 at 02:08:29PM +0100, Grant Likely wrote:
I would prefer to see a WARN_ON(!IS_ENABLED(CONFIG_PPC32)); added here.
I completely agree.
OK. So do we keep this around on unaffected
On Wed, Apr 23, 2014 at 02:35:03PM +0200, Arnd Bergmann wrote:
On Thursday 13 March 2014, Maxime Ripard wrote:
Now that we have a DMA driver, we can add the DMA bindings in the DTSI for
the
controller and the devices supported that can use DMA.
Signed-off-by: Maxime Ripard
On Wed, Apr 23, 2014 at 02:39:26PM +0200, Arnd Bergmann wrote:
On Thursday 17 April 2014, Maxime Ripard wrote:
The DT are supposed to be ordered by physical address. Move the NMI node
where
it belongs.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked-by: Arnd
On Tue, 22 Apr 2014 15:05:26 +0100, Leif Lindholm leif.lindh...@linaro.org
wrote:
On Tue, Apr 22, 2014 at 02:08:29PM +0100, Grant Likely wrote:
I would prefer to see a WARN_ON(!IS_ENABLED(CONFIG_PPC32)); added here.
I completely agree.
OK. So do we keep this around on unaffected
On Wed, Apr 23, 2014 at 02:39:02PM +0200, Arnd Bergmann wrote:
On Thursday 17 April 2014, Maxime Ripard wrote:
Since we start to have a lot of clocks to protect, some of them in a few
boards
only, it becomes difficult to handle the clock protection without having to
add
per machine
Hi,
On Tue, 2014-04-22 at 17:31 -0700, Courtney Cavin wrote:
From: Josh Cartwright jo...@codeaurora.org
The Qualcomm 8941 and 8841 PMICs are components used with the Snapdragon
800 series SoC family. This driver exists largely as a glue mfd component,
it exists to be an owner of an SPMI
On Tue, Apr 22, 2014 at 3:35 AM, Haojian Zhuang
haojian.zhu...@linaro.org wrote:
If gpio base number isn't specified, the gpio base will be find from
the end of gpio number. In order to keep with schematics, use alias
to get the ID of gpio chip.
Signed-off-by: Haojian Zhuang
On Mon, Mar 3, 2014 at 11:27 AM, th...@altera.com wrote:
From: Tien Hock Loh th...@altera.com
Add driver support for Altera GPIO soft IP, including interrupts and I/O.
Tested on Altera CV SoC board using dipsw and LED using LED framework.
Signed-off-by: Tien Hock Loh th...@altera.com
Some
On Wednesday 23 April 2014 15:17:20 Maxime Ripard wrote:
+#include linux/clk.h
#include linux/init.h
#include linux/of_platform.h
@@ -19,9 +20,17 @@
static void __init sun4i_dt_init(void)
{
+ struct clk *clk;
+
sunxi_setup_restart();
On 04/23/2014 02:55 PM, Laurent Pinchart wrote:
Hi Andrzej,
On Wednesday 23 April 2014 14:48:31 Andrzej Hajda wrote:
On 04/23/2014 01:34 PM, Laurent Pinchart wrote:
On Wednesday 23 April 2014 11:02:21 Andrzej Hajda wrote:
On 04/21/2014 02:28 PM, YoungJun Cho wrote:
This patch adds DT
On Wednesday 23 April 2014 15:28:29 Maxime Ripard wrote:
On Wed, Apr 23, 2014 at 02:33:50PM +0200, Arnd Bergmann wrote:
On Thursday 17 April 2014, Maxime Ripard wrote:
This will allow to add per-SoC hooks more easily.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
On Wed, Apr 23, 2014 at 02:33:50PM +0200, Arnd Bergmann wrote:
On Thursday 17 April 2014, Maxime Ripard wrote:
This will allow to add per-SoC hooks more easily.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/mach-sunxi/Makefile | 6 +-
On Wednesday 09 April 2014, Jonas Jensen wrote:
Add SD/MMC driver for MOXA ART SoCs.
The MOXA ART MMC controller is likely a faraday ftsdc010,
a controller with support in U-Boot:
http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/mmc/ftsdc010_mci.c
Signed-off-by: Jonas Jensen
On 04/23/2014 03:18 AM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
Add a wrapper function to retrieve the FDT size from the FDT header. This
is primarily to avoid libfdt include paths for the whole kernel.
Signed-off-by: Rob Herring r...@kernel.org
---
v2: new patch
On Tue, Apr 22, 2014 at 3:38 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Patch applied, but I edited the subject to
Register the controller for device tree based lookup of DMA channels
(non-fatal for backwards compatibility with older device trees) and
provide the '#dma-cells' property in the shared mpc5121.dtsi file
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
---
arch/powerpc/boot/dts/mpc5121.dtsi |
On 04/23/2014 03:18 AM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
Both powerpc and microblaze have the same FDT blob in debugfs feature.
Move this to common location and remove the powerpc and microblaze
implementations. This feature could become more useful when FDT
overlay
2013/7/14 Gerhard Sittig g...@denx.de:
this series
- introduces slave s/g support (that's support for DMA transfers which
involve peripherals in contrast to mem-to-mem transfers)
- adds device tree based lookup support for DMA channels
- combines floating patches and related feedback which
Introduce a device tree binding document for the MPC512x DMA controller
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
---
.../devicetree/bindings/dma/mpc512x-dma.txt| 40 ++
1 file changed, 40 insertions(+)
create mode 100644
MPC512x and MPC8308 have similar DMA controllers, but are independent SoCs.
DMA controller driver should have separate 'compatible' values for these SoCs.
Signed-off-by: Alexander Popov a13xp0p0...@gmail.com
---
arch/powerpc/boot/dts/mpc8308_p1m.dts | 2 +-
arch/powerpc/boot/dts/mpc8308rdb.dts
This patch adds a new common OF dma xlate callback function which will match a
channel by it's id. The binding expects one integer argument which it will use
to
lookup the channel by the id.
Unlike of_dma_simple_xlate this function is able to handle a system with
multiple DMA controllers. When
On Tue, Apr 22, 2014 at 5:18 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
This patch has a dependency on the first patch of this serie, since it
uses a binding that was documented there.
Maybe you'll want to wait for the ACK from the DT maintainers to merge
this one.
Yeah I
On 04/23/2014 03:18 AM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
With libfdt support, we can take advantage of helper accessors in libfdt
for accessing the FDT header data. This makes the code more readable and
makes the FDT blob structure more opaque to the kernel. This also
On Tue, Apr 22, 2014 at 4:20 PM, Arnd Bergmann a...@arndb.de wrote:
Patch applied, and g we need to get rid of these static #gpios defines
in the long run.
Yes, that would be nice. I guess the gpio-descriptor framework should
have solved this, but we can't move everything over to that
Document the newly added berlin clock driver
Signed-off-by: Alexandre Belloni alexandre.bell...@free-electrons.com
---
Cc: devicetree@vger.kernel.org
Documentation/devicetree/bindings/clock/berlin-clock.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
On Tue, Apr 15, 2014 at 5:10 AM, Andy Gross agr...@codeaurora.org wrote:
Add missing PINCTRL selection. This enables selection of pinctrollers for
Qualcomm processors.
Signed-off-by: Andy Gross agr...@codeaurora.org
Acked-by: Linus Walleij linus.wall...@linaro.org
David are you picking
On Tue, Apr 15, 2014 at 5:10 AM, Andy Gross agr...@codeaurora.org wrote:
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.
Signed-off-by: Andy Gross agr...@codeaurora.org
Patch applied with Björns requested change and Review tag.
Yours,
On Wed, Apr 23, 2014 at 8:48 AM, Michal Simek mon...@monstr.eu wrote:
On 04/23/2014 03:18 AM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
With libfdt support, we can take advantage of helper accessors in libfdt
for accessing the FDT header data. This makes the code more readable and
On Tue, Apr 22, 2014 at 5:56 PM, Antoine Ténart
antoine.ten...@free-electrons.com wrote:
On Tue, Apr 22, 2014 at 02:52:10PM +0200, Linus Walleij wrote:
On Fri, Apr 11, 2014 at 3:35 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
On 04/11/2014 02:37 PM, Antoine Ténart wrote:
On 23/04/2014 15:48, Linus Walleij wrote:
On Tue, Apr 22, 2014 at 3:38 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
On 04/19/2014 12:33 AM, Scott Wood wrote:
On Fri, 2014-04-18 at 18:11 +0300, Diana Craciun wrote:
From: Diana Craciun diana.crac...@freescale.com
The CoreNet coherency fabric is a fabric-oriented, conectivity
infrastructure that enables the implementation of coherent, multicore
systems. The
On 04/23/2014 04:05 PM, Rob Herring wrote:
On Wed, Apr 23, 2014 at 8:48 AM, Michal Simek mon...@monstr.eu wrote:
On 04/23/2014 03:18 AM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
With libfdt support, we can take advantage of helper accessors in libfdt
for accessing the FDT header
Alan,
Sorry, I had to cut-n-paste your comment as I lost your email from my inbox.
-Original Message-
From: Karicheri, Muralidharan
Sent: Friday, April 11, 2014 3:18 PM
To: devicetree@vger.kernel.org; linux-...@vger.kernel.org;
linux-ker...@vger.kernel.org;
linux-ser...@vger.kernel.org
On Apr 23, 2014, at 9:03 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Tue, Apr 15, 2014 at 5:10 AM, Andy Gross agr...@codeaurora.org wrote:
Add missing PINCTRL selection. This enables selection of pinctrollers for
Qualcomm processors.
Signed-off-by: Andy Gross
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