On 05/29/2014 03:19 PM, Mark Rutland wrote:
On Thu, May 29, 2014 at 10:43:05AM +0100, Michal Simek wrote:
Hi Mark,
+static struct of_device_id cdns_wdt_of_match[] = {
+ { .compatible = xlnx,zynq-wdt-r1p2, },
+ { .compatible = cdns,wdt-r1p2, },
If these can currently be handled
On Thu, Apr 24, 2014 at 11:30:00AM -0400, Santosh Shilimkar wrote:
Here is an updated v3 of the series. Series introduces support for setting up
dma parameters based on device tree properties like 'dma-ranges' and
'dma-coherent' and also update to ARM 32 bit port. Earlier version of the
series
On Sun, Jun 01, 2014 at 11:23:48AM +0200, Hans de Goede wrote:
Hi,
Neither seems to actually ever have been used with
more than one slot. I doubt anyone building an exynos-based system
will ever do a multi-slot solution, and it seems that the at91 driver
doesn't actually handle more than
Hi Bjorn,
Thanks for the patches.
snip
Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p
patches for mainline.
It could be argued that smd is a bus and should go in drivers/bus, but
for the rest I fear that we just created drivers/soc/qcom as another
dumping ground for
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
wrote:
The following existing MMC host controller bindings use slot subnodes:
Hi,
On 06/02/2014 10:29 AM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
wrote:
The following existing MMC host controller bindings
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
wrote:
The following existing MMC host controller bindings use
On 06/02/2014 05:38 PM, Jaehoon Chung wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
wrote:
The
On 2 June 2014 10:38, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014 at 12:03 PM, Hans de Goede hdego...@redhat.com
On 2 June 2014 10:46, Jaehoon Chung jh80.ch...@samsung.com wrote:
On 06/02/2014 05:38 PM, Jaehoon Chung wrote:
On 06/02/2014 05:29 PM, Ulf Hansson wrote:
On 1 June 2014 11:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 05/31/2014 10:13 PM, Olof Johansson wrote:
On Sat, May 31, 2014
This series adds the SMP support for Marvell Berlin BG2 and BG2Q.
This implementation takes advantage of the reset exception register and
the software reset address register to make the CPUs execute the Berlin
secondary startup when being being reseted. This has the advantage of
not using the pen
The SMP support for Marvell Berlin SoCs introduce a new enable-method.
Document it.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
Adds SMP support for Berlin SoCs. Secondary CPUs are reseted, then
execute the instruction we put in the reset exception register, setting
the pc at the address contained in the software reset address register,
which is the physical address of the Berlin secondary startup.
This implementation
Add required nodes and properties into the Berlin BG2 device tree to
take advantage of the newly introduced SMP support. Add the scu and
cpu-ctrl nodes along with the CPUs enable-method property.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2.dtsi |
Document the CPU control compatible, needed for the SMP support on
Marvell Berlin SoCs.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/arm/marvell,berlin.txt | 16
1 file changed, 16 insertions(+)
diff --git
Add required nodes and properties into the Berlin BG2Q device tree to
take advantage of the newly introduced SMP support. Add the scu and
cpu-ctrl nodes along with the CPUs enable-method property.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
arch/arm/boot/dts/berlin2q.dtsi
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index d3c5f14dc142..e3733692f67a 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -4,6 +4,7 @@ config ARCH_BERLIN
Mon, 2 Jun 2014 09:56:51 +0100 от Mark Rutland mark.rutl...@arm.com:
On Sun, Jun 01, 2014 at 10:55:22AM +0100, Alexander Shiyan wrote:
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock subsystem.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
On Mon, Jun 02, 2014 at 10:29:13AM +0100, Russell King - ARM Linux wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index d3c5f14dc142..e3733692f67a 100644
--- a/arch/arm/mach-berlin/Kconfig
+++
On Mon, Jun 02, 2014 at 11:21:01AM +0200, Antoine Ténart wrote:
This series adds the SMP support for Marvell Berlin BG2 and BG2Q.
This implementation takes advantage of the reset exception register and
the software reset address register to make the CPUs execute the Berlin
secondary startup
Hi Andrew,
On Mon, Jun 02, 2014 at 11:35:32AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:01AM +0200, Antoine Ténart wrote:
This series adds the SMP support for Marvell Berlin BG2 and BG2Q.
This implementation takes advantage of the reset exception register and
the software
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline void berlin_reset_cpu(unsigned int cpu)
+{
+ u32 val;
+
+ val = readl(cpu_ctrl + CPU_RESET);
+ val |= BIT(cpu_logical_map(cpu));
+ writel(val, cpu_ctrl + CPU_RESET);
+}
Hi Antoine
Is this
Hi Andrew,
On Mon, Jun 02, 2014 at 11:47:15AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline void berlin_reset_cpu(unsigned int cpu)
+{
+ u32 val;
+
+ val = readl(cpu_ctrl + CPU_RESET);
+ val |=
On Mon, Jun 02, 2014 at 11:15:24AM +0300, Stanimir Varbanov wrote:
Lately I've been working on rpm, rpm-smd, smem, smd, smsm, smp2p
patches for mainline.
It could be argued that smd is a bus and should go in drivers/bus, but
for the rest I fear that we just created drivers/soc/qcom as
On Mon, Jun 02, 2014 at 12:00:48PM +0200, Antoine Ténart wrote:
Hi Andrew,
On Mon, Jun 02, 2014 at 11:47:15AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline void berlin_reset_cpu(unsigned int cpu)
+{
+ u32 val;
+
+
On 01/06/14 14:38, Rickard Strandqvist wrote:
There is a risk that the variable will be used without being initialized.
This was largely found by using a static code analysis program called
cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
On Mon, Jun 02, 2014 at 12:03:32PM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 12:00:48PM +0200, Antoine Ténart wrote:
Hi Andrew,
On Mon, Jun 02, 2014 at 11:47:15AM +0200, Andrew Lunn wrote:
On Mon, Jun 02, 2014 at 11:21:02AM +0200, Antoine Ténart wrote:
+
+static inline
Hi Maxime,
On Thu, 22 May 2014, Maxime Coquelin wrote:
Initially it supports the stih416 and stih415 SoCs, and has
been tested on a stih416-b2020 board.
In next version, could you also add drivers/mmc/host/sdhci-st.c in
the ARM/STI ARCHITECTURE field of MAINTAINERS file?
Was out on hols
On Sat, May 31, 2014 at 11:13:05AM +0200, Hans de Goede wrote:
Hi,
On 05/28/2014 12:33 PM, Maxime Ripard wrote:
On Wed, May 28, 2014 at 11:51:52AM +0200, Hans de Goede wrote:
Hi,
On 05/28/2014 11:36 AM, Maxime Ripard wrote:
On Tue, May 27, 2014 at 04:18:29PM +0200, Linus Walleij wrote:
On 31/05/14 22:46, trem wrote:
Hi Jonathan,
On 30/05/14 18:29, Jonathan Cameron wrote:
On May 29, 2014 10:22:00 PM GMT+01:00, Philippe Reynestrem...@yahoo.fr wrote:
This driver add partial support of the
maxim 1027/1029/1031. Differential mode is not
supported.
It was tested on armadeus
On Fri, May 30, 2014 at 09:49:59PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 14:31:55 Rob Herring wrote:
On Fri, May 30, 2014 at 2:06 PM, Arnd Bergmann a...@arndb.de wrote:
On Friday 30 May 2014 08:16:05 Rob Herring wrote:
On Fri, May 23, 2014 at 3:33 PM, Thierry Reding
On Mon, Jun 02, 2014 at 10:32:48AM +0100, Alexander Shiyan wrote:
Mon, 2 Jun 2014 09:56:51 +0100 от Mark Rutland mark.rutl...@arm.com:
On Sun, Jun 01, 2014 at 10:55:22AM +0100, Alexander Shiyan wrote:
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock
On Mon, Jun 02, 2014 at 10:21:03AM +0100, Antoine Ténart wrote:
The SMP support for Marvell Berlin SoCs introduce a new enable-method.
Document it.
Signed-off-by: Antoine Ténart antoine.ten...@free-electrons.com
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1
On Fri, May 30, 2014 at 09:11:07PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:27:28 Dave Martin wrote:
On Fri, May 30, 2014 at 08:30:08AM +0100, Thierry Reding wrote:
On Thu, May 29, 2014 at 09:52:22AM -0600, Stephen Warren wrote:
On 05/23/2014 02:36 PM, Thierry Reding wrote:
Hi Lee,
Thanks for your feedback, all your other comments will be fixed in v2.
However see comments below for this patch
+ clk_prepare_enable(clk);
Move this down as far as it will go. When do you _need_ the clock
running by?
+ host-mmc-caps |= MMC_CAP_8_BIT_DATA |
From: Chew, Chiau Ee chiau.ee.c...@intel.com
SPI PXA2XX core layer depends on common clock framework to obtain
information on host supported clock rate. Thus, we setup and register
clock device for PCI mode host in SPI PXA2XX pci glue layer using
common clock APIs.
In addition, in order for PCI
From: Chew, Chiau Ee chiau.ee.c...@intel.com
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew,
From: Darren Hart dvh...@linux.intel.com
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
Signed-off-by: Darren Hart dvh...@linux.intel.com
Reviewed-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Cc: Mika Westerberg
On Fri, May 30, 2014 at 09:01:19PM +0200, Arnd Bergmann wrote:
On Friday 30 May 2014 12:22:32 Dave Martin wrote:
+
+Examples:
+=
+
+Single-master IOMMU:
+
+
+ iommu {
+ #address-cells = 0;
+ #size-cells = 0;
+ };
+
Mon, 2 Jun 2014 11:42:22 +0100 от Mark Rutland mark.rutl...@arm.com:
On Mon, Jun 02, 2014 at 10:32:48AM +0100, Alexander Shiyan wrote:
Mon, 2 Jun 2014 09:56:51 +0100 от Mark Rutland mark.rutl...@arm.com:
On Sun, Jun 01, 2014 at 10:55:22AM +0100, Alexander Shiyan wrote:
This patch adds DT
Hi Max,
here is the review:
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index c94db1c..f973632 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -663,6 +663,16 @@ config I2C_PXA_SLAVE
is necessary for systems where the PXA may be a
On Tue, Jun 03, 2014 at 03:46:19AM +0800, Chew Chiau Ee wrote:
From: Darren Hart dvh...@linux.intel.com
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
This needs to be patch 1 in the series not patch 2 since the change to
the
On Tue, Jun 03, 2014 at 03:46:18AM +0800, Chew Chiau Ee wrote:
---
drivers/spi/spi-pxa2xx-pci.c | 20
1 files changed, 20 insertions(+), 0 deletions(-)
+ clk = clk_register_fixed_rate(dev-dev, spi_pxa2xx_clk, NULL,
+
On 05/30/2014 01:15 PM, Heiko Stübner wrote:
Am Freitag, 30. Mai 2014, 21:54:13 schrieb Seungwon Jeon:
+ Dinh Nguyen dingu...@altera.com
+ Heiko Stuebner he...@sntech.de
On Wed, May 28, 2014, Jaehoon Chung wrote:
dw-mmc controller can support the multiple slot.
So each slot's property can
On Mon, Jun 02, 2014 at 07:25:16AM +0100, Michal Simek wrote:
On 05/29/2014 03:19 PM, Mark Rutland wrote:
On Thu, May 29, 2014 at 10:43:05AM +0100, Michal Simek wrote:
Hi Mark,
+static struct of_device_id cdns_wdt_of_match[] = {
+ { .compatible = xlnx,zynq-wdt-r1p2, },
+ {
On Monday 02 June 2014 02:37 AM, Shawn Guo wrote:
On Thu, Apr 24, 2014 at 11:30:00AM -0400, Santosh Shilimkar wrote:
Here is an updated v3 of the series. Series introduces support for setting up
dma parameters based on device tree properties like 'dma-ranges' and
'dma-coherent' and also update
On 06/02/2014 03:17 PM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 07:25:16AM +0100, Michal Simek wrote:
On 05/29/2014 03:19 PM, Mark Rutland wrote:
On Thu, May 29, 2014 at 10:43:05AM +0100, Michal Simek wrote:
Hi Mark,
+static struct of_device_id cdns_wdt_of_match[] = {
+ {
This patch series enables DMA support for QSPI on r8a7791/koelsch
reference. It's independent from the series ARM: shmobile: koelsch
legacy: Enable DMA for QSPI, but it depends on the SHDMA work for r8a7790
by Ben Dooks (cfr. [PATCH v2 0/9] Updates Renesas OF-DMA code).
Changes Compared to
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
Documentation/devicetree/bindings/dma/shdma.txt | 5 +++--
drivers/dma/sh/shdmac.c | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- New
Documentation/devicetree/bindings/dma/shdma.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/shdma.txt
b/Documentation/devicetree/bindings/dma/shdma.txt
index
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
arch/arm/boot/dts/r8a7791.dtsi | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
Add nodes for the SYS-DMA controllers, SYS-DMAC0 and SYS-DMAC1. These
both share the same device sources, so are wrapped in the shdma-mux
node to allow both to be used.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
Add channel resource identifiers for the SYS DMA controller.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
I don't like the CHCR_[RT]X_*BIT definitions
include/dt-bindings/dma/r8a7791-dma.h | 111
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
arch/arm/boot/dts/r8a7791-koelsch.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts
b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 05d44f9b202f..75c88dc88b9f
Add a DMA property to the QSPI node
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- QSPI needs to use 8-bit accesses for DMA, not 32-bit,
- Reorder: TX first, RX second.
arch/arm/boot/dts/r8a7791.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: devicetree@vger.kernel.org
---
The format of the DMA specifiers depends on the DT bindings for SHDMA,
which are still under development.
---
Documentation/devicetree/bindings/spi/spi-rspi.txt | 6
drivers/spi/spi-rspi.c
On 02/06/14 14:42, Geert Uytterhoeven wrote:
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- New
Documentation/devicetree/bindings/dma/shdma.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/shdma.txt
On 02/06/14 14:42, Geert Uytterhoeven wrote:
Add a DMA property to the QSPI node
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- QSPI needs to use 8-bit accesses for DMA, not 32-bit,
- Reorder: TX first, RX second.
arch/arm/boot/dts/r8a7791.dtsi | 3 +++
1 file
Initially it supports the stih416 and stih415 SoCs, and has
been tested on a stih416-b2020 board.
In next version, could you also add drivers/mmc/host/sdhci-st.c in
the ARM/STI ARCHITECTURE field of MAINTAINERS file?
Was out on hols last week. I have fixed it in v2.
This should be
On 02/06/14 14:42, Geert Uytterhoeven wrote:
Add channel resource identifiers for the SYS DMA controller.
Cfr. the r8a7790 version by Ben Dooks.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
---
v2:
- No changes
I don't like the CHCR_[RT]X_*BIT definitions
On 02/06/14 14:42, Geert Uytterhoeven wrote:
This patch series enables DMA support for QSPI on r8a7791/koelsch
reference. It's independent from the series ARM: shmobile: koelsch
legacy: Enable DMA for QSPI, but it depends on the SHDMA work for r8a7790
by Ben Dooks (cfr. [PATCH v2 0/9] Updates
Grygorii Strashko grygorii.stras...@ti.com writes:
Hi All,
On 05/28/2014 12:03 PM, Grant Likely wrote:
[...]
The bisected patch causes platform_get_irq() to always parse the
devicetree to obtain the irq instead of using a precalculated value in
the platform_device. There are two possible
On Mon, Jun 02, 2014 at 03:38:20PM +0200, Geert Uytterhoeven wrote:
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: devicetree@vger.kernel.org
---
The format of the DMA specifiers depends on the DT bindings for SHDMA,
which are still under development.
This looks fine to me,
Hi Mark,
On Mon, Jun 2, 2014 at 4:54 PM, Mark Brown broo...@kernel.org wrote:
On Mon, Jun 02, 2014 at 03:38:20PM +0200, Geert Uytterhoeven wrote:
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: devicetree@vger.kernel.org
---
The format of the DMA specifiers depends on the DT
On Sun, 1 Jun 2014 15:01:23 +0300, Ivaylo Dimitrov
ivo.g.dimitrov...@gmail.com wrote:
The current code unconditionally adds aliases without check if it already
exists, so it is not possible to alter an alias, from board DT file for
example. Fix that by replacing an alias if it already exists
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote:
On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote:
We would like to be able to describe PCIe ECAM resources as
IORESOURCE_MEM blocks while distinguish them from standard
memory resources. Add an IORESOURCE_BIT entry for
On Wed, 28 May 2014 10:39:02 -0700, Florian Fainelli f.faine...@gmail.com
wrote:
Add an early check for the node argument in __of_get_next_child and
of_get_next_available_child() to avoid dereferencing a NULL node pointer
a few lines after.
CC: Daniel Mack zon...@gmail.com
Signed-off-by:
On 6/2/14, 5:35, Mark Brown broo...@kernel.org wrote:
On Tue, Jun 03, 2014 at 03:46:19AM +0800, Chew Chiau Ee wrote:
From: Darren Hart dvh...@linux.intel.com
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
This needs to be
Hi Dmitry, sorry for the terribly late reply.
On Sun, May 18, 2014 at 01:40:09PM -0700, Dmitry Torokhov wrote:
Hi Guido,
On Wed, May 07, 2014 at 10:00:42AM -0300, Guido Martínez wrote:
Add DT support for the Analog ADP5589 matrix keypad decoding functions.
Signed-off-by: Guido Martínez
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote:
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote:
On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote:
We would like to be able to describe PCIe ECAM resources as
IORESOURCE_MEM blocks while
Arnd,
On Monday 02 June 2014 11:06 AM, Arnd Bergmann wrote:
On Monday 02 June 2014 09:24:50 Santosh Shilimkar wrote:
On Monday 02 June 2014 02:37 AM, Shawn Guo wrote:
On Thu, Apr 24, 2014 at 11:30:00AM -0400, Santosh Shilimkar wrote:
Here is an updated v3 of the series. Series introduces
On 06/02/2014 03:43 AM, Marcel Ziswiler wrote:
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller,
SPI bus and PWM LEDs generically accessible from user space and an
LM95245 temperature sensor chip. The
On 2.06.2014 17:59, Grant Likely wrote:
On Sun, 1 Jun 2014 15:01:23 +0300, Ivaylo Dimitrov
ivo.g.dimitrov...@gmail.com wrote:
The current code unconditionally adds aliases without check if it already
exists, so it is not possible to alter an alias, from board DT file for
example. Fix that
On 06/01/2014 05:37 PM, Marcel Ziswiler wrote:
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller, I2C
as well as SPI buses and PWM LEDs generically accessible from user
space and an LM95245 temperature
On Mon, 2 Jun 2014 10:40:30 -0500, Kumar Gala ga...@codeaurora.org wrote:
On Jun 2, 2014, at 10:09 AM, Grant Likely grant.lik...@linaro.org wrote:
On Sat, 31 May 2014 20:41:04 +0200, Arnd Bergmann a...@arndb.de wrote:
On Saturday 31 May 2014 01:36:40 Liviu Dudau wrote:
We would like to
On 06/02/2014 06:00 PM, Stephen Warren wrote:
BTW: How about TEGRA_EMC_SCALING_ENABLE
I thought a patch was sent to remove that. Perhaps the patch was only
sent to tegra_defconfig.
... MTD_M25P80 which depends on MTD_SPI_NOR
I've seen patches to fix that too.
Yes, you are right. I have
On 06/01/2014 05:37 PM, Marcel Ziswiler wrote:
This patch adds the device tree to support Toradex Apalis T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L
RAM, eMMC, an LM95245 temperature sensor chip,
On 06/01/2014 05:37 PM, Marcel Ziswiler wrote:
This patch adds the device tree to support Toradex Apalis T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L
RAM, eMMC, an LM95245 temperature sensor chip,
* Tony Lindgren t...@atomide.com [140528 11:11]:
* Lee Jones lee.jo...@linaro.org [140528 00:14]:
Thanks Tony, here's the pull-request:
The following changes since commit 455c6fdbd219161bd09b1165f11699d6d73de11c:
Linux 3.14 (2014-03-30 20:40:15 -0700)
are available in the git
On Mon, Jun 2, 2014 at 2:43 AM, Marcel Ziswiler mar...@ziswiler.com wrote:
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller,
SPI bus and PWM LEDs generically accessible from user space and an
LM95245
On Sat, May 10, 2014 at 04:20:14PM +0900, Pankaj Dubey wrote:
Let's handle i2c interrupt re-configuration in i2c driver. This will
help us in removing some soc specific checks from machine files.
Since only Exynos5250, and Exynos5420 need to do this, added syscon
based phandle to i2c device
Ok, there was already a patch posted by you for this[1], which had
quite a much discussion
on it.
Would you like to give some pointers based on that ?
One that Olof had suggested was to use gpio-reset driver which is yet
to make to mainline.
But i think with that too we need to take care of
On 06/02/2014 11:01 AM, Olof Johansson wrote:
On Mon, Jun 2, 2014 at 2:43 AM, Marcel Ziswiler mar...@ziswiler.com wrote:
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller,
SPI bus and PWM LEDs generically
On Sun, Jun 01, 2014 at 01:33:51PM +0200, Rickard Strandqvist wrote:
There is a risk for memory leak in when something unexpected happens
and the function returns.
I don't think there is a risk of memory leak, but wrong address access,
in this case.
This was largely found by using a static
On Mon, May 5, 2014 at 2:57 PM, Florian Fainelli f.faine...@gmail.com wrote:
2014-05-05 14:47 GMT-07:00 Iyappan Subramanian isubraman...@apm.com:
This patch adds documentation for APM X-Gene SoC ethernet DTS binding.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Ravi
On Monday 02 June 2014 11:54:36 Santosh Shilimkar wrote:
On Monday 02 June 2014 11:06 AM, Arnd Bergmann wrote:
On Monday 02 June 2014 09:24:50 Santosh Shilimkar wrote:
On Monday 02 June 2014 02:37 AM, Shawn Guo wrote:
On Thu, Apr 24, 2014 at 11:30:00AM -0400, Santosh Shilimkar wrote:
On Monday 02 June 2014 03:00 PM, Arnd Bergmann wrote:
On Monday 02 June 2014 11:54:36 Santosh Shilimkar wrote:
On Monday 02 June 2014 11:06 AM, Arnd Bergmann wrote:
On Monday 02 June 2014 09:24:50 Santosh Shilimkar wrote:
On Monday 02 June 2014 02:37 AM, Shawn Guo wrote:
On Thu, Apr 24, 2014
On Monday 02 June 2014 13:09:08 Kumar Gala wrote:
However, what do we do with the 2 cases that exist in upstream that
are using ranges for cfg space?
Ignore them in the core code? Make the specific host controller handle
them I would think.
I just meant, should we ‘break’ their DTs
On 05/31, Georgi Djakov wrote:
+
+static const struct qcom_reset_map gcc_apq8084_resets[] = {
+ [GCC_VENUS0_BCR] = { 0x1020 },
+ [GCC_VPU_BCR] = { 0x1400 },
+ [GCC_MDSS_BCR] = { 0x2300 },
+ [GCC_AVSYNC_BCR] = { 0x2400 },
+ [GCC_OXILI_BCR] = { 0x4020 },
+
Adding APM X-Gene SoC Ethernet driver.
v5: Address comments from v4 review
* Documentation: Added phy-handle, reg-names and changed mdio part
* dtb: Added reg-names supplemental property
* changed platform_get_resource to platform_get_resource_byname
* added separate tx/rx set_desc/get_desc
This patch adds bindings for APM X-Gene SoC ethernet driver.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Ravi Patel rapa...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
arch/arm64/boot/dts/apm-mustang.dts |4
arch/arm64/boot/dts/apm-storm.dtsi |
This patch adds documentation for APM X-Gene SoC ethernet DTS binding.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Ravi Patel rapa...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
.../devicetree/bindings/net/apm-xgene-enet.txt | 72
Hi
No, regardless if it is a program that cppcheck or myself with limited
experience of kernel programming is not so easy to figure out.
But then I know that there is nothing wrong in this case, and that is
the main thing :-)
Best regards
Rickard Strandqvist
2014-06-02 2:10 GMT+02:00 Olof
On 05/31, Georgi Djakov wrote:
Add the necessary DT node to probe the serial driver on
APQ8084 platforms.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Reviewed-by: Stephen Boyd sb...@codeaurora.org
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux
This patch adds a MAINTAINERS entry for APM X-Gene SoC
ethernet driver.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Ravi Patel rapa...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
MAINTAINERS |8
1 file changed, 8 insertions(+)
diff --git
On 05/31, Georgi Djakov wrote:
Add the compatible string for the APQ8084 global clock controller
to the clock binding documentation.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Reviewed-by: Stephen Boyd sb...@codeaurora.org
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora
On 05/31, Georgi Djakov wrote:
This patch adds the necessary node to probe the global clock
controller on APQ8084 platforms.
Signed-off-by: Georgi Djakov gdja...@mm-sol.com
Reviewed-by: Stephen Boyd sb...@codeaurora.org
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
On 02.06.14, 22:36, Stephen Boyd wrote:
On 05/31, Georgi Djakov wrote:
+
+static const struct qcom_reset_map gcc_apq8084_resets[] = {
+[GCC_VENUS0_BCR] = { 0x1020 },
+[GCC_VPU_BCR] = { 0x1400 },
+[GCC_MDSS_BCR] = { 0x2300 },
+[GCC_AVSYNC_BCR] = { 0x2400 },
+
Neither CMA nor noncoherent allocations support atomic allocations.
Add a dedicated atomic pool to support this.
Change-Id: I46c8fdffe5e0687403d42b37643137c8cf344259
Signed-off-by: Laura Abbott lau...@codeaurora.org
---
v2: Various bug fixes pointed out by David and Ritesh (CMA dependency,
On 06/02/2014 06:26 PM, Stephen Warren wrote:
+ toradex,colibri_t30
+ toradex,colibri_t30-eval-v3
Those don't seem to be related to Apalis support.
Yes, that's why I mentioned it in the commit message as follows:
While at it also add the device tree binding documentation for Apalis
T30
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