This patch add documentation for S2MPU02 PMIC device. S2MPU02 has a little
difference from S2MPS11/S2MPS14 PMIC and has LDO[1-28]/Buck[1-7].
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
Add details of following properties which are used on driver but
not documented on DT binding document.
- ams,enable-internal-int-pullup
- ams,enable-internal-i2c-pullup
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Reported-by: Lee Jones lee.jo...@linaro.org
---
On Friday 06 June 2014 08:58 PM, Lee Jones wrote:
Laxman,
This patch has already been applied, but ...
+ as3722-en_intern_int_pullup = of_property_read_bool(np,
+ ams,enable-internal-int-pullup);
+ as3722-en_intern_i2c_pullup =
The macro name for enable3 pin is named as AS3722_EXT_CONTROL_PIN_ENABLE2
which is conflict with the enable2 pin.
Correct this macro name to correctly reflect the enable pin i.e.
AS3722_EXT_CONTROL_PIN_ENABLE3.
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Reported-by: Dan Willemsen
From: Leif Lindholm leif.lindh...@linaro.org
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit bfaed5abad998bfc88a66e6e71c7b08dcf82f04e upstream.
The current .dts for ste-ccu8540 lacks a 'device_type = memory' for
its memory node, relying on an
From: Leif Lindholm leif.lindh...@linaro.org
3.12-stable review patch. If anyone has any objections, please let me know.
===
commit dfc44f8030653b345fc6fb337558c3a07536823f upstream.
A few platforms lack a 'device_type = memory' for their memory
nodes, relying on an old ppc quirk
On Sat, Jun 07, 2014 at 01:55:22AM +0100, Laura Abbott wrote:
On 6/5/2014 10:05 AM, Catalin Marinas wrote:
On Mon, Jun 02, 2014 at 09:03:52PM +0100, Laura Abbott wrote:
Neither CMA nor noncoherent allocations support atomic allocations.
Add a dedicated atomic pool to support this.
CMA
Peach pit board uses a Maxim 77802 Power Management IC to
drive regulators and its Real Time Clock. This patch adds
support for this chip.
These are the device nodes and pinctrl configuration that
is present on the Peach pit DeviceTree source file in the
the Chrome OS kernel 3.8 tree.
MAX77802 is a PMIC that contains 10 high efficiency Buck regulators,
32 Low-dropout (LDO) regulators, two 32kHz buffered clock outputs,
a Real-Time-Clock (RTC) and a I2C interface to program the individual
regulators, clocks and the RTC.
This series are based on drivers added by Simon Glass to
The MAX7802 PMIC has a Real-Time-Clock (RTC) with two alarms.
This patch adds support for the RTC and is based on a driver
added by Simon Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
drivers/mfd/max77802.c | 3 +
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application processors and peripherals, a 2-channel
32kHz clock outputs, a Real-Time-Clock (RTC) and a I2C interface
to program the individual regulators,
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
.../devicetree/bindings/clock/maxim,max77802.txt | 40
drivers/clk/Kconfig
On 06/09/2014 06:30 AM, Peter Chen wrote:
On Thu, Jun 05, 2014 at 05:48:37PM +0200, Antoine Ténart wrote:
This series adds the support for the Marvell Berlin USB controllers,
the USB PHYs and also adds a reset controller.
The reset controller is used by the USB PHY driver and shares the
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
MAX77802 is a PMIC that contains 10 high efficiency Buck regulators,
32 Low-dropout (LDO) regulators, two 32kHz buffered clock outputs,
a Real-Time-Clock (RTC) and a I2C interface to program the individual
regulators, clocks
This patch add documentation for S2MPU02 PMIC device. S2MPU02 has a little
difference from S2MPS11/S2MPS14 PMIC and has LDO[1-28]/Buck[1-7].
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application processors and peripherals, a 2-channel
32kHz clock outputs, a
The regulators would set different state/mode according to the kind of suspend
state. So regulation_constraints structure has already regulator suspend state
filed.
This patch parse regulator suspend state from devicetree file.
For example:
ldoX_reg: LDOx {
The regulation_constraints structure includes specific field to support
suspend state for global PMIC STANDBY/HIBERNATE mode. This patch add support
for parsing regulator_state for suspend state.
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
---
drivers/regulator/of_regulator.c | 61
This patch add regulator suspend state to constraint in dt file. The regulation_
constraints structure already has regulator suspend state field as following.
The regulator suspend state control the state of regulator according to
PM (Power Management) state.
- struct regulator_state state_disk
-
On Sat, Jun 07, 2014 at 03:22:13PM +0200, Arnd Bergmann wrote:
On Saturday 07 June 2014 00:45:45 Thierry Reding wrote:
This is somewhat off-topic, but given the various concepts discussed in
this thread I'm beginning to wonder how they will be implemented.
I think it's good you raised the
This patch adds documentation for Device-Tree bindings for the Security
System cryptographic accelerator driver.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
Documentation/devicetree/bindings/crypto/sunxi-ss.txt | 9 +
1 file changed, 9 insertions(+)
create mode 100644
Add support for the Security System included in Allwinner SoC A20.
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/sunxi-ss/Makefile | 16 ++
The Security System is a hardware cryptographic accelerator that support
AES/MD5/SHA1/DES/3DES/PRNG algorithms.
It could be found on many Allwinner SoC.
This patch enable the Security System on the Allwinner A20 SoC Device-tree.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
Add necessary changes for configuring and compiling the Security System driver.
Signed-off-by: LABBE Corentin clabbe.montj...@gmail.com
---
drivers/crypto/Kconfig | 76 +
drivers/crypto/Makefile | 1 +
2 files changed, 77 insertions(+)
diff
Display domain is removed due to instability issues. Explaining
the problem below:
exynos_init_late triggers the pm_genpd_poweroff_unused which
powers off the unused power domains. This call hits before
the trigger to deferred probes.
DRM DP Panel defers the probe due to supply get failure. By
Hello,
On Thursday 05 June 2014 01:54:47 Sergei Shtylyov wrote:
Hello.
On 06/04/2014 03:40 PM, Kishon Vijay Abraham I wrote:
This PHY, though formally being a part of Renesas USBHS controller,
contains the UGCTRL2 register that controls multiplexing of the USB
ports (Renesas calls them
Hi Sergei,
Thank you for the patch.
On Saturday 24 May 2014 02:06:03 Sergei Shtylyov wrote:
This PHY, though formally being a part of Renesas USBHS controller, contains
the UGCTRL2 register that controls multiplexing of the USB ports (Renesas
calls them channels) to the different USB
On Mon, Jun 09, 2014 at 12:22:41PM +0200, Krzysztof Kozlowski wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
+static const struct max77802_irq_data max77802_irqs[] = {
+ DECLARE_IRQ(MAX77802_PMICIRQ_PWRONF,PMIC_INT1, 1 0),
+
On Fri, Jun 6, 2014 at 5:28 PM, Lee Jones lee.jo...@linaro.org wrote:
+ as3722-en_intern_int_pullup = of_property_read_bool(np,
+ ams,enable-internal-int-pullup);
+ as3722-en_intern_i2c_pullup = of_property_read_bool(np,
+
Here is the third version of the crypto driver.
Changes since v2:
- reworked crypto_enqueue/dequeue_request mechanism. The queue
length has been changed to one to reflect the hardware
capabilities
- the workqueue has been deleted and replaced by new queue function
- few not functional
Here is Qualcomm crypto driver device tree binding documentation
to used as a reference example.
Signed-off-by: Stanimir Varbanov svarba...@mm-sol.com
---
.../devicetree/bindings/crypto/qcom-qce.txt| 25
1 files changed, 25 insertions(+), 0 deletions(-)
create
On Sunday 08 June 2014 10:13 PM, Fabio Estevam wrote:
On Thu, Jun 5, 2014 at 12:22 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Recently we introduced the generic device tree infrastructure for couple of
DMA
bus parameter, dma-ranges and dma-coherent. Update the documentation so
On 4 June 2014 17:55, Mark Brown broo...@kernel.org wrote:
On Tue, Jun 03, 2014 at 12:57:52PM +0200, Ulf Hansson wrote:
On 28 May 2014 13:03, Mark Brown broo...@kernel.org wrote:
No, runtime PM isn't really fine grained - I'm talking about things
like starting and stopping individual
On Mon, 2014-06-09 at 12:34 +0900, Jaehoon Chung wrote:
dw-mmc controller can support multiple slots.
But, there are no use-cases anywhere. So we don't need to support the
slot-node for dw-mmc controller.
And supports-highspeed property in dw-mmc is deprecated.
supports-highspeed property can
Hello,
This patch series adds support for Atmel HLCDC (High LCD Controller)
available on some Atmel SoCs (i.e. the sama5d3 family).
The HLCDC actually provides a Display Controller and a PWM device, hence I
decided to declare an MFD device that exposes 2 subdevices: a display
controller and a
The HLCDC IP available on some Atmel SoCs (i.e. at91sam9n12, at91sam9x5
family or sama5d3 family) exposes 2 subdevices:
- a display controller (controlled by a DRM driver)
- a PWM chip
Add support for the MFD device which will just retrieve HLCDC clocks and
create a regmap so that subdevices can
Add LCD panel related nodes (backlight, regulators and panel) to the
sama5d3 Display Module dtsi.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d3xdm.dtsi | 32
1 file changed, 32 insertions(+)
diff --git
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12,
at91sam9x5 family or sama5d3 family) provide a PWM device.
This driver add support for this PWM device.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt
Enable LCD related nodes and reference panel node in the hlcdc (High
LCD Controller) controller on sama5d3xek boards.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d31ek.dts | 24
arch/arm/boot/dts/sama5d33ek.dts | 24
Define the HLCDC (High LCD Controller) IP available on some sama5d3 SoCs
(i.e. sama5d31, sama5d33, sama5d34 and sama5d36).
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
arch/arm/boot/dts/sama5d3_lcd.dtsi | 26 ++
1 file changed, 26 insertions(+)
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clock subsystem.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
.../devicetree/bindings/clock/clps711x-clock.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
On Mon, 2014-06-09 at 15:08 +0300, Stanimir Varbanov wrote:
The driver is separated by functional parts. The core part
implements a platform driver probe and remove callbaks.
The probe enables clocks, checks crypto version, initialize
and request dma channels, create done tasklet and init
This patch adds DT binding documentation for the Cirrus Logic
CLPS711X-based CPUs clocksource subsystem.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
.../bindings/timer/cirrus,clps711x-timer.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Tomasz,
On Fri, Jun 6, 2014 at 4:41 PM, Mike Turquette mturque...@linaro.org wrote:
Quoting Tomasz Figa (2014-06-05 15:26:31)
On 05.06.2014 22:35, Doug Anderson wrote:
The aclk66_peric clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful to
On Mon, Jun 09, 2014 at 07:29:40PM +0900, Chanwoo Choi wrote:
+- regulator-initial-state: initial state for suspend state
+- regulator-state-[standby/mem/disk] sub-root node for suspend state
+ regulator-volt: voltage consumers may set in suspend state
+ regulator-mode: voltage mode
On Mon, Jun 09, 2014 at 07:29:39PM +0900, Chanwoo Choi wrote:
+ ret = of_property_read_u32(suspend_np, regulator-mode, pval);
+ if (!ret)
+ suspend_state-mode = pval;
If we're going to do that we'd need to define what modes mean in the DT
binding -
On Mon, Jun 09, 2014 at 11:37:47AM +0200, Javier Martinez Canillas wrote:
+ case REGULATOR_MODE_STANDBY:/* switch off */
+ if (id != MAX77802_LDO1 id != MAX77802_LDO20
+ id != MAX77802_LDO21 id != MAX77802_LDO3) {
+
On Mon, Jun 09, 2014 at 11:37:46AM +0200, Javier Martinez Canillas wrote:
+Optional node:
+- voltage-regulators : The regulators of max77802 have to be instantiated
+ under subnode named voltage-regulators using the following format.
Every other PMIC calls this node regulators...
+
On Mon, Jun 09, 2014 at 11:31:45AM +0800, Bo Shen wrote:
Signed-off-by: Bo Shen voice.s...@atmel.com
Applied, thanks.
signature.asc
Description: Digital signature
On Mon, Jun 09, 2014 at 11:31:43AM +0800, Bo Shen wrote:
Signed-off-by: Bo Shen voice.s...@atmel.com
Applied, thanks.
signature.asc
Description: Digital signature
Dne 3.6.2014 20:25, Julia Lawall napsal(a):
From: Stephen Boyd sb...@codeaurora.org
Failure to terminate an of_device_id table can lead to confusing
failures depending on where the compiler places the array. Add a
check to make sure these tables are terminated. Thanks to Mitchel
Humpherys
On 06/09/14 14:47, Michal Marek wrote:
Dne 3.6.2014 20:25, Julia Lawall napsal(a):
From: Stephen Boyd sb...@codeaurora.org
Failure to terminate an of_device_id table can lead to confusing
failures depending on where the compiler places the array. Add a
check to make sure these tables are
On 06/04/2014 01:17 PM, Mark Brown wrote:
You're saying you're controlling it from userspace. This is a
particular detail of what you are doing in your system. You happen to
want to control the devices you are hanging off the system with
userspace drivers but that's just what you're doing
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller, PWM
LEDs generically accessible from user space and an LM95245 temperature
sensor chip. The later three can also be found on the Colibri T30
module.
While at
The NVIDIA Tegra 3 based Apalis T30 module contains an Intel i210 resp.
i211 gigabit Ethernet controller, an STMPE811 ADC/touch controller, I2C
buses and PWM LEDs generically accessible from user space and an
LM95245 temperature sensor chip. The later four can also be found on
the Colibri T30
Hello Krzystof,
Thanks a lot for your feedback.
On 06/09/2014 06:04 PM, Doug Anderson wrote:
Krzystof,
On Mon, Jun 9, 2014 at 3:16 AM, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
MAX77802 is a PMIC that contains 10
This patch adds the device tree to support Toradex Apalis T30, a
computer on module which can be used on different carrier boards.
The module consists of a Tegra 3 SoC, two PMICs, 1 or 2 GB of DDR3L
RAM, eMMC, an LM95245 temperature sensor chip, an i210 resp. i211
gigabit Ethernet controller, an
On Tue, Jun 10, 2014 at 12:16:13AM +0200, Marcel Ziswiler wrote:
On 06/04/2014 01:17 PM, Mark Brown wrote:
You're saying you're controlling it from userspace. This is a
particular detail of what you are doing in your system. You happen to
want to control the devices you are hanging off the
Hello Krzysztof,
On 06/09/2014 12:22 PM, Krzysztof Kozlowski wrote:
On pon, 2014-06-09 at 11:37 +0200, Javier Martinez Canillas wrote:
Maxim MAX77802 is a power management chip that contains 10 high
efficiency Buck regulators, 32 Low-dropout (LDO) regulators used
to power up application
Hello Mark,
On 06/09/2014 09:47 PM, Mark Brown wrote:
On Mon, Jun 09, 2014 at 11:37:46AM +0200, Javier Martinez Canillas wrote:
+Optional node:
+- voltage-regulators : The regulators of max77802 have to be instantiated
+ under subnode named voltage-regulators using the following format.
Javier,
On Mon, Jun 9, 2014 at 3:55 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
* The RTC has many subtle differences between the 77686 and 77802.
They expanded it to handle a 200 year timeframe instead of 100 and
that meant that they had to shuffle the bits around
Hi Mark,
On 06/10/2014 04:21 AM, Mark Brown wrote:
On Mon, Jun 09, 2014 at 07:29:39PM +0900, Chanwoo Choi wrote:
+ret = of_property_read_u32(suspend_np, regulator-mode, pval);
+if (!ret)
+suspend_state-mode = pval;
If we're going to do that
we are early in the cycle and I feel there will be a v2 of the chipidea
stub. IMHO, controlling the vbus regulator should not be business of the
phy driver, so ci will have to deal with it.
vbus handling has already in chipidea common code, it treats vbus as a
regulator.
So, the glue
From: Chao Xie chao@marvell.com
The general composite clock supports div/mux/gate.
marvell SOCes have many clocks that need change
div and mux together. So it need the composite
clock that supports mix/gate.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/Makefile
From: Chao Xie chao@marvell.com
For the clk-frac, if it has table, we need to make
sure that the initial clock rate is one item of the
table.
If it is not, we use the first item in the table by default.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/clk-frac.c | 40
From: Chao Xie chao@marvell.com
For MMP series SOC, it will use some types of clock.
Add the device tree support for these kind of clocks.
It includes mux/div/mix/gate/factor clock.
Signed-off-by: Chao Xie chao@marvell.com
Conflicts:
drivers/clk/mmp/Makefile
---
From: Chao Xie chao@marvell.com
The platforms including pxa168/pxa910/mmp2.
After add clock device tree support. There is no need
to maintain mmp2-dt.c because it is same as mmp-dt.c now.
The file will be removed.
Compiling test for pxa168 because of lacking of platform.
The platform is too
From: Chao Xie chao@marvell.com
For Marvell MMP series SOC, many clocks share same register.
In the operations of these clock, a spin lock is needed to avoid
confilicts.
When parse the clock from the device tree and register the clock,
we do not know whether it share the register with others.
From: Chao Xie chao@marvell.com
To parse composite clock from device tree file, there are some
rules.
The clock to be composited will be the child of the composite
clock in device tree file.
It can support the composition of (mux,div,gate) clock defined
as common clock and (mix,gate) defined
From: Chao Xie chao@marvell.com
The clock type mix is a kind of clock combines div and mux.
This kind of clock can not allow to change div first then
mux or change mux first or div.
The reason is
1. Some clock has frequency change bit. Each time want to change
the frequency, there are some
From: Chao Xie chao@marvell.com
To support device tree for clock, we need pass the register
base and range to the clock.
There are many clock share same range of registers.
For example, clk1 has register as 0xd4210010 while clk2
has 0xd42100c0. If we map the register seperately. There
will
Hi Mark,
On 06/10/2014 04:16 AM, Mark Brown wrote:
On Mon, Jun 09, 2014 at 07:29:40PM +0900, Chanwoo Choi wrote:
+- regulator-initial-state: initial state for suspend state
+- regulator-state-[standby/mem/disk] sub-root node for suspend state
+regulator-volt: voltage consumers may set
From: Chao Xie chao@marvell.com
The patch set focuses at support device tree for clock.
The first part of the patches
clk: mmp: add prefix mmp for structures defined for clk-frac
clk: mmp: add spin lock for clk-frac
clk: mmp: add init callback for clk-frac
clk: mmp: move definiton of
From: Chao Xie chao@marvell.com
Move the definition of structure of mmp_clk_frac to
clk.h.
So device tree support can use this structure.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/clk-frac.c | 8
drivers/clk/mmp/clk.h | 32
From: Chao Xie chao@marvell.com
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. Some clocks has operations of out of reset and enable.
To enable clock, we need do out of reset and enable.
To disable clock, we may not need set
From: Chao Xie chao@marvell.com
The structures defined for clk-frac will be used out side
of clk-frac.c.
To avoid conflicts, add prefix mmp for these structures'
name.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/clk-frac.c | 23 ---
From: Chao Xie chao@marvell.com
The register used by clk-frac may be shared with
other clocks.
So it needs to use spin lock to protect the register
access.
Signed-off-by: Chao Xie chao@marvell.com
---
drivers/clk/mmp/clk-frac.c | 11 ++-
drivers/clk/mmp/clk-mmp2.c | 2 +-
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