On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka Bhadram wrote:
On 07/14/2014 05:10 PM, Dong Aisheng wrote:
(...)
diff --git a/drivers/net/can/m_can/Makefile b/drivers/net/can/m_can/Makefile
new file mode 100644
index 000..a6aae67
--- /dev/null
+++ b/drivers/net/can/m_can/Makefile
On Mon, Jul 14, 2014 at 03:01:51PM +0200, Marc Kleine-Budde wrote:
[...]
+#define IR_ERR_STATE(IR_BO | IR_EW | IR_EP)
+#define IR_ERR_LEC(IR_STE| IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
+#define IR_ERR_BUS(IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | IR_BEC \
+| IR_TOO |
On Mon, 2014-07-14 at 14:20 -0700, Stephen Boyd wrote:
On 07/14/14 06:58, Ivan T. Ivanov wrote:
On Fri, 2014-07-11 at 18:56 -0700, Stephen Boyd wrote:
On 07/10/14 02:53, Linus Walleij wrote:
On Wed, Jul 9, 2014 at 11:18 PM, Bjorn Andersson bj...@kryo.se wrote:
On Wed, Jul 9, 2014 at 1:53
Hi Mark,
On Mon, Jul 14, 2014 at 8:37 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Mon, Jul 14, 2014 at 01:16:09PM +0100, Harini Katakam wrote:
Add cadence-wdt bindings documentation.
Signed-off-by: Harini Katakam hari...@xilinx.com
---
v3 changes:
- Change reset property type and
Hi,
On Wed, Jul 09, 2014 at 03:54:34PM +0800, Chen-Yu Tsai wrote:
sun6i-apb0-gates uses the clock-indices DT property to indicate
valid gate bits or holes in between. However, the rest of sunxi
clock drivers use bitmaps for this purpose.
This patch modifies sun6i-apb0-gates to use bitmaps
On Wed, Jul 09, 2014 at 03:54:39PM +0800, Chen-Yu Tsai wrote:
With sun8i PRCM support available, we can add the PRCM clock and
reset controller nodes to the DTSI. Also update R_UART's clock
phandle and add it's reset control phandle.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied,
On Wed, Jul 09, 2014 at 03:54:35PM +0800, Chen-Yu Tsai wrote:
This patch adds allwinner,sun8i-a23-apb0-gates-clk, a A23 specific
compatible to the sun6i-a31-apb0-gates clock driver, along with the
gate bitmap.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks.
Maxime
--
Maxime
On 07/15/2014 11:57 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka Bhadram wrote:
+/* Test Register (TEST) */
+#define TEST_LBCK BIT(4)
+
+/* CC Control Register(CCCR) */
+#define CCCR_TEST BIT(7)
+#define CCCR_MON BIT(5)
+#define CCCR_CCE BIT(1)
Hi Lee,
On Thu, Jul 10, 2014 at 10:37:07AM +0100, Lee Jones wrote:
On Wed, 09 Jul 2014, Chen-Yu Tsai wrote:
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
the APB0 clock has different divisors, and some
* Lokesh Vutla lokeshvu...@ti.com [140714 21:09]:
On Monday 14 July 2014 09:53 PM, Tony Lindgren wrote:
* Lokesh Vutla lokeshvu...@ti.com [140714 07:47]:
In my experiments I observed that when RTC regulator is switched
off and switched on, there is an abort while accessing RTC registers.
On Wed, Jul 09, 2014 at 03:54:38PM +0800, Chen-Yu Tsai wrote:
The 8250_dw driver fails to probe if the specified clock isn't
registered at probe time. Even if a clock frequency is given,
the required clock might be gated because it wasn't properly
enabled.
This happened to me when the
On 07/15/2014 08:56 AM, Varka Bhadram wrote:
On 07/15/2014 11:57 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka Bhadram wrote:
+/* Test Register (TEST) */
+#define TEST_LBCKBIT(4)
+
+/* CC Control Register(CCCR) */
+#define CCCR_TESTBIT(7)
+#define
On Tue, 15 Jul 2014, Maxime Ripard wrote:
Hi Lee,
On Thu, Jul 10, 2014 at 10:37:07AM +0100, Lee Jones wrote:
On Wed, 09 Jul 2014, Chen-Yu Tsai wrote:
The Allwinner A23 SoC has a PRCM unit like the previous A31 SoC.
The differences are the AR100 clock can no longer be modified,
On 07/15/2014 12:40 PM, Marc Kleine-Budde wrote:
On 07/15/2014 08:56 AM, Varka Bhadram wrote:
On 07/15/2014 11:57 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka Bhadram wrote:
+/* Test Register (TEST) */
+#define TEST_LBCKBIT(4)
+
+/* CC Control Register(CCCR) */
On Tue, Jul 15, 2014 at 12:45:15PM +0530, Varka Bhadram wrote:
On 07/15/2014 12:40 PM, Marc Kleine-Budde wrote:
On 07/15/2014 08:56 AM, Varka Bhadram wrote:
On 07/15/2014 11:57 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka Bhadram wrote:
+/* Test Register (TEST) */
* Kishon Vijay Abraham I kis...@ti.com [140714 03:44]:
[1] is split into separate series in order for individual subsystem
Maintainers to pick up the patches. This series handles the PCIe
dt data for DRA7.
This series has better commit logs than the previous one modified as
suggested by
On 07/15/2014 12:44 PM, Dong Aisheng wrote:
On Tue, Jul 15, 2014 at 12:45:15PM +0530, Varka Bhadram wrote:
On 07/15/2014 12:40 PM, Marc Kleine-Budde wrote:
On 07/15/2014 08:56 AM, Varka Bhadram wrote:
On 07/15/2014 11:57 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 06:17:17PM +0530, Varka
* Peter Ujfalusi peter.ujfal...@ti.com [140710 04:26]:
Hi,
This set is to enable audio (finally) on the omap5-uevm. We have been waiting
for the palmas 32K clock driver to make it to upstream, which it did and it is
already in linux-next.
With the three patch we can have audio working on
On 07/15/2014 05:33 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 02:13:46PM +0200, Marc Kleine-Budde wrote:
On 07/14/2014 01:40 PM, Dong Aisheng wrote:
The patch adds the basic CAN TX/RX function support for Bosch M_CAN
controller.
For TX, only one dedicated tx buffer is used for sending
On 2014-07-15 at 00:18:05 +0200, Iyappan Subramanian isubraman...@apm.com
wrote:
This patch adds network driver for APM X-Gene SoC ethernet.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Ravi Patel rapa...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
On Mon, Jul 14, 2014 at 11:03:03PM +0100, Heiko Stübner wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Commit 3ab72f9156bb dt-bindings: add GIC-400 binding added the
arm,gic-400 compatible string, but the corresponding IRQCHIP_DECLARE
was never added to the gic driver.
On Tue, Jul 15, 2014 at 09:29:54AM +0200, Marc Kleine-Budde wrote:
On 07/15/2014 05:33 AM, Dong Aisheng wrote:
On Mon, Jul 14, 2014 at 02:13:46PM +0200, Marc Kleine-Budde wrote:
On 07/14/2014 01:40 PM, Dong Aisheng wrote:
The patch adds the basic CAN TX/RX function support for Bosch M_CAN
On Mon, Jul 14, 2014 at 11:20:17AM +0100, Daniel Mack wrote:
Hi Mark,
thanks a lot for your feedback! Much appreciated.
On 07/14/2014 11:52 AM, Mark Rutland wrote:
On Fri, Jul 11, 2014 at 11:06:33AM +0100, Daniel Mack wrote:
+++ b/Documentation/devicetree/bindings/input/cap1106.txt
On Tue, Jul 15, 2014 at 4:21 AM, Jonathan Cameron ji...@kernel.org wrote:
On 14/07/14 18:32, Philippe Reynes wrote:
Hi Jonathan,
regarding your comment below
snip
+static int max5821_get_value(struct iio_dev *indio_dev,
+int *val, int channel)
+{
+ struct
On 07/15/2014 10:26 AM, Dong Aisheng wrote:
+static void m_can_read_fifo(const struct net_device *dev, struct
can_frame *cf,
+ u32 rxfs)
+{
+ struct m_can_priv *priv = netdev_priv(dev);
+ u32 flags, fgi;
+
+ /* calculate the fifo get index for where to read data */
+
On Tue, Jul 15, 2014 at 07:39:40AM +0100, Harini Katakam wrote:
Hi Mark,
On Mon, Jul 14, 2014 at 8:37 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Mon, Jul 14, 2014 at 01:16:09PM +0100, Harini Katakam wrote:
Add cadence-wdt bindings documentation.
Signed-off-by: Harini Katakam
Hi Mark,
On Tue, Jul 15, 2014 at 2:29 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Jul 15, 2014 at 07:39:40AM +0100, Harini Katakam wrote:
Hi Mark,
On Mon, Jul 14, 2014 at 8:37 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Mon, Jul 14, 2014 at 01:16:09PM +0100, Harini Katakam
On Mon, Jul 14, 2014 at 07:15:48PM +0100, Arnd Bergmann wrote:
On Monday 14 July 2014 17:54:43 Catalin Marinas wrote:
On Tue, Jul 01, 2014 at 07:43:34PM +0100, Liviu Dudau wrote:
Introduce a default implementation for remapping PCI bus I/O resources
onto the CPU address space.
On Tue, Jul 15, 2014 at 10:46:32AM +0200, Marc Kleine-Budde wrote:
On 07/15/2014 10:26 AM, Dong Aisheng wrote:
+static void m_can_read_fifo(const struct net_device *dev, struct
can_frame *cf,
+ u32 rxfs)
+{
+ struct m_can_priv *priv = netdev_priv(dev);
On 07/15/2014 10:51 AM, Mark Rutland wrote:
On Mon, Jul 14, 2014 at 11:20:17AM +0100, Daniel Mack wrote:
Hmm, I thought about that, but there are - in theory - more details that
could be specified per channel. I left those functions out for the first
version, as I have no good way to test
On July 15, 2014 9:56:17 AM GMT+01:00, Antonio Borneo
borneo.anto...@gmail.com wrote:
On Tue, Jul 15, 2014 at 4:21 AM, Jonathan Cameron ji...@kernel.org
wrote:
On 14/07/14 18:32, Philippe Reynes wrote:
Hi Jonathan,
regarding your comment below
snip
+static int max5821_get_value(struct
On 07/15/2014 11:07 AM, Dong Aisheng wrote:
On Tue, Jul 15, 2014 at 10:46:32AM +0200, Marc Kleine-Budde wrote:
On 07/15/2014 10:26 AM, Dong Aisheng wrote:
+static void m_can_read_fifo(const struct net_device *dev, struct
can_frame *cf,
+ u32 rxfs)
+{
+
On 07/14/2014 05:03 PM, Lee Jones wrote:
On Mon, 14 Jul 2014, Stanimir Varbanov wrote:
On 07/11/2014 12:07 PM, Lee Jones wrote:
On Thu, 10 Jul 2014, Stanimir Varbanov wrote:
The Qualcomm QPNP PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
Hi Bjorn,
On 07/10/2014 06:43 PM, Stanimir Varbanov wrote:
On 07/10/2014 04:08 PM, Bjorn Andersson wrote:
On Thu, Jul 3, 2014 at 6:14 AM, Stanimir Varbanov svarba...@mm-sol.com
wrote:
[...]
+static const struct of_device_id qpnp_rtc_table[] = {
+ { .compatible = qcom,qpnp-rtc, },
+
Hello Thierry,
On Mon, 14 Jul 2014 12:05:43 +0200
Thierry Reding thierry.red...@gmail.com wrote:
On Mon, Jul 07, 2014 at 06:42:59PM +0200, Boris BREZILLON wrote:
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5 family or sama5d3 family)
This driver is a general version for tps611xx backlgiht chips of TI.
It supports tps61158, tps61161, tps61163 and tps61165 backlight driver
based on EasyScale protocol(1-Wire Control Interface).
EasyScale
EasyScale is a simple but flexible one pin interface to configure the current.
The interface
This driver a general version for tps611xx backlgiht chips of TI.
It supports tps61158, tps61161, tps61163 and tps61165 backlight driver
based on EasyScale protocol.
Daniel Jeong (2):
[RFC v5 1/2] backlight: add new tps611xx backlight driver
[RFC v5 2/2] backlight: device tree: add new
This commit is about tps611xx device tree documentation.
Signed-off-by: Daniel Jeong gshark.je...@gmail.com
---
.../video/backlight/tps611xx-backlight.txt | 26
1 file changed, 26 insertions(+)
create mode 100644
Hi Boris,
On Tuesday 15 July 2014 12:06:19 Boris BREZILLON wrote:
On Mon, 14 Jul 2014 12:05:43 +0200 Thierry Reding wrote:
On Mon, Jul 07, 2014 at 06:42:59PM +0200, Boris BREZILLON wrote:
The Atmel HLCDC (HLCD Controller) IP available on some Atmel SoCs (i.e.
at91sam9n12, at91sam9x5
On 07/15/2014 03:39 PM, Daniel Jeong wrote:
(...)
+
+static int tps611xx_backlight_remove(struct platform_device *pdev)
+{
+ struct tps611xx_bl_data *pchip = platform_get_drvdata(pdev);
+ const struct tps611xx_esdata *esdata = pchip-esdata;
+
+
On Tue, Jul 15, 2014 at 12:06:19PM +0200, Boris BREZILLON wrote:
On Mon, 14 Jul 2014 12:05:43 +0200 Thierry Reding thierry.red...@gmail.com
wrote:
On Mon, Jul 07, 2014 at 06:42:59PM +0200, Boris BREZILLON wrote:
[...]
diff --git a/Documentation/devicetree/bindings/drm/atmel-hlcdc-dc.txt
On Tue, Jul 15, 2014 at 12:20:02PM +0200, Laurent Pinchart wrote:
Hi Boris,
On Tuesday 15 July 2014 12:06:19 Boris BREZILLON wrote:
On Mon, 14 Jul 2014 12:05:43 +0200 Thierry Reding wrote:
On Mon, Jul 07, 2014 at 06:42:59PM +0200, Boris BREZILLON wrote:
The Atmel HLCDC (HLCD
Hello Mark,
I agree that the commit message could have a better description and I
understand your concerns. I'm not an SPI expert by any means but I did
my best to review the patches and provide feedback to Naveen on the
first iterations of the series.
On Mon, Jul 14, 2014 at 7:25 PM, Mark Brown
Hi Thierry,
On Tuesday 15 July 2014 12:37:19 Thierry Reding wrote:
On Tue, Jul 15, 2014 at 12:20:02PM +0200, Laurent Pinchart wrote:
On Tuesday 15 July 2014 12:06:19 Boris BREZILLON wrote:
On Mon, 14 Jul 2014 12:05:43 +0200 Thierry Reding wrote:
On Mon, Jul 07, 2014 at 06:42:59PM +0200,
On Thu, Jun 05, 2014 at 03:53:31PM +0200, Boris BREZILLON wrote:
Add vendor prefix for Foxlink Group.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
On Tue, Jul 15, 2014 at 11:21:57AM +0200, Marc Kleine-Budde wrote:
On 07/15/2014 11:07 AM, Dong Aisheng wrote:
On Tue, Jul 15, 2014 at 10:46:32AM +0200, Marc Kleine-Budde wrote:
On 07/15/2014 10:26 AM, Dong Aisheng wrote:
+static void m_can_read_fifo(const struct net_device *dev, struct
On Thu, Jun 05, 2014 at 03:53:32PM +0200, Boris BREZILLON wrote:
This panel is used by Atmel's SAMA5D3 Evaluation Kits (sama5d3xek) and
supported by the simple-panel driver.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../bindings/panel/foxlink,fl500wvr00-a0t.txt
On Tue, Jul 15, 2014 at 12:43:02PM +0200, Laurent Pinchart wrote:
Hi Thierry,
On Tuesday 15 July 2014 12:37:19 Thierry Reding wrote:
On Tue, Jul 15, 2014 at 12:20:02PM +0200, Laurent Pinchart wrote:
On Tuesday 15 July 2014 12:06:19 Boris BREZILLON wrote:
On Mon, 14 Jul 2014 12:05:43
On 07/14/2014 08:12 PM, Olof Johansson wrote:
On Tue, Jul 8, 2014 at 4:18 AM, Michal Simek michal.si...@xilinx.com wrote:
On 06/30/2014 07:15 AM, Olof Johansson wrote:
Hi,
On Sun, Jun 29, 2014 at 1:50 PM, Andreas Färber afaer...@suse.de wrote:
This allows to boot the Adapteva Parallella
On Tue, Jul 15, 2014 at 09:33:21AM +0530, Naveen Krishna Ch wrote:
On 15 July 2014 00:45, Mark Brown broo...@kernel.org wrote:
The problem isn't what you're trying to do, the problem is verifying
that it has been done correctly - making sure that everything has been
accounted for in the
This series patches add the support for NAND controller of hisilicon
hip04 Soc. These patches are base on branch integration-hilt-working-v3.14
in linaro landing-team git repository[1].
The NAND controller IP was developed by hisilicon and need a new driver
to support. The driver is usable and I
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
arch/arm/boot/dts/hip04.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 681267a..6ff48eb 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi-nand.txt | 40
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi-nand.txt
diff --git
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig |5 +
drivers/mtd/nand/Makefile|1 +
drivers/mtd/nand/hisi_nand.c | 836 ++
3 files changed, 842 insertions(+)
create mode 100644 drivers/mtd/nand/hisi_nand.c
Hi Thierry,
On Tuesday 15 July 2014 12:52:54 Thierry Reding wrote:
On Tue, Jul 15, 2014 at 12:43:02PM +0200, Laurent Pinchart wrote:
On Tuesday 15 July 2014 12:37:19 Thierry Reding wrote:
On Tue, Jul 15, 2014 at 12:20:02PM +0200, Laurent Pinchart wrote:
On Tuesday 15 July 2014 12:06:19
On Sat, 12 Jul 2014 14:37:16 -0400
Rob Clark robdcl...@gmail.com wrote:
On Sat, Jul 12, 2014 at 2:16 PM, Boris BREZILLON
boris.brezil...@free-electrons.com wrote:
Hello,
On Mon, 7 Jul 2014 18:42:58 +0200
Boris BREZILLON boris.brezil...@free-electrons.com wrote:
+int
This patch adds a driver for Microchips CAP1106, an I2C driven, 6-channel
capacitive touch sensor.
For now, only the capacitive buttons are supported, and no specific
settings that can be tweaked for individual channels, except for the
device-wide sensitivity gain. The defaults seem to work just
On Mon, 14 Jul 2014 12:18:08 +0200
Thierry Reding thierry.red...@gmail.com wrote:
On Fri, Jul 11, 2014 at 02:00:25PM +0200, Boris BREZILLON wrote:
On Fri, 11 Jul 2014 12:37:46 +0200 Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
On Thursday 10 July 2014 14:56:26 Boris
The pwm-fan driver enables control of fans connected to PWM lines.
This driver uses the PWM framework, so it is compatible with all
PWM devices that provide drivers through the PWM framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
Changes since v2:
- add CONFIG_PM_SLEEP around
On 07/15/2014 05:21 PM, Kamil Debski wrote:
The pwm-fan driver enables control of fans connected to PWM lines.
This driver uses the PWM framework, so it is compatible with all
PWM devices that provide drivers through the PWM framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
* Marek Belisko ma...@goldelico.com [140714 13:22]:
This patch series completes the GTA04 device tree to describe all hardware
components that are on the different variants of the GTA04 boards.
Marek Belisko (5):
arm: dts: omap3-gta04: Add missing nodes to fully describe gta04 board
On Tue, 15 Jul 2014 12:52:54 +0200
Thierry Reding thierry.red...@gmail.com wrote:
On Tue, Jul 15, 2014 at 12:43:02PM +0200, Laurent Pinchart wrote:
Hi Thierry,
On Tuesday 15 July 2014 12:37:19 Thierry Reding wrote:
On Tue, Jul 15, 2014 at 12:20:02PM +0200, Laurent Pinchart wrote:
Current SPI core has generic implementation for configuring
the Chip select gpios during .setup() .cleanup(). By modifying
the spi-s3c64xx.c driver to expect the cs-gpios property in SPI
device node instead of the subnode controller-data.
This way we can avoid parsing the cs-gpios in the driver.
This patch validates the cs-line (Chip select gpio) and
struct s3c64xx_spi_csinfo *cs object for both DT and NON-DT
platforms before using in .setup().
Also, check gpio_is_valid(spi-cs_gpio) in cleanup() before
freeing up.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier
This patch modifies the spi-s3c64xx.c driver to fetch the
Chip select or Slave select gpio line property cs-gpios
from SPI node instead of controller_data subnode.
Rename the property cs-gpio to cs-gpios in accordance
with the SPI core. Such that s3c64xx.c can use spi-cs_gpio
instead of parsing
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@
This adds regulator support to enable/disable the LCD voltage, using
'lcd-supply' as regulator name.
Signed-off-by: Alexander Stein alexander.st...@systec-electronic.com
---
.../devicetree/bindings/video/atmel,lcdc.txt | 3 +++
drivers/video/fbdev/atmel_lcdfb.c| 20
On Tue, Jul 15, 2014 at 12:38:58PM +0200, Javier Martinez Canillas wrote:
Hello Mark,
Don't top post.
On Mon, Jul 14, 2014 at 7:25 PM, Mark Brown broo...@kernel.org wrote:
On Mon, Jul 14, 2014 at 11:11:44AM +0530, Naveen Krishna Chatradhi wrote:
So, the .line field is used to specify a
Hi Marek,
You seem to add some DT nodes for hw that doesn't have drivers in
mainline. I think you should leave those out until the driver itself
is upstream and the bindings for it is documented.
On 14 July 2014 22:20, Marek Belisko ma...@goldelico.com wrote:
Signed-off-by: Marek Belisko
Hi Kukjin,
Am 04.07.2014 23:06, schrieb Kukjin Kim:
BTW Andreas, I can't use 'Färber' in my git tree so which one is right
or more preferred? Farber, Faerber, Ferber? Sorry.
Hm, git-am should in theory just work fine for this patch with UTF-8 on
Linux. As for Reviewed-by / Tested-by, some
On 14.07.2014 20:13, Mark Brown wrote:
On Mon, Jul 14, 2014 at 02:05:19PM +0200, Stefan Assmann wrote:
On 14.07.2014 14:00, Mark Brown wrote:
No, you need to implement clocks using the clock API. Please read the
changelogs for the above commits...
Yes, that's what I expected. Got any
On 07/15/2014 05:21 PM, Kamil Debski wrote:
The pwm-fan driver enables control of fans connected to PWM lines.
This driver uses the PWM framework, so it is compatible with all
PWM devices that provide drivers through the PWM framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
2014-07-01 17:09 GMT+02:00 Doug Anderson diand...@chromium.org:
+Olof who posted the patch that Yuvaraj referenced.
On Tue, Jul 1, 2014 at 5:20 AM, Yuvaraj Cd yuvaraj.l...@gmail.com wrote:
On Tue, Jul 1, 2014 at 12:27 PM, James Cameron qu...@laptop.org wrote:
On Mon, Jun 30, 2014 at
* Suman Anna s-a...@ti.com [140711 14:47]:
Add the hwmod data for the 13 instances of the system mailbox
IP in DRA7 SoC. The patch is needed for performing a soft-reset
while configuring the respective mailbox instance, otherwise is
a non-essential change for functionality. The modules are
On Tue, Jul 15, 2014 at 10:12:22AM +0100, Daniel Mack wrote:
On 07/15/2014 10:51 AM, Mark Rutland wrote:
On Mon, Jul 14, 2014 at 11:20:17AM +0100, Daniel Mack wrote:
Hmm, I thought about that, but there are - in theory - more details that
could be specified per channel. I left those
On Fri, 2014-07-11 at 11:13 +0200, Simon Horman wrote:
On Wed, Jul 09, 2014 at 02:23:35PM +0200, Geert Uytterhoeven wrote:
The documentation only mentioned the generic fallback compatible property.
Add the missing SoC-specific compatible properties, some of which are
already in use.
On Jun 17, 2014, at 1:33 PM, Kumar Gala ga...@codeaurora.org wrote:
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
Hi,
On Wednesday 18 June 2014 12:03 AM, Kumar Gala wrote:
Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
v5:
* Fix copy/paste error when killing qcom_ipq806x_sata_delay_us
v4:
* removed
This patch introduces polarity indication for pll power up bit
and for standby bit in order to have same code between stih416
and stih407 boards.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-fsyn.c | 12
This patch uses CLK_DIVIDER_ROUND_CLOSEST flag to specify
the divider has to round to closest div.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-mux.c | 3 ++-
1 file changed, 2 insertions(+), 1
The patch added support for DT registration of ClockGenC0
It includes 2 c32 type PLL and a 660 Quadfs.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
Acked-by: Peter Griffin peter.grif...@linaro.org
---
Naming convention was changed in dts file but the
clock binding documentation hasn't been updated.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Acked-by: Peter Griffin peter.grif...@linaro.org
---
.../bindings/clock/st/st,clkgen-divmux.txt | 28 +--
The patch added support for DT registration of ClockGenA0
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
---
drivers/clk/st/clkgen-pll.c | 16
1 file changed, 16 insertions(+)
diff
The patch added support for ClockGenD0/D2/D3
It includes one 660 Quadfs.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-fsyn.c | 46
tegra_clocks_apply_init_table needs to be called after the udelay loop has
been calibrated (see 441f199a37cfd66c5dd8dd45490bd3ea6971117d why that is).
On existing Tegra SoCs this was done by calling tegra_clocks_apply_init_table
from tegra_dt_init. To make this also work on ARM64, we need to
Tegra132 has almost the same clock structure as Tegra124, except for the CPU
related clocks.
Patch 1 is a small change to not stop initializing clocks when an error is
encountered
Patch 2 makes tegra_clocks_apply_init_table an arch_initcall to make it work
on ARM64
Patch 3 updates
Tegra132 has almost the same clock structure than Tegra124. This patch
documents the missing clock IDs.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
.../bindings/clock/nvidia,tegra124-car.txt |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git
Add support for the ccplex clocks in Tegra132.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/Makefile |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f7dfb72..4231865 100644
The patch added support for DT registration of ClockGenA9
It includes c32 type PLL.
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-pll.c | 16
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This patch
deals with the small differences.
--
I'm not entirely sure why the soc_therm clock needs to be enabled on Tegra132,
but turning it off results in a system hang. I presume this might be because
of fastboot initializing
Tegra132 has a few new clocks for the CPU complex (ccplex).
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
.../bindings/clock/nvidia,tegra132-ccplex-clk.txt | 27
include/dt-bindings/clock/tegra132-ccplex.h| 12 +
2 files changed, 39
Just continue initializing clocks if there's an error on one of them. This
is useful if there's a mistake in the inittable, because the system could
hang if clk_disable_unused() disables some of the critical clocks in this
table.
Signed-off-by: Peter De Schrijver pdeschrij...@nvidia.com
---
converts stm_fs tables into static const
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
---
drivers/clk/st/clkgen-fsyn.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c
Changes in v3:
- Change commit message
- Remove uncessary (void *) cast
- add a block diagram for flexgen clock binding documentation
Changes in v2:
- use static const for clkgen_pll_data and stm_fs tables (from
Peter Griffin review)
- add 326 and 333 Mhz frequencies
- cosmetic
This patch is the Flexgen implementation reusing as much as possible
of Common Clock Framework functions.
The idea is to have an instance of struct flexgen per output clock.
It represents the clock cross bar (by a mux element), and the pre and final
dividers
(using dividers and gates elements).
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
---
drivers/clk/st/clkgen-fsyn.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index a7e5db4..e8d599d 100644
--- a/drivers/clk/st/clkgen-fsyn.c
converts clkgen_pll_data tables into static const
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
---
drivers/clk/st/clkgen-pll.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c
A Flexgen structure is composed by:
- a clock cross bar (represented by a mux element)
- a pre and final dividers (represented by a divider and gate elements)
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Acked-by: Peter Griffin peter.grif...@linaro.org
---
This patch adds the support of quadfs reset handling.
Signed-off-by: Olivier Bideau olivier.bid...@st.com
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-fsyn.c | 5 +
1 file changed, 5 insertions(+)
The patch supports the A9-mux clocks used by ClockGenA9
Signed-off-by: Gabriel Fernandez gabriel.fernan...@linaro.org
Signed-off-by: Olivier Bideau olivier.bid...@st.com
Acked-by: Peter Griffin peter.grif...@linaro.org
---
drivers/clk/st/clkgen-mux.c | 9 +
1 file changed, 9
1 - 100 of 187 matches
Mail list logo
