On 16 July 2014 09:17, Dr. H. Nikolaus Schaller wrote:
> Am 15.07.2014 um 14:45 schrieb Joachim Eastwood:
>
>> Hi Marek,
>>
>> You seem to add some DT nodes for hw that doesn't have drivers in
>> mainline. I think you should leave those out until the driver itself
>> is upstream and the bindings f
Hi Thierry,
Thanks for your comments.
On Fri, Jul 18, 2014 at 4:18 AM, Thierry Reding
wrote:
> On Fri, Jul 18, 2014 at 02:20:39AM +0530, Ajay kumar wrote:
>> +devicetree@vger.kernel.org
>>
>> On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar wrote:
>> > Add DT binding documentation for panel-lvds dri
Hi,
Dan Murphy wrote:
> The TI SoC reset controller support utilizes the
> reset controller framework to give device drivers or
> function drivers a common set of APIs to call to reset
> a module.
>
> The reset-ti is a common interface to the reset framework.
> The register data is retrieved dur
On 18 July 2014 11:47, Olof Johansson wrote:
> Why complicate it by using two properties?
>
> If there is no property, then the CPUs are assumed to be controlled
> independently.
>
> if there is a clock-master = property, then that points at
> the cpu that is the main one controlling clock for th
On Thu, Jul 17, 2014 at 10:35 PM, Viresh Kumar wrote:
> Clock lines may or may not be shared among different CPUs on a platform. When
> clock lines are shared between CPUs, they change DVFS state together.
>
> Possible configurations:
>
> 1.) All CPUs share a single clock line.
> 2.) All CPUs have
This patchset support Exynos3250 ADC (Analog Digital Converter) because
Exynos3250 has additional special clock for ADC IP.
Changes from v5:
- Add acked message by Kukjin Kim
- Add reviewed messgae by Tomasz Figa
- Fix typo (for for -> for)
Changes from v4:
- Use 'exynos_adc_data' structure inste
This patchset fix wrong compatible string for Exynos3250 ADC. Exynos3250 SoC
need to control only special clock for ADC. Exynos SoC except for Exynos3250
has not included special clock for ADC. The exynos ADC driver can control
special clock if compatible string is 'exynos3250-adc-v2'.
Signed-off-
This patch control special clock for ADC in Exynos series's FSYS block.
If special clock of ADC is registerd on clock list of common clk framework,
Exynos ADC drvier have to control this clock.
Exynos3250/Exynos4/Exynos5 has 'adc' clock as following:
- 'adc' clock: bus clock for ADC
Exynos3250 ha
This patchset add 'exynos_adc_data' structure which includes some functions
to control ADC operation and specific data according to ADC version (v1 or v2).
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Reviewed-by: Naveen Krishna Chatradhi
Reviewed-by: Tomasz Figa
---
drivers/iio/adc/ex
This patch add DT binding documentation for Exynos3250 ADC IP. Exynos3250 has
special clock ('sclk_adc') for ADC which provide clock to internal ADC.
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Reviewed-by: Naveen Krishna Chatradhi
Reviewed-by: Tomasz Figa
Acked-by: Kukjin Kim
---
..
Clock lines may or may not be shared among different CPUs on a platform. When
clock lines are shared between CPUs, they change DVFS state together.
Possible configurations:
1.) All CPUs share a single clock line.
2.) All CPUs have independent clock lines.
3.) CPUs within a group/cluster share clo
Add a codec driver for the Everest ES8328. It supports two separate audio
outputs and two separate audio inputs.
Signed-off-by: Sean Cross
---
Documentation/devicetree/bindings/sound/es8328.txt | 38 +
sound/soc/codecs/Kconfig | 13 +
sound/soc/codecs/Makefile
This adds an initial machine driver for the ES8328 audio codec on Freescale
boards. The driver supports headphones and an audio regulator for an onboard
speaker amp.
Signed-off-by: Sean Cross
---
.../devicetree/bindings/sound/imx-audio-es8328.txt | 61 ++
sound/soc/fsl/Kconfig
Everest Semiconductor makes audio codecs.
Signed-off-by: Sean Cross
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 4
This patchset adds support for the Everest Semi ES8328 audio codec, used in
the Novena open source laptop. It also adds support for using the es8328 on
IMX boards.
We write a machine driver rather than using simple-card because the machine
driver needs to support regulators for the speaker amps a
Jonathan Cameron wrote:
>
> On 27/06/14 05:30, Chanwoo Choi wrote:
> > Changes from v4:
> > - Use 'exynos_adc_data' structure instead of 'exynos_adc_ops' structure
> >and remove enum variable of ADC version
> > - Fix wrong name of special clock (sclk_tsadc -> sclk_adc)
> > - Add reviewed messa
Hi Beniamino,
于 2014年07月18日 03:24, Beniamino Galvani 写道:
On Thu, Jul 17, 2014 at 02:08:14PM +0800, caesar wrote:
Signed-off-by: caesar
Hi Caesar,
just a couple of comments below.
---
drivers/pwm/pwm-rockchip.c | 108 -
1 file changed, 88 insert
On 18 July 2014 06:32, Rafael J. Wysocki wrote:
>> > only support the following cases:
>> >
>> > * One clock for all CPUs
>> > * One clock for each CPU
>>
>> Yeah, so I also proposed this yesterday that we stick to only these
>> two implementations for now. And was looking at how would the
>> cp
Dear Laurent
On 7/17/2014 7:00 PM, Laurent Pinchart wrote:
Hi Josh,
What's the status of this patch set ? Do you plan to rebase and resubmit it ?
Thanks for the reminding.
yes, I will rebase it and resubmit the new version for this patch set
with the data bus width support.
Thanks.
Best R
Hi Thierry,
On 07/17/2014 07:38 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:24PM +0900, YoungJun Cho wrote:
This patch adds DT bindings for s6e3fa0 panel.
The bindings describes panel resources and display timings.
The commit message here should preferably say which platform this
Hi Thierry,
Thank you a lot for kind comments.
On 07/17/2014 07:36 PM, Thierry Reding wrote:
On Thu, Jul 17, 2014 at 06:01:25PM +0900, YoungJun Cho wrote:
[...]
diff --git a/drivers/gpu/drm/panel/panel-s6e3fa0.c
b/drivers/gpu/drm/panel/panel-s6e3fa0.c
[...]
+/* Manufacturer Command Set */
+
On Thursday, July 17, 2014 01:11:45 PM Viresh Kumar wrote:
> On 17 July 2014 13:05, Thomas Petazzoni
> wrote:
> > Could you summarize what is the issue with the binding?
> >
> > At least for the case where we have one clock per CPU, the DT binding
> > is really dead simple: each CPU node can carry
There exist 2 variants using either the act8846 or rk808 as pmic, while the
rest of the board stays the same.
Signed-off-by: Heiko Stuebner
Tested-by: Will Deacon
---
arch/arm/boot/dts/rk3288-evb-act8846.dts | 134 +++
arch/arm/boot/dts/rk3288-evb-rk808.dts | 18 +
Node definitions shared by all rk3288 based boards.
Signed-off-by: Heiko Stuebner
Tested-by: Will Deacon
---
arch/arm/boot/dts/rk3288.dtsi | 552 ++
1 file changed, 552 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3288.dtsi
diff --git a/arch/arm
Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.
Signed-off-by: Heiko Stuebner
Tested-by: Will Deacon
---
arch/arm/mach-rockchip/Kconfig| 1 +
arch/arm/mach-rockchip/rockchip.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/ma
The new rk3288 needs a bigger gpio space, as it has 9 gpio banks.
Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Tested-by: Will Deacon
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 87b63fd
The debug uart settings from the DEBUG_RK3X_UART options are usable on
all Rockchip SoCs from the rk30xx and rk31xx series but not on the
new rk3288 SoCs. Thus clarify their use to prevent confusion.
Signed-off-by: Heiko Stuebner
---
arch/arm/Kconfig.debug | 8
1 file changed, 4 inserti
The uarts on rk3288 are still compatible with the dw_8250, but located
at a different position and need DEBUG_UART_8250_WORD enabled.
Signed-off-by: Heiko Stuebner
Reviewed-by: Doug Anderson
Tested-by: Doug Anderson
Tested-by: Will Deacon
---
arch/arm/Kconfig.debug | 12 +++-
1 file c
As announced parts from ARM they will probably be used in socs shortly.
Signed-off-by: Heiko Stuebner
Acked-by: Mark Rutland
---
Documentation/devicetree/bindings/arm/cpus.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b/Documentation/d
This series adds the initial support for Rockchip rk3288 socs including
debug uart and devicetree files for the rk3288 evaluation board and
enables these boards to boot into an initramfs.
Boards using uboot need an updated bootloader, which must start the timer
supplying the architected timer, whi
This patch adds the registers, bit fields and compatible strings
required to support for the 1 TMU channels on Exynos3250.
Signed-off-by: Chanwoo Choi
[Add MUX address setting bits by Jonghwa Lee]
Signed-off-by: Jonghwa Lee
Acked-by: Kyungmin Park
Reviewed-by: Amit Daniel Kachhap
---
.../devic
On 07/17/14 09:17, Stanimir Varbanov wrote:
> Hello everyone,
>
> Here is the continuation of patch sets sent recently about Qualcomm
> QPNP SPMI PMICs.
>
> The previous version of the patch set can be found at [1].
>
> Changes since v1:
> - removed completely custom *of* parser
> - renamed the m
On Fri, Jul 18, 2014 at 02:20:39AM +0530, Ajay kumar wrote:
> +devicetree@vger.kernel.org
>
> On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar wrote:
> > Add DT binding documentation for panel-lvds driver.
> >
> > Signed-off-by: Ajay Kumar
> > ---
> > .../devicetree/bindings/panel/panel-lvds.txt
Hello Kukjin,
On 06/24/2014 06:28 PM, Doug Anderson wrote:
> This adds cros_ec to exynos5420-peach-pit and exynos5800-peach-pi,
> including:
> * The keyboard
> * The i2c tunnel
> * The tps65090 under the i2c tunnel
> * The battery under the i2c tunnel
>
> To add extra motivation, it should be not
+devicetree@vger.kernel.org
On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar wrote:
> From: Vincent Palatin
>
> Add DT binding documentation for ps8622/ps8625 bridge driver.
>
> Signed-off-by: Vincent Palatin
> Signed-off-by: Ajay Kumar
> ---
> .../devicetree/bindings/drm/bridge/ps8622.txt |
+devicetree@vger.kernel.org
On Fri, Jul 18, 2014 at 2:13 AM, Ajay Kumar wrote:
> Add DT binding documentation for panel-lvds driver.
>
> Signed-off-by: Ajay Kumar
> ---
> .../devicetree/bindings/panel/panel-lvds.txt | 50
>
> 1 file changed, 50 insertions(+)
> cre
On Thu, Jul 17, 2014 at 08:57:09PM +0100, Mark Brown wrote:
> On Tue, Jul 15, 2014 at 09:41:33AM +0800, Sean Cross wrote:
>
> > Add a codec driver for the Everest ES8328. It supports two separate audio
> > outputs and two separate audio inputs.
>
> This looks mostly fine so I've applied it, ther
On Tue, Jul 15, 2014 at 09:41:34AM +0800, Sean Cross wrote:
> This adds an initial machine driver for the ES8328 audio codec on Freescale
> boards. The driver supports headphones and an audio regulator for an onboard
> speaker amp.
Applied, thanks.
signature.asc
Description: Digital signature
On Tue, Jul 15, 2014 at 09:41:33AM +0800, Sean Cross wrote:
> Add a codec driver for the Everest ES8328. It supports two separate audio
> outputs and two separate audio inputs.
This looks mostly fine so I've applied it, there are some issues below -
please send followups fixing them.
> + if
From: "Ivan T. Ivanov"
Available 'power-source' labels differ between chips.
Use just VIN0-VIN14 in the input source names.
PM8018, PM8038, PM8058, PM8917, PM8921 pin controller hardware
support only one function 'gpio'. Currently GPIO's will
support only 'normal' mode. Rest of the modes will be
Hello Mark,
On 07/17/2014 08:46 PM, Mark Brown wrote:
> On Wed, Jul 16, 2014 at 05:19:07PM +0200, Javier Martinez Canillas wrote:
>> This reverts commit 3146beec21b64f4551fcf0ac148381d54dc41b1b.
>
> For the benefit of those who haven't memorized the SHA1s of every commit
> that's "spi: s3c64xx: A
On Thu, Jul 17, 2014 at 02:08:14PM +0800, caesar wrote:
> Signed-off-by: caesar
Hi Caesar,
just a couple of comments below.
> ---
> drivers/pwm/pwm-rockchip.c | 108
> -
> 1 file changed, 88 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/p
On 17/07/14 18:07, Jassi Brar wrote:
On 17 July 2014 20:39, Sudeep Holla wrote:
On 17/07/14 13:56, Jassi Brar wrote:
On 17 July 2014 16:01, Sudeep Holla wrote:
[...]
This note could be added as how this mailbox works in general and
it's not just Rx right ? Even Tx done is based on
On Wed, Jul 16, 2014 at 05:19:10PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi
>
> This patch replaces the "cs-gpio" from "controller-data" node
> as was specified in the old binding and uses the standard
> "cs-gpios" property expected by the SPI core as is defined now
On Wed, Jul 16, 2014 at 05:19:09PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi
>
> Samsung SPI driver now uses the generic SPI "cs-gpios"
> binding so update the documentation accordingly.
Applied, thanks. Please do try to use changelogs that are consistent
with the
On Wed, Jul 16, 2014 at 05:19:08PM +0200, Javier Martinez Canillas wrote:
> From: Naveen Krishna Chatradhi
>
> The s3c64xx SPI driver uses a custom DT binding to specify
> the GPIO used to drive the chip select (CS) line instead of
> using the generic "cs-gpios" property already defined in:
> Doc
On Wed, Jul 16, 2014 at 05:19:07PM +0200, Javier Martinez Canillas wrote:
> This reverts commit 3146beec21b64f4551fcf0ac148381d54dc41b1b.
For the benefit of those who haven't memorized the SHA1s of every commit
that's "spi: s3c64xx: Added provision for dedicated cs pin" - please
include the human
On Thu, Jul 17, 2014 at 03:40:00PM +0200, Wolfram Sang wrote:
> On Fri, Jul 11, 2014 at 10:50:14AM +0200, Uwe Kleine-König wrote:
> > Olof Johansson pointed out that usually the company name is picked as
> > namespace prefix to specific properties. So expect "energymicro,location"
> > but fall back
On Thu, Jul 17, 2014 at 10:33 AM, pramod gurav
wrote:
> Hi Bjorn,
>
> On Wed, Jul 16, 2014 at 4:30 AM, Bjorn Andersson
> wrote:
>> Driver for the Resource Power Manager (RPM) found in Qualcomm 8660, 8960
>> and 8064 based devices. The driver exposes resources that child drivers
>> can operate on;
Hi Bjorn,
On Wed, Jul 16, 2014 at 4:30 AM, Bjorn Andersson
wrote:
> Driver for the Resource Power Manager (RPM) found in Qualcomm 8660, 8960
> and 8064 based devices. The driver exposes resources that child drivers
> can operate on; to implementing regulator, clock and bus frequency
> drivers.
>
On Thursday 17 July 2014 22:24:43 Jassi Brar wrote:
> On 17 July 2014 19:18, Arnd Bergmann wrote:
> > On Thursday 17 July 2014 19:02:53 Jassi Brar wrote:
> >> From a few hundred micro-sec for CPU reset, to potentially tens of
> >> milli-sec for some I2C transaction ... yes we do have for I2C over
Mark
On 07/17/2014 11:58 AM, Mark Brown wrote:
> On Mon, Jul 14, 2014 at 03:10:45PM -0500, Dan Murphy wrote:
>
> There's a few smallish issues below but this is basically good so I've
> applied it, please send incremental fixed for the things below.
>
>> +/* Turn on Class D amplifier */
>> +
On 17 July 2014 20:39, Sudeep Holla wrote:
>
>
> On 17/07/14 13:56, Jassi Brar wrote:
>>
>> On 17 July 2014 16:01, Sudeep Holla wrote:
>>>
>>> On 17/07/14 07:25, Jassi Brar wrote:
>
>> + u32 val;
>> +
>> + pr_debug("%s:%d\n", __func__, __LINE__);
>
>
On Mon, Jul 14, 2014 at 03:10:45PM -0500, Dan Murphy wrote:
There's a few smallish issues below but this is basically good so I've
applied it, please send incremental fixed for the things below.
> + /* Turn on Class D amplifier */
> + snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_CLAS
On 17 July 2014 19:18, Arnd Bergmann wrote:
> On Thursday 17 July 2014 19:02:53 Jassi Brar wrote:
>
>> > Losing half the RAM or PCI should not be a problem, you'd just run
>> > with reduced functionality. You wouldn't want to do that in practice,
>> > but it's different from a hard dependency.
>>
Add the prm_resets node to the prm parent node.
Add the omap54xx_resets file to define the
omap5 reset lines that are handled by this reset
framework.
Signed-off-by: Dan Murphy
---
v3 - No changes
arch/arm/boot/dts/omap5.dtsi |7
arch/arm/boot/dts/omap54xx-resets.dtsi | 6
Add the prcm_resets node to the prcm parent node.
Add the am34xx_resets file to define the
am34xx reset lines that are handled by this reset
framework.
Signed-off-by: Dan Murphy
---
v3 - No changes
arch/arm/boot/dts/am4372.dtsi|7 +
arch/arm/boot/dts/am43xx-resets.dtsi | 52
Describe the TI reset DT entries for TI SoC's.
Signed-off-by: Dan Murphy
---
v3 - Changed Headline no other changes
.../devicetree/bindings/reset/ti,reset.txt | 103
1 file changed, 103 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/ti,r
The TI SoC reset controller support utilizes the
reset controller framework to give device drivers or
function drivers a common set of APIs to call to reset
a module.
The reset-ti is a common interface to the reset framework.
The register data is retrieved during initialization
of the reset driv
Add the prcm_resets node to the prcm parent node.
Add the am33xx_resets file to define the
am33xx reset lines that are handled by this reset
framework.
Signed-off-by: Dan Murphy
---
v3 - No changes
arch/arm/boot/dts/am33xx-resets.dtsi | 42 ++
arch/arm/boot/d
Add the prcm_resets node to the prm parent node.
Add the draxx_resets file to define the
dra7xx reset lines that are handled by this reset
framework.
Signed-off-by: Dan Murphy
---
v3 - No changes
arch/arm/boot/dts/dra7.dtsi |7 +++
arch/arm/boot/dts/dra7xx-resets.dtsi | 82
Document DT bindings used to describe the Qualcomm SPMI PMICs.
Currently the SPMI PMICs supported are pm8941, pm8841 and pma8084.
Signed-off-by: Stanimir Varbanov
---
.../devicetree/bindings/mfd/qcom,pm8xxx-spmi.txt | 49
1 files changed, 49 insertions(+), 0 deletions(-)
The pm8941 and pm8841 spmi devicetree nodes are childrens of
spmi pmic arbiter. The msm8974 SoC uses two PMIC chips
pm8941 and pm8841. Every PMIC chip has two spmi bus slave id's.
Signed-off-by: Stanimir Varbanov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 37 +++
The pm8921-core driver presently supports pm8921 and pm8058
Qualcomm PMICs. To avoid confusion with new generation PMICs
(like pm8941) rename the pm8921-core driver to more
appropriate name pm8xxx-ssbi, which reflects better that
those chips use SSBI interface.
Signed-off-by: Stanimir Varbanov
-
From: Josh Cartwright
The Qualcomm SPMI PMIC chips are components used with the
Snapdragon 800 series SoC family. This driver exists
largely as a glue mfd component, it exists to be an owner
of an SPMI regmap for children devices described in
device tree.
Signed-off-by: Stanimir Varbanov
---
Hello everyone,
Here is the continuation of patch sets sent recently about Qualcomm
QPNP SPMI PMICs.
The previous version of the patch set can be found at [1].
Changes since v1:
- removed completely custom *of* parser
- renamed the mfd driver from qpnp-spmi to pm8xxx-spmi
- now MFD_PM8XXX_SPM
Hi Maxime,
El 17/07/14 06:08, Maxime Ripard escribió:
PLL6 out of reset is running at 2.4GHz, which is outside of its operating
boundaries.
Enforce its maximum frequency as set in the datasheet to make sure we stays
within these bounds.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun
Hi Maxime,
El 17/07/14 06:08, Maxime Ripard escribió:
In the A13, the out of reset frequency for the PLL6 is too high to be actually
working.
Hence, we need to be able to lower down its frequency whenever we need to use
the clock to some acceptable frequency.
This patch adds two new properties
On Thu, Jul 17, 2014 at 8:29 AM, Rob Clark wrote:
> On Thu, Jul 17, 2014 at 4:10 AM, divya ojha wrote:
[...]
>> Don't we need to have a if(regulator_enabled) check after
>> devm_regulator_get function ?
>> I see a similar test after camera regulator_get function call.
>
> tbh, I'm not 100% sure.
On Thu, Jul 17, 2014 at 3:50 AM, Bjorn Andersson wrote:
>> On Wed, Jul 16, 2014 at 4:30 AM, Bjorn Andersson
>> wrote:
> [...]
>>> + rpm@108000 {
>>> + compatible = "qcom,rpm-msm8960";
>>> + reg = <0x108000 0x1000>;
>>> + qcom,ipc = <&apcs 0x8 2>;
>>
On Thu, Jul 17, 2014 at 4:10 AM, divya ojha wrote:
> Hi Rob,
>
> On Tue, Jul 8, 2014 at 9:30 PM, Rob Clark wrote:
>> Now that we (almost) have enough dependencies in place (MMCC, RPM, etc),
>> add necessary DT support so that we can use drm/msm on upstream kernel.
>>
>> Signed-off-by: Rob Clark
From: "Ivan T. Ivanov"
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm GPIO and MPP sub-function blocks found in the PMIC chips.
Signed-off-by: Ivan T. Ivanov
---
drivers/pinctrl/Kconfig | 12 +
drivers/pinctrl/Makefile |
From: "Ivan T. Ivanov"
Hi,
This is second version of the patches posted earlier[1].
Patches could be applied on top of the Bjorn Andersson
qcom,pm8xxx-gpio driver, which could be found here[2].
Fist patch modify Bjorn's driver and bindings to make room
for newer Qualcomm PMIC chips. It is not
From: "Ivan T. Ivanov"
DT binding documentation for qcom,pm8xxx-mpp pinctrl drivers.
Signed-off-by: Ivan T. Ivanov
---
.../bindings/pinctrl/qcom,pm8xxx-mpp.txt | 199 +
1 file changed, 199 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctr
From: "Ivan T. Ivanov"
Add nodes for PM8941 and PM8841 GPIO and MPP sub-functions.
Signed-off-by: Ivan T. Ivanov
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 61 +
1 file changed, 61 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi
b/arch/arm/bo
On 17/07/14 13:56, Jassi Brar wrote:
On 17 July 2014 16:01, Sudeep Holla wrote:
On 17/07/14 07:25, Jassi Brar wrote:
+ u32 val;
+
+ pr_debug("%s:%d\n", __func__, __LINE__);
Please remove all these debug prints.
These are as good as absent unless DEBUG is defined.
Yes
On 7/17/2014 8:55 AM, Mark Rutland wrote:
Hi Jason,
On Thu, Jul 17, 2014 at 02:18:54PM +0100, Jason Cooper wrote:
On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
Hi Santosh,
On 07/17/2014 05:58 PM, Grygorii Strashko wrote:
The Keystone 2 has MDIO HW block which are compatible
to Davinci SoCs:
See "Gigabit Ethernet (GbE) Switch Subsystem"
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
Hence, add corresponding DT entry for Keystone 2.
This is upda
The Keystone 2 has MDIO HW block which are compatible
to Davinci SoCs:
See "Gigabit Ethernet (GbE) Switch Subsystem"
See http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf
Hence, add corresponding DT entry for Keystone 2.
Signed-off-by: Grygorii Strashko
---
arch/arm/boot/dts/keystone.dtsi | 11
On Thu, Jul 17, 2014 at 02:55:34PM +0100, Mark Rutland wrote:
> Hi Jason,
>
> On Thu, Jul 17, 2014 at 02:18:54PM +0100, Jason Cooper wrote:
> > On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com
> > wrote:
> > > From: Suravee Suthikulpanit
> > >
> > > This patch set introdu
On 7/17/2014 7:48 AM, Jason Cooper wrote:
On Tue, Jul 15, 2014 at 12:03:03AM +0200, Heiko Stübner wrote:
From: Suravee Suthikulpanit
Commit 3ab72f9156bb "dt-bindings: add GIC-400 binding" added the
"arm,gic-400" compatible string, but the corresponding IRQCHIP_DECLARE
was never added to the gi
Hello Naveen,
On Thu, Jul 17, 2014 at 6:21 AM, Naveen Krishna Ch
wrote:
>
> Can you pull the 3/4 and 4/4 patches.
>
Patch 4/4 depends on the max77802 support series [0] since the ADC
uses the max77802 ldo9 regulator as its voltage supply. So that patch
can't be merged before the series land in m
Hi,
On Thursday, July 17, 2014 05:41:16 PM Naveen Krishna Ch wrote:
> Hello Sachin,
>
> On 17 July 2014 17:24, Sachin Kamat wrote:
> > Hi Naveen,
> >
> > On Thu, Jul 17, 2014 at 4:49 PM, Naveen Krishna Chatradhi
> > wrote:
> >> This patch updates the IIO based ADC driver to use syscon and regm
Hi Jason,
On Thu, Jul 17, 2014 at 02:18:54PM +0100, Jason Cooper wrote:
> On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com wrote:
> > From: Suravee Suthikulpanit
> >
> > This patch set introduces support for MSI(-X) in GICv2m specification,
> > which is implemented in some
On Thursday 17 July 2014 19:02:53 Jassi Brar wrote:
> On 16 July 2014 01:39, Arnd Bergmann wrote:
> > On Tuesday 15 July 2014 23:07:58 Jassi Brar wrote:
>
> >> >> diff --git a/arch/arm/mach-mb86s7x/Kconfig
> >> >> b/arch/arm/mach-mb86s7x/Kconfig
> >> >> new file mode 100644
> >> >> index 000
On Fri, Jul 11, 2014 at 10:50:14AM +0200, Uwe Kleine-König wrote:
> Olof Johansson pointed out that usually the company name is picked as
> namespace prefix to specific properties. So expect "energymicro,location"
> but fall back to the previously introduced name "efm32,location".
>
> Cc: Olof Joh
On Thu, Jul 10, 2014 at 07:14:15PM +0200, Boris BREZILLON wrote:
> Hello,
>
> This series moves the AIC driver to the irqchip directory and make use of
> the generic chip framework whenever possible.
>
> This driver only support DT boards (all legacy board files should be soon
> replaced by their
On 16 July 2014 01:39, Arnd Bergmann wrote:
> On Tuesday 15 July 2014 23:07:58 Jassi Brar wrote:
>> >> diff --git a/arch/arm/mach-mb86s7x/Kconfig b/arch/arm/mach-mb86s7x/Kconfig
>> >> new file mode 100644
>> >> index 000..44f5b0c
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-mb86s7x/Kconfig
>
On Mon, Jul 14, 2014 at 11:03:03PM +0100, Heiko Stübner wrote:
> From: Suravee Suthikulpanit
>
> Commit 3ab72f9156bb "dt-bindings: add GIC-400 binding" added the
> "arm,gic-400" compatible string, but the corresponding IRQCHIP_DECLARE
> was never added to the gic driver.
>
> Therefore add the mi
On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> This patch set introduces support for MSI(-X) in GICv2m specification,
> which is implemented in some variation of GIC400.
>
> This depends on and has been tested with the V7 of"Add s
Hi Suravee,
Apologies for the late reply on this one. I was hoping that Marc would
be able to take another look at this, but he's away at present.
On Thu, Jul 10, 2014 at 12:05:03AM +0100, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> ARM GICv2m specification extends GI
On Wed, Jul 09, 2014 at 06:05:02PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> This patch restructures the code to prepare for future MSI support.
> It moves the declaration of structures and functions into the header file,
> and omit the static prefix.
>
> Sinc
On Wed, Jul 09, 2014 at 06:05:03PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> ARM GICv2m specification extends GICv2 to support MSI(-X) with
> a new set of register frames. This patch introduces support for
> the non-secure GICv2m register frame.
>
> The driver
On Thu, Jul 17, 2014 at 11:23:42AM +0100, Lee Jones wrote:
> Hi Wolfram,
>
> Are you going to take a lot at this set?
Sure thing, yet I won't make it for 3.17, sadly :( It has high priority
for 3.18, though.
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Description: Digital signature
On 17 July 2014 16:01, Sudeep Holla wrote:
> On 17/07/14 07:25, Jassi Brar wrote:
>>
>>>
+ u32 val;
+
+ pr_debug("%s:%d\n", __func__, __LINE__);
>>>
>>>
>>>
>>> Please remove all these debug prints.
>>>
>> These are as good as absent unless DEBUG is defined.
>>
>
> Yes,
Suravee,
On Wed, Jul 09, 2014 at 06:05:04PM -0500, suravee.suthikulpa...@amd.com wrote:
> From: Suravee Suthikulpanit
>
> This patch extend GICv2m MSI to support multiple MSI in ARM64.
>
> This requires the common arch_setup_msi_irqs() to be overwriten
> with ARM64 version which does not return
On Mon, Jul 14, 2014 at 10:59:57AM -0500, Suravee Suthikulanit wrote:
> On 7/13/2014 6:14 PM, Jason Cooper wrote:
> >Suravee,
> >
> >On Wed, Jul 09, 2014 at 06:05:00PM -0500, suravee.suthikulpa...@amd.com
> >wrote:
> >>From: Suravee Suthikulpanit
> >>
> >>This patch set introduces support for MSI
On Tue, Jul 15, 2014 at 12:03:03AM +0200, Heiko Stübner wrote:
> From: Suravee Suthikulpanit
>
> Commit 3ab72f9156bb "dt-bindings: add GIC-400 binding" added the
> "arm,gic-400" compatible string, but the corresponding IRQCHIP_DECLARE
> was never added to the gic driver.
>
> Therefore add the mi
On Tue, Jul 15, 2014 at 6:56 PM, Felipe Balbi wrote:
> Hi all,
>
> the following patches add suport for AM43xx's Video Processing
> Front End (VPFE). Full documentation is available at [1] chapter 14.
>
> This driver has been tested with linux-next from yesterday, plus my
> (already queued) am437x
On Thu, Jul 17, 2014 at 07:19:15PM +0800, Peter Chen wrote:
> Currently, we are designing a generic driver, we don't know what's the
> hardware architecture, we are trying to find a solution how to set
> dma mask for all possible devices which will use this driver, Antoine's
> this patch is trying
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