Hi!
ttha...@opensource.altera.com writes:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.
Signed-off-by: Thor Thayer ttha...@opensource.altera.com
---
v2: Changes to SoC SDRAM EDAC code.
v3:
On Thursday 14 August 2014 17:11:23 Florian Fainelli wrote:
+static void __init bcm63xx_init(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL,
+ platform_bus);
+ l2x0_of_init(0, ~0);
+}
+
+static const char * const bcm63xx_dt_compat[] = {
+
On Thursday 14 August 2014 17:11:26 Florian Fainelli wrote:
+/ {
+ compatible = brcm,BCM963138DVT, brcm,bcm63138;
+ model = Broadcom BCM963138DVT;
+
+ memory {
+ reg = 0x0 0x0800;
+ };
+
+};
+
+serial0 {
+ status = okay;
+};
+
+serial1
On Thursday 14 August 2014 17:11:25 Florian Fainelli wrote:
Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:
- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD Global
Hello Ulf,
On Thu, Aug 14, 2014 at 11:26:28AM +0200, Ulf Hansson wrote:
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 95cceae96944..52e83f389428 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -452,6 +452,14 @@ int mmc_of_parse(struct
From: Sascha Hauer s.ha...@pengutronix.de
Some eMMC and SD cards implement a DSR register that allows to tune
raise/fall times and drive strength of the CMD and DATA outputs.
The values to use depend on the card in use and the host.
It might be needed to reduce the drive strength to prevent
On Thu, Aug 14, 2014 at 04:49:59PM +0100, Liviu Dudau wrote:
On Thu, Aug 14, 2014 at 03:58:04PM +0100, Wei Yang wrote:
On Tue, Aug 12, 2014 at 05:25:15PM +0100, Liviu Dudau wrote:
Enhance the default implementation of pcibios_add_device() to
parse and map the IRQ of the device if a DT binding
On 15 August 2014 10:38, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
From: Sascha Hauer s.ha...@pengutronix.de
Some eMMC and SD cards implement a DSR register that allows to tune
raise/fall times and drive strength of the CMD and DATA outputs.
The values to use depend on the card
On Fri, Aug 15, 2014 at 09:56:32AM +0100, Wei Yang wrote:
On Thu, Aug 14, 2014 at 04:49:59PM +0100, Liviu Dudau wrote:
On Thu, Aug 14, 2014 at 03:58:04PM +0100, Wei Yang wrote:
On Tue, Aug 12, 2014 at 05:25:15PM +0100, Liviu Dudau wrote:
Enhance the default implementation of
On Tue, 12 Aug 2014 18:46:36 -0700, Stephen Boyd sb...@codeaurora.org wrote:
On 08/12/14 17:57, Stepan Moskovchenko wrote:
diff --git a/drivers/of/device.c b/drivers/of/device.c
index f685e55..3e116f6 100644
--- a/drivers/of/device.c
+++ b/drivers/of/device.c
@@ -54,7 +54,7 @@ int
On Fri, Aug 15, 2014 at 11:45 AM, Grant Likely grant.lik...@linaro.org wrote:
On Tue, 12 Aug 2014 18:46:36 -0700, Stephen Boyd sb...@codeaurora.org wrote:
On 08/12/14 17:57, Stepan Moskovchenko wrote:
diff --git a/drivers/of/device.c b/drivers/of/device.c
index f685e55..3e116f6 100644
---
On Thu, Aug 14, 2014 at 09:40:14AM +0900, Chanwoo Choi wrote:
+- regulator-initial-state: initial state for suspend state, cnd set initial
+ state among following defined suspend states:
+ 2: PM_SUSPEND_STANDBY - Setup regulator according to
regulator-state-standby
+ 3: PM_SUSPEND_MEM -
[devicetree-discuss is no more, fixing up to devicetree@vger.kernel.org]
Hi,
On Fri, Aug 15, 2014 at 10:49:12AM +0100, Bhupesh Sharma wrote:
This patch adds a devicetree binding documentation for FSL's
Management Complex.
Management Complex is a hardware resource manager that manages
On Fri, Aug 15, 2014 at 11:52 AM, Grant Likely grant.lik...@linaro.org wrote:
On Fri, Aug 15, 2014 at 11:45 AM, Grant Likely grant.lik...@linaro.org
wrote:
On Tue, 12 Aug 2014 18:46:36 -0700, Stephen Boyd sb...@codeaurora.org
wrote:
On 08/12/14 17:57, Stepan Moskovchenko wrote:
diff --git
Hi Dinh,
On Thu, Aug 14, 2014 at 10:13:34PM +0100, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
bring secondary cores online. This patch adds a /memreserve/ section to
reserve
On Thu, Aug 14, 2014 at 07:47:42AM +0100, Hiroshi Doyu wrote:
Thierry Reding thierry.red...@gmail.com writes:
+Multiple-master IOMMU:
+--
+
+ iommu {
+ /* the specifier represents the ID of the master */
+ #iommu-cells = 1;
+
Hello Nick,
On 08/08/2014 04:52 PM, Javier Martinez Canillas wrote:
On 08/07/2014 02:38 PM, Nick Dyer wrote:
I'm afraid you have misunderstood the impact of this change to the way that
the GPIOs coming in to the touch controller are mapped to key codes. Look
Unfortunately there are no
Dear Mark,
On Fri, Aug 15, 2014 at 7:56 PM, Mark Brown broo...@kernel.org wrote:
On Thu, Aug 14, 2014 at 09:40:14AM +0900, Chanwoo Choi wrote:
+- regulator-initial-state: initial state for suspend state, cnd set initial
+ state among following defined suspend states:
+ 2:
Will Deacon will.dea...@arm.com writes:
On Thu, Aug 14, 2014 at 07:47:42AM +0100, Hiroshi Doyu wrote:
Thierry Reding thierry.red...@gmail.com writes:
+Multiple-master IOMMU:
+--
+
+ iommu {
+ /* the specifier represents the ID of the master
On Wed, 6 Aug 2014 13:15:00 -0700, Brian Norris computersforpe...@gmail.com
wrote:
On Wed, Aug 06, 2014 at 01:02:27PM -0700, Florian Fainelli wrote:
In case the Device Tree blob passed by the boot agent supplies both an
'interrupts-extended' and an 'interrupts' property in order to allow for
On Wed, 06 Aug 2014 15:12:42 -0700, Florian Fainelli f.faine...@gmail.com
wrote:
On 08/06/2014 02:50 PM, Tim Bird wrote:
On Wed, Aug 6, 2014 at 1:12 PM, Brian Norris
computersforpe...@gmail.com wrote:
On Wed, Aug 06, 2014 at 01:42:08PM -0500, Rob Herring wrote:
On Wed, Aug 6, 2014 at
On Fri, Aug 15, 2014 at 01:29:41PM +0100, Hiroshi Doyu wrote:
Will Deacon will.dea...@arm.com writes:
I think there's some confusion here. The ARM architected SMMU does not
perform any StreamID translation -- it sees an incoming ID and uses that to
lookup a set of translation tables.
-Original Message-
From: Mark Rutland [mailto:mark.rutl...@arm.com]
Sent: Friday, August 15, 2014 6:00 AM
To: Sharma Bhupesh-B45370
Cc: devicetree@vger.kernel.org; Catalin Marinas; a...@arndb.de; Rivera Jose-
B46482; Will Deacon; Yoder Stuart-B08248; grant.lik...@secretlab.ca; Basu
Hi Suravee,
On Wed, Aug 13 2014 at 4:00:41 pm BST, suravee.suthikulpa...@amd.com
suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to
On Aug 15, 2014, at 6:00 AM, Mark Rutland mark.rutl...@arm.com wrote:
[devicetree-discuss is no more, fixing up to devicetree@vger.kernel.org]
Hi,
On Fri, Aug 15, 2014 at 10:49:12AM +0100, Bhupesh Sharma wrote:
This patch adds a devicetree binding documentation for FSL's
Management
Hi Mark,
On 8/15/14, 6:27 AM, Mark Rutland wrote:
Hi Dinh,
On Thu, Aug 14, 2014 at 10:13:34PM +0100, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to
bring secondary cores
Hi Suravee,
On Wed, Aug 13 2014 at 4:00:40 pm BST, suravee.suthikulpa...@amd.com
suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces
The series has been re-worked from v2 onwards to split out the ehci and ohci
parts
into their own drivers / devices like most other ARM platforms based on
feedback from Arnd Bergmann (see here
http://www.spinics.net/lists/linux-usb/msg24.html.
The ehci-platform ohci-platform have been
This patch adds the glue code required to ensure the on-chip EHCI
controller works on STi consumer electronics SoC's from STMicroelectronics.
It mainly manages the setting and enabling of the relevant clocks and manages
the reset / power signals to the IP block.
Signed-off-by: Peter Griffin
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c2066f4..89aef87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1356,6 +1356,8 @@ F:drivers/pinctrl/pinctrl-st.c
F:
This patch adds the glue code required to ensure the on-chip OHCI
controller works on STi consumer electronics SoC's from STMicroelectronics.
It mainly manages the setting and enabling of the relevant clocks and manages
the reset / power signals to the IP block.
Signed-off-by: Peter Griffin
This patch documents the device tree bindings required for
the ohci on-chip controller found in ST consumer electronics SoC's.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
Documentation/devicetree/bindings/usb/ohci-st.txt | 37 +++
1 file changed, 37
This patch documents the device tree bindings required for the
ehci on-chip controller found in ST consumer electronics SoC's.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
Documentation/devicetree/bindings/usb/ehci-st.txt | 39 +++
1 file changed, 39
Hello.
On 08/15/2014 06:03 PM, Peter Griffin wrote:
This patch documents the device tree bindings required for the
ehci on-chip controller found in ST consumer electronics SoC's.
Signed-off-by: Peter Griffin peter.grif...@linaro.org
---
Documentation/devicetree/bindings/usb/ehci-st.txt |
On 8/15/2014 8:31 AM, Marc Zyngier wrote:
Hi Suravee,
+/*
+ * ARM64 function for seting up MSI irqs.
+ * Copied from driver/pci/msi.c: arch_setup_msi_irqs().
+ */
+int arm64_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+ struct msi_desc *entry;
+ int ret;
+
+ if
On Fri, Aug 15 2014 at 3:53:25 pm BST, Suravee Suthikulanit
suravee.suthikulpa...@amd.com wrote:
On 8/15/2014 8:31 AM, Marc Zyngier wrote:
Hi Suravee,
+/*
+ * ARM64 function for seting up MSI irqs.
+ * Copied from driver/pci/msi.c: arch_setup_msi_irqs().
+ */
+int
Update version after incorporating David Miller's comment from earlier
posting [1]. I would like to get these merged for upcoming 3.18 merge
window if there are no concerns on this version.
The network coprocessor (NetCP) is a hardware accelerator that processes
Ethernet packets. NetCP has a
From: Sandeep Nair sandee...@ti.com
Signed-off-by: Sandeep Nair sandee...@ti.com
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
MAINTAINERS |6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 134483f..7b1c41d 100644
--- a/MAINTAINERS
+++
From: Sandeep Nair sandee...@ti.com
The network coprocessor (NetCP) is a hardware accelerator that processes
Ethernet packets. NetCP has a gigabit Ethernet (GbE) subsystem with a ethernet
switch sub-module to send and receive packets. NetCP also includes a packet
accelerator (PA) module to
On Thu, 14 Aug 2014, Vivek Gautam wrote:
Now that we have completely moved from older USB-PHY drivers
to newer GENERIC-PHY drivers for PHYs available with USB controllers
on Exynos series of SoCs, we can remove the support for the same
in our host drivers too.
This should fix the issue on
On Thu, 14 Aug 2014, Vivek Gautam wrote:
Now that we have completely moved from older USB-PHY drivers
to newer GENERIC-PHY drivers for PHYs available with USB controllers
on Exynos series of SoCs, we can remove the support for the same
in our host drivers too.
This should fix the issue on
-Original Message-
From: Kumar Gala [mailto:ga...@codeaurora.org]
Sent: Friday, August 15, 2014 10:26 AM
To: Basu Arnab-B45036
Cc: Mark Rutland; Sharma Bhupesh-B45370; a...@arndb.de; Catalin Marinas;
devicetree-disc...@lists.ozlabs.org; Will Deacon; Yoder Stuart-B08248;
On Aug 15, 2014, at 10:41 AM, Stuart Yoder stuart.yo...@freescale.com wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@codeaurora.org]
Sent: Friday, August 15, 2014 10:26 AM
To: Basu Arnab-B45036
Cc: Mark Rutland; Sharma Bhupesh-B45370; a...@arndb.de; Catalin Marinas;
Add the TI drv260x haptics/vibrator driver.
This device uses the input force feedback
to produce a wave form to driver an
ERM or LRA actuator device.
The initial driver supports the devices
real time playback mode. But the device
has additional wave patterns in ROM.
This functionality will be
-Original Message-
From: Kumar Gala [mailto:ga...@codeaurora.org]
Sent: Friday, August 15, 2014 10:44 AM
To: Yoder Stuart-B08248
Cc: Basu Arnab-B45036; Mark Rutland; Sharma Bhupesh-B45370; a...@arndb.de;
Catalin Marinas; Will Deacon; grant.lik...@secretlab.ca; linux-arm-
On Fri, Aug 15, 2014 at 04:49:53PM +0100, Stuart Yoder wrote:
On Aug 15, 2014, at 10:41 AM, Stuart Yoder stuart.yo...@freescale.com
wrote:
So we want to do the standard/conventional thing here that will
allow are device trees to be used in more than u-boot.
Well, I think the guys
On 15/08/14 13:01, Javier Martinez Canillas wrote:
By passing all these keycodes the touchpad worked as expected for me and the
driver did the same than the Chrome OS driver that has these keycodes
hardcoded
when is_tp is true.
at the protocol guide for T19.
I don't have access to proper
Am Montag, 11. August 2014, 11:47:29 schrieb Doug Anderson:
The PMIC interrupt pinctrl line was added to the rk3288-evb-act8846,
but it's the same line on both the ACT8846 version and the RK808
version. This makes a lot of sense since they share the same SoC
daugherboard. Move the pinctrl
On Fri, 15 Aug 2014, Steffen Trumtrar wrote:
Hi!
Hello
Thanks for the feedback...
ttha...@opensource.altera.com writes:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera
SoC project.
Signed-off-by: Thor
On 08/15/2014 10:08 AM, Nick Dyer wrote:
On 15/08/14 13:01, Javier Martinez Canillas wrote:
By passing all these keycodes the touchpad worked as expected for me and the
driver did the same than the Chrome OS driver that has these keycodes hardcoded
when is_tp is true.
at the protocol guide
Adding Greg...
On Tue, Aug 12, 2014 at 9:30 PM, Stepan Moskovchenko
step...@codeaurora.org wrote:
When we parse the device tree and allocate platform
devices, the 'name' of the newly-created platform_device
is set to point to the 'name' field of the 'struct device'
embedded within the
On 08/15/2014 11:07 AM, atull wrote:
On Fri, 15 Aug 2014, Steffen Trumtrar wrote:
Hi!
Hello
Thanks for the feedback...
ttha...@opensource.altera.com writes:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
On Fri, Aug 15, 2014 at 11:07:31AM -0500, atull wrote:
On Fri, 15 Aug 2014, Steffen Trumtrar wrote:
Hi!
Hello
Thanks for the feedback...
ttha...@opensource.altera.com writes:
From: Thor Thayer ttha...@opensource.altera.com
Add the Altera SDRAM EDAC bindings and
On Fri, Aug 15, 2014 at 11:47:09AM -0500, Thor Thayer wrote:
Hi Steffen!
Building on Alan's points, I don't see the reference to the child
nodes in the syscon.txt binding documentation - can you point out
what I'm missing?
I based this patch on other examples of syscon, and there aren't
On Wed, Aug 13, 2014 at 04:52:01PM +0100, Lorenzo Pieralisi wrote:
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the
+Stephen
On 14 August 2014 22:02, Simon Glass s...@chromium.org wrote:
(correct list)
On 14 August 2014 21:42, Simon Glass s...@chromium.org wrote:
Hi,
In U-Boot we currently specify the console device (typically serial)
using something like:
aliases {
console = /serial@1234;
}
On Wed, Aug 13, 2014 at 06:22:32PM +0100, Mitchel Humpherys wrote:
On Tue, Aug 12 2014 at 05:51:33 PM, Mitchel Humpherys
mitch...@codeaurora.org wrote:
This series is based on on Will's iommu/pci branch.
Incredibly, I also neglected to base this on top of Olav's recent patch
+Even more people (thanks Stephen)
On 15 August 2014 11:22, Simon Glass s...@chromium.org wrote:
+Stephen
On 14 August 2014 22:02, Simon Glass s...@chromium.org wrote:
(correct list)
On 14 August 2014 21:42, Simon Glass s...@chromium.org wrote:
Hi,
In U-Boot we currently specify the
Cc: devicetree@vger.kernel.org
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
arch/arm/boot/dts/dra7.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 10066f4..a904561 100644
---
Cc: devicetree@vger.kernel.org
Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
arch/arm/boot/dts/am33xx.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 4a4e02d..cdccbd6 100644
---
Hello Ulf,
On Fri, Aug 15, 2014 at 11:05:39AM +0200, Ulf Hansson wrote:
On 15 August 2014 10:38, Uwe Kleine-König
u.kleine-koe...@pengutronix.de wrote:
From: Sascha Hauer s.ha...@pengutronix.de
Some eMMC and SD cards implement a DSR register that allows to tune
raise/fall times and
On Thursday, August 14, 2014 6:37pm, Bjorn Andersson bj...@kryo.se said:
On Thu, Aug 14, 2014 at 12:20 AM, Kiran Padwal
kiran.pad...@smartplayin.com wrote:
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi
b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 92bf793..fbebf5c 100644
---
Add a new device tree binding cpu-return-addr. This binding is required for
all ARM v8 CPUs that have an enable-method property value of spin-table. The
value is a 64 bit read-only physical address that secondary CPU execution will
transfer to upon CPU shutdown.
Signed-off-by: Geoff Levand
Add entries for the new device tree property cpu-return-addr to the
existing arm64 dts files.
Signed-off-by: Geoff Levand ge...@infradead.org
---
Just FYI.
arch/arm64/boot/dts/apm-storm.dtsi | 8
arch/arm64/boot/dts/foundation-v8.dts | 4
On Tue, Jul 22, 2014 at 07:16:15PM +0200, Stephen Warren wrote:
On 07/15/2014 09:24 AM, Peter De Schrijver wrote:
Just continue initializing clocks if there's an error on one of them. This
is useful if there's a mistake in the inittable, because the system could
hang if clk_disable_unused()
On Fri, Aug 15, 2014 at 11:38:33AM -0500, Rob Herring wrote:
Adding Greg...
On Tue, Aug 12, 2014 at 9:30 PM, Stepan Moskovchenko
step...@codeaurora.org wrote:
When we parse the device tree and allocate platform
devices, the 'name' of the newly-created platform_device
is set to point to
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