Hi Daniel,
On Tue, Aug 19, 2014 at 3:26 PM, Daniel Mack wrote:
> Hi,
>
> On 07/22/2014 11:08 AM, Subbaraya Sundeep Bhatta wrote:
>> This patch adds xilinx usb2 device driver support
>
> Add some more information here, please. Copying the text from the
> Kconfig option is already a good start.
>
>
On Wed, Aug 20, 2014 at 02:29:17PM -0500, Dmitry Torokhov wrote:
> On August 20, 2014 1:54:11 PM CDT, Doug Anderson
> wrote:
> >On Wed, Aug 20, 2014 at 3:04 AM, Thierry Reding
> > wrote:
> >> On Tue, Aug 19, 2014 at 09:07:54AM -0700, Doug Anderson wrote:
> >>> The rk3288 has the ability to invert
Hello Viresh,
Am 21.08.2014 06:26, schrieb Viresh Kumar:
On Thu, Aug 21, 2014 at 2:00 AM, Stephen Warren wrote:
On 08/20/2014 02:02 PM, Andreas Färber wrote:
Am 20.08.2014 17:39, schrieb Javier Martinez Canillas:
If this not the correct workflow and you have a better way to manage
this, I wo
On Mon 11 Aug 08:40 PDT 2014, Ivan T. Ivanov wrote:
> From: "Ivan T. Ivanov"
>
> This is the pinctrl, pinmux, pinconf and gpiolib driver for the
> Qualcomm GPIO and MPP sub-function blocks found in the PMIC chips.
>
Hi Ivan,
I'm not very fond of the mixing of gpio and mpp in the same driver,
This patch adds a function to get the MACIDs from the am33xx SoC
control module registers which hold unique vendor MACIDs. This is only
used if of_get_mac_address() fails to get a valid mac address.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
Tested-by: Steven Rostedt
---
Document
"MII_BUS_ID_SIZE" is defined in linux/phy.h which is not included in the
cpsw.h file.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
drivers/net/ethernet/ti/cpsw.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
i
This series adds support to the cpsw driver to read the MACIDs of the am335x
chip and use them as fallback. These addresses are only used if there are no
mac addresses in the devicetree, for example set by a bootloader.
In v4 I removed an unused Makefile rule which was introduced by me when this
s
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
arch/arm/boot/dts/am33xx.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 3a0a161342ba..25e38b6ac376 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch
ret is set 0 at this point, so jumping to that error label would result
in a return value of 0. Set ret to -ENOMEM to return a proper error
value.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
drivers/net/ethernet/ti/cpsw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/driv
Use dev_err instead of pr_err.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
drivers/net/ethernet/ti/cpsw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index f09b4639ad31..0bc2c2a2c236 100644
mac-address is an optional property. If no mac-address is set, a random
mac-address will be generated.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
Documentation/devicetree/bindings/net/cpsw.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/de
There are 2 MACIDs stored in the control module of the am33xx. These are
read by the cpsw driver if no valid MACID was found in the devicetree.
Signed-off-by: Markus Pargmann
Reviewed-by: Wolfram Sang
---
arch/arm/boot/dts/am33xx.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm
On 21 August 2014 02:34, Tuomas Tynkkynen wrote:
> Add a new cpufreq driver for Tegra124. Instead of using the PLLX as
> the CPU clocksource, switch immediately to the DFLL. It allows the use
> of higher clock rates, and will automatically scale the CPU voltage as
> well. Besides the CPU clocksour
Hi Felipe,
On Wed, Aug 20, 2014 at 11:44 PM, Felipe Balbi wrote:
> Hi,
>
> On Thu, Aug 14, 2014 at 07:53:53PM +0530, Vivek Gautam wrote:
>> - This series is based on 'usb-next' branch.
>>
>> Now that we have support for USB PHY controllers for Exynos SoC series,
>> we are free to remove the olde
On Thu, Aug 21, 2014 at 2:00 AM, Stephen Warren wrote:
> On 08/20/2014 02:02 PM, Andreas Färber wrote:
>> Am 20.08.2014 17:39, schrieb Javier Martinez Canillas:
>>> If this not the correct workflow and you have a better way to manage
>>> this, I would love to know about it.
Oh yes, this was certa
Dear Eduardo,
On 08/20/2014 10:38 PM, edubez...@gmail.com wrote:
> Hello Chanwoo,
>
> On Tue, Aug 19, 2014 at 7:52 PM, Chanwoo Choi wrote:
>> This patch add support for TRIM_RELOAD feature at Exynos3250. The TMU of
>> Exynos3250 has two TRIMINFO_CON register.
>
> Can you please split the two ch
On 08/20/2014 10:41 PM, Soren Brinkmann wrote:
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann
---
Hi Mikhail,
Thank you for the patch.
On Tuesday 19 August 2014 16:50:51 Mikhail Ulyanov wrote:
A commit message would be nice.
> Signed-off-by: Mikhail Ulyanov
Acked-by: Laurent Pinchart
> ---
> arch/arm/boot/dts/r8a7791.dtsi| 6 +++---
> include/dt-bindings/clock/r8a7791-clock
Hi Mikhail,
Thank you for the patch.
On Tuesday 19 August 2014 16:50:49 Mikhail Ulyanov wrote:
A commit message would be nice.
> Signed-off-by: Mikhail Ulyanov
Acked-by: Laurent Pinchart
> ---
> arch/arm/boot/dts/r8a7790.dtsi| 6 +++---
> include/dt-bindings/clock/r8a7790-clock
On Mon 11 Aug 08:40 PDT 2014, Ivan T. Ivanov wrote:
> diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard-pmics-pins.dtsi
> b/arch/arm/boot/dts/qcom-apq8074-dragonboard-pmics-pins.dtsi
[...]
> +
> +&pm8941_gpios {
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pm8941_gpios_defaul
Hi Mikhail,
Thank you for the patch.
On Tuesday 19 August 2014 16:50:53 Mikhail Ulyanov wrote:
> Signed-off-by: Mikhail Ulyanov
> ---
> .../devicetree/bindings/media/renesas,jpu.txt | 23 +++
> 1 file changed, 23 insertions(+)
> create mode 100644 Documentation/devicetree/
On Mon 11 Aug 08:40 PDT 2014, Ivan T. Ivanov wrote:
[...]
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
> b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
[...]
> +SUBNODES:
[...]
> +- function:
> + Usage: required
> + Value type:
> + Defini
On Wed, Aug 20, 2014 at 2:28 PM, Bjorn Andersson
wrote:
> On Wed 20 Aug 01:06 PDT 2014, Srinivas Kandagatla wrote:
>> 2> Looking back at v3.4 kernel, for gpio modes, BIT(0) of bank 0 is set
>> to enable gpio mode. without this bit driver does not work for output pins.
>>
>
> Thanks, I missed that.
On Mon 18 Aug 00:16 PDT 2014, Ivan T. Ivanov wrote:
> On Sat, 2014-08-16 at 16:24 +0100, Daniel wrote:
> > @Ivan: sorry about the double post.
> >
> > Am 11.08.2014 um 16:40 schrieb Ivan T. Ivanov :
[...]
> > > +#define PMIC_GPIO_PULL_UP_30 1
> > > +#define PMIC_GPIO_PULL_UP_1P5
Chris,
On Tue, Aug 19, 2014 at 8:40 PM, Chris Zhong wrote:
> Signed-off-by: Chris Zhong
>
> ---
>
> Changes in v2: None
>
> drivers/clk/Kconfig |9 +++
> drivers/clk/Makefile|1 +
> drivers/clk/clk-rk808.c | 146
> +++
> 3 files chan
Chris,
On Tue, Aug 19, 2014 at 8:31 PM, Chris Zhong wrote:
> The RK808 chip is a power management IC for multimedia and handheld
> devices. It contains the following components:
>
> - Regulators
> - RTC
>
> The rk808 core driver is registered as a platform driver and provides
> communication thro
On Wed 20 Aug 01:06 PDT 2014, Srinivas Kandagatla wrote:
> Hi Bjorn,
>
Hi Srinivas,
Thanks for the testing. I'm reworking the driver to incorporate yours, Linus'
and Ivans feedback.
> Two things which I noticed while trying out this driver to drive a reset
> line.
>
> 1> gpio numbering for pi
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124 SoCs. The
DFLL is the intended primary clock source for the fast CPU cluster.
This code is very closely based on a patch by Paul Walmsley from
December (http://comments.gmane.o
With closed loop support, the clock rate of the DFLL can be adjusted.
The oscillator itself in the DFLL is a free-running oscillator whose
rate is directly determined the supply voltage. However, the DFLL
module contains logic to compare the DFLL output rate to a fixed
reference clock (51 MHz) and
Tegra CVB tables encode the relationship between operating voltage
and optimal frequency as a function of the so-called speedo value.
The speedo value is written to the on-chip fuses at the factory,
which allows the voltage-frequency operating points to be calculated
on an per-chip basis.
Add util
From: Paul Walmsley
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP bl
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well. The DFLL
is a separate IP block from the usual Tegra124 clock-and-reset
controller, so it gets its own node in the device tree.
Signed-off-by: Tuomas Tynkkynen
---
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 8 +++-
1 file changed, 7 insertions(+), 1 delet
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen
---
arch/arm/boot/dts/tegra124.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegr
Add the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen
---
v3: New patch
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
ind
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen
---
drivers/clk/tegra/clk-tegra-super-gen4.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-g
Save and restore this register since the LP1 restore assembly routines
fiddle with it. Otherwise the CPU would keep running on PLLX after
resume from suspend even when DFLL was the original clocksource.
Signed-off-by: Tuomas Tynkkynen
---
drivers/clk/tegra/clk-tegra124.c | 14 ++
1 f
Add basic platform driver support for the fast CPU cluster DFLL
clocksource found on Tegra124 SoCs. This small driver selects the
appropriate Tegra124-specific characterization data and integration
code. It relies on the DFLL common code to do most of the work.
Signed-off-by: Tuomas Tynkkynen
---
Add a new cpufreq driver for Tegra124. Instead of using the PLLX as
the CPU clocksource, switch immediately to the DFLL. It allows the use
of higher clock rates, and will automatically scale the CPU voltage as
well. Besides the CPU clocksource switch, we let the cpufreq-cpu0 driver
for all the cpuf
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen
---
arch/arm/boot/dts/tegra124.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124.d
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen
---
v3: vdd-cpu-supply property added
---
.../bindings/cpufreq/tegra124-cpufreq.txt | 44 +
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen
---
v3: New patch
---
drivers/cpufreq/Kconfig.arm| 6 +++---
drivers/cpufreq/Makefile
The Tegra124 cpufreq driver depends on CONFIG_GENERIC_CPUFREQ_CPU0, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen
---
v4: New patch
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/tegra_defconfi
v4 changes:
DFLL:
- fix wrong register accessors used for the DFLL_OUTPUT_CFG register
- I decided to leave the dfll_i2c_{readl,writel} separate since the
correct barrier function still needs to be called
- fix PMIC I2C voltage register address being uninitialized
cpufreq:
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1: 2f3edfd7e27ad4206acbc2ae99c9df5f46353024)
Signed-off-by: Soren Brink
The DDR controller can detect idle periods and leverage low power
features like self-refresh and clock stop.
When new requests occur, the DDRC resumes normal operation.
Signed-off-by: Soren Brinkmann
---
arch/arm/mach-zynq/Makefile | 2 +-
arch/arm/mach-zynq/common.c | 1 +
arch/arm/mach-zynq/
From: Daniel Lezcano
The core is not powered down, it is pointless to call the cpu_pm notifiers and
switch to the global timer.
Signed-off-by: Daniel Lezcano
Reviewed-and-tested-by: Soren Brinkmann
---
drivers/cpuidle/cpuidle-zynq.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions
Add the DDR controller to the Zynq devicetree.
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts/zynq-7000.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6cc83d4c6c76..587cadcf7001 100644
--- a/arch/arm/b
Signed-off-by: Soren Brinkmann
---
.../devicetree/bindings/memory-controllers/synopsys.txt | 11 +++
1 file changed, 11 insertions(+)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/synopsys.txt
diff --git a/Documentation/devicetree/bindings/memory-control
Hi,
I'm working on some PM-related updates and suspend for Zynq (for the
interested, a branch with all patches is found here:
https://github.com/sorenb-xlnx/linux-xlnx/commits/suspend).
This series consists of the rather unproblematic parts that affect Zynq
only and have no further dependencies.
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann
---
arch/arm/mach-zynq/Makefile | 1 -
arch/arm/mach
Match the naming pattern of all other SMP ops and rename
zynq_platform_cpu_die --> zynq_cpu_die.
Signed-off-by: Soren Brinkmann
---
arch/arm/mach-zynq/platsmp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
ind
From: Daniel Lezcano
As there is no Power management unit on this board, it is not possible to power
down a core, just WFI is allowed. There is no point to invalidate the cache and
exit coherency.
Signed-off-by: Daniel Lezcano
Reviewed-and-tested-by: Soren Brinkmann
---
arch/arm/mach-zynq/hot
Signed-off-by: Soren Brinkmann
---
arch/arm/mach-zynq/common.c | 6 ++
arch/arm/mach-zynq/common.h | 11 +++
arch/arm/mach-zynq/platsmp.c | 9 +
3 files changed, 26 insertions(+)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 31a6fa40ba37..3c
On Tue, Aug 19, 2014 at 08:22:14PM +0300, Georgi Djakov wrote:
> This patch adds support for the TLMM (Top-Level Mode Mux) block found
> in the APQ8084 platform.
Comment in-line
> + PINCTRL_PIN(134, "GPIO_134"),
> + PINCTRL_PIN(135, "GPIO_135"),
> + PINCTRL_PIN(136, "GPIO_136"),
> +
On 20.08.14 18:42, Andy Gross wrote:
> On Tue, Aug 19, 2014 at 09:39:30PM -0700, Bjorn Andersson wrote:
>> On Tue 19 Aug 10:22 PDT 2014, Georgi Djakov wrote:
>>
>>> This patch adds support for the TLMM (Top-Level Mode Mux) block found
>>> in the APQ8084 platform.
>>>
>> [...]
>>> +
>>> +#define NUM
On 08/20/2014 02:02 PM, Andreas Färber wrote:
Hi Javier,
Am 20.08.2014 17:39, schrieb Javier Martinez Canillas:
As you already know when you apply a patch with git am, everything
that is between a line with 3 dashes line (---) and the actual diff is
omitted since that is where the generated dif
Hi Javier,
Am 20.08.2014 17:39, schrieb Javier Martinez Canillas:
> As you already know when you apply a patch with git am, everything
> that is between a line with 3 dashes line (---) and the actual diff is
> omitted since that is where the generated diffstat is placed by git
> format-patch.
>
>
Dmitry,
On Wed, Aug 20, 2014 at 12:29 PM, Dmitry Torokhov
wrote:
> On August 20, 2014 1:54:11 PM CDT, Doug Anderson
> wrote:
>>On Wed, Aug 20, 2014 at 3:04 AM, Thierry Reding
>> wrote:
>>> On Tue, Aug 19, 2014 at 09:07:54AM -0700, Doug Anderson wrote:
The rk3288 has the ability to invert
>
On August 20, 2014 1:54:11 PM CDT, Doug Anderson wrote:
>On Wed, Aug 20, 2014 at 3:04 AM, Thierry Reding
> wrote:
>> On Tue, Aug 19, 2014 at 09:07:54AM -0700, Doug Anderson wrote:
>>> The rk3288 has the ability to invert
>>> + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
>>> +
>
Add the core device nodes for the SARADC found on both the Cortex-A9 series
(rk3066 and rk3188) as well as the newer rk3288.
Signed-off-by: Heiko Stuebner
---
if nobody complains I'll queue this into my v3.18-next/dts branch
arch/arm/boot/dts/rk3288.dtsi | 10 ++
arch/arm/boot/dts/rk3xx
The Radxa Rock uses a hym8563 as rtc. Add the i2c device and necessary
pinconfig for the interrupt pin - labeled rtc_int in the schematics.
Signed-off-by: Heiko Stuebner
---
if nobody complains I'll queue this into my v3.18-next/dts branch
arch/arm/boot/dts/rk3188-radxarock.dts | 17 +++
Thierry,
On Wed, Aug 20, 2014 at 3:04 AM, Thierry Reding
wrote:
> On Tue, Aug 19, 2014 at 09:07:54AM -0700, Doug Anderson wrote:
>> The rk3288 has the ability to invert the polarity of the PWM. Let's
>> enable that ability.
>>
>> To do this we increase the number of pwm_cells to 3 to allow using
PWM0 is the PWM associated with the LCD backlight. Enable it.
Signed-off-by: Doug Anderson
---
Changes in v4: None
Changes in v3:
- Fix space to tab in 2 places in DTS.
- Make sure PWM is upper case in prose.
Changes in v2: None
arch/arm/boot/dts/rk3288-evb.dtsi | 53 +
The rk3288 SoC has an option to switch all of the PWMs in the system
between the old IP block and the new IP block. The rk3288 PWM driver
is written for the new block, so make sure that we enable the new
block in the GRF (general register file) when the PWM driver probes.
We emulate the solution
This adds the PWM info (other than the VOP PWM) to the main rk3288
dtsi file.
Signed-off-by: Caesar Wang
Signed-off-by: Doug Anderson
---
Changes in v4:
- Add rockchip,grf to pwm nodes.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 72
These patches enable the PWM backlight for the rk3288-evb board.
There were tested by watching the backlight grow from off to max with
the following instructions:
cd /sys/class/backlight/backlight*/
for i in $(seq 255); do echo $i > brightness; sleep .01; done
The first patch switches PWM cel
The rk3288 has the ability to invert the polarity of the PWM. Let's
enable that ability. Note that this increases pwm_cells to 3 for
rk3288.
Signed-off-by: Doug Anderson
---
Changes in v4:
- Updated comment not to add caveats about pwm_cells 3.
- rockchip_pwm_set_polarity() is now static.
- Sep
On Wed, Jul 23, 2014 at 03:33:23PM +0100, Peter Griffin wrote:
> > > > > + reset_control_assert(dwc3_data->rstc_pwrdn);
> > > > > +
> > > > > + pinctrl_pm_select_sleep_state(dev);
> >
> > pinctrl will select sleep and default states automatically for you.
>
> I've left this in v3, as grep
Hi,
On Thu, Aug 14, 2014 at 07:53:53PM +0530, Vivek Gautam wrote:
> - This series is based on 'usb-next' branch.
>
> Now that we have support for USB PHY controllers for Exynos SoC series,
> we are free to remove the older usb-phy support.
> In the process, we are removing the entire phy-samsung-
Hi,
On Wed, Jul 30, 2014 at 04:28:09PM +0100, Peter Griffin wrote:
> This patch adds the ST glue logic to manage the DWC3 HC
> on STiH407 SoC family. It manages the powerdown signal,
> and configures the internal glue logic and syscfg registers.
>
> Signed-off-by: Giuseppe Cavallaro
> Signed-off
On Tuesday 19 August 2014 07:42 AM, Brian Norris wrote:
On Wed, Aug 06, 2014 at 02:32:18AM +0530, pe...@pek-sem.com wrote:
On Tuesday 05 August 2014 07:53 PM, Lee Jones wrote:
On Thu, 03 Jul 2014, Gupta, Pekon wrote:
+ /* Load last page of block */
+ offs = (loff_t)block << chip->p
On Wed, Jul 30, 2014 at 04:28:10PM +0100, Peter Griffin wrote:
> This patch documents the device tree documentation required for
> the ST usb3 controller glue layer found in STiH407 devices.
>
> Signed-off-by: Giuseppe Cavallaro
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> Docu
On Wed, Jul 30, 2014 at 04:28:11PM +0100, Peter Griffin wrote:
-ENOLOG
> Signed-off-by: Peter Griffin
> Acked-by: Lee Jones
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 702ca10..269ad3b 100644
> --- a/MAINTAINERS
> +++ b/MAINTA
On Wed, Aug 20, 2014 at 2:25 PM, Simon Glass wrote:
> Yes, I see that, but linux doesn't use it AFAICT. Are you suggesting
> that U-Boot should? Or should we use 'u-boot,stdout-path' in /chosen?
> See my question immediately above about /chosen.
Linux use stdout-path property specified, without
Hi Sascha,
On 18 August 2014 13:19, Sascha Hauer wrote:
>
> Simon,
>
> On Thu, Aug 14, 2014 at 10:02:10PM -0600, Simon Glass wrote:
>> (correct list)
>>
>> On 14 August 2014 21:42, Simon Glass wrote:
>> > Hi,
>> >
>> > In U-Boot we currently specify the console device (typically serial)
>> > usi
From: Pratik Patel
Coresight IP blocks allow for the support of HW assisted tracing
on ARM SoCs. Bindings for the currently available blocks are
presented herein.
Signed-off-by: Pratik Patel
Signed-off-by: Panchaxari Prasannamurthy
Signed-off-by: Mathieu Poirier
---
.../devicetree/bindings/
On Wed, Aug 20, 2014 at 11:36:42AM +0800, Chris Zhong wrote:
> The regulator module consists of 4 DCDCs, 8 LDOs and 2 switches.
> The output voltages are configurable and are meant to supply power
> to the main processor and other components
Applied, thanks.
signature.asc
Description: Digital si
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So, renamed
On Wed, Aug 20, 2014 at 08:40:28AM +0200, Frans Klaver wrote:
> On Tue, Aug 19, 2014 at 01:57:02PM -0500, Felipe Balbi wrote:
> > On Tue, Aug 19, 2014 at 02:14:47PM +0200, Frans Klaver wrote:
> > > At 3.6Mbaud, with slightly over 2Mbit/s data coming in, we see 1600 uart
> > > rx buffer overflows wi
Am 20.08.2014 17:56, schrieb Soren Brinkmann:
> Move the GEM's size and address cells properties to the common
> dtsi file.
>
> Cc: Andreas Färber
> Signed-off-by: Soren Brinkmann
> ---
> arch/arm/boot/dts/zynq-7000.dtsi | 4
> arch/arm/boot/dts/zynq-parallella.dts | 2 --
> 2 files c
On Thu, 17 Jul 2014, Wolfram Sang wrote:
> On Thu, Jul 17, 2014 at 11:23:42AM +0100, Lee Jones wrote:
> > Hi Wolfram,
> >
> > Are you going to take a look at this set?
>
> Sure thing, yet I won't make it for 3.17, sadly :( It has high priority
> for 3.18, though.
Do you want me to re-send now t
Move the GEM's size and address cells properties to the common
dtsi file.
Cc: Andreas Färber
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts/zynq-7000.dtsi | 4
arch/arm/boot/dts/zynq-parallella.dts | 2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/b
Add missing Ethernet phys to Zynq DTs.
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts/zynq-zc702.dts | 6 ++
arch/arm/boot/dts/zynq-zc706.dts | 6 ++
arch/arm/boot/dts/zynq-zed.dts | 6 ++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch
The used PHYs should be qualified as 'rgmii-id' instead of just 'rgmii'.
For the Zed board this seems to make a difference between working and
broken Ethernet.
Signed-off-by: Soren Brinkmann
---
arch/arm/boot/dts/zynq-zc702.dts | 2 +-
arch/arm/boot/dts/zynq-zc706.dts | 2 +-
arch/arm/boot/dts/z
On Sat, 16 Aug 2014, Mika Westerberg wrote:
> If an MFD device is backed by ACPI namespace, we should allow subdevice
> drivers to access their corresponding ACPI companion devices through normal
> means (e.g using ACPI_COMPANION()).
>
> This patch adds such support to the MFD core. If the MFD par
On Tue, Aug 19, 2014 at 09:39:30PM -0700, Bjorn Andersson wrote:
> On Tue 19 Aug 10:22 PDT 2014, Georgi Djakov wrote:
>
> > This patch adds support for the TLMM (Top-Level Mode Mux) block found
> > in the APQ8084 platform.
> >
> [...]
> > +
> > +#define NUM_GPIO_PINGROUPS 143
> > +
>
> I think t
Hello Viresh,
On Wed, Aug 20, 2014 at 8:39 AM, Viresh Kumar wrote:
> On 20 August 2014 01:14, Tuomas Tynkkynen wrote:
>> There's actually a (mis-?)feature in git format-patch: a literal '---'
>> line in a commit message won't be escaped, so the patch notes can be
>> written in the commit message
Hi,
Am 20.08.2014 14:02, schrieb Kiran Padwal:
> This patch adds pinmux and i2c pinctrl DT node for IFC6410 board.
> It also adds necessary DT support for i2c eeprom which is present on
> IFC6410.
>
> Tested on IFC6410 board.
>
> Signed-off-by: Kiran Padwal
> ---
> Chages since v1:
> - Re
On Wed, Aug 20, 2014 at 11:47:42AM +0800, Addy Ke wrote:
> Signed-off-by: Addy Ke
Applied, thanks.
signature.asc
Description: Digital signature
On Wed, Aug 20, 2014 at 11:27:28AM +0800, Chris Zhong wrote:
> +- regulators: This is the list of child nodes that specify the regulator
> + initialization data for defined regulators. Not all regulators for the
> given
> + device need to be present. The definition for each of these nodes is
>
On Wed, 20 Aug 2014, atull wrote:
>
>
> On Wed, 20 Aug 2014, Romain Baeriswyl wrote:
>
> > From: Romain Baeriswyl
> >
> > Some legacy devices support ony I2C standard mode at 100kHz.
> > This patch allows to select the standard mode through the DTS
> > with the use of the existing clock-frequ
On Wed, 20 Aug 2014, Romain Baeriswyl wrote:
> Hi Alan,
>
> We got board issue using I2C and they were solved by changing the i2c timing.
>
> It is possible to change the tLOW and tHIGH period with the following
> parameters:
> i2c-sda-hold-time-ns
> i2c-sda-falling-time-ns
> i2c-scl-fa
If a memory block is not aligned to PAGE_SIZE, its base address must be
rounded up, not down, and its size must be reduced.
Signed-off-by: Geert Uytterhoeven
---
drivers/of/fdt.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index f4
Hi,
On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote:
> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
> or USB3 devices.
>
> Signed-off-by: alexandre torgue
> Signed-off-by: Giuseppe Cavallaro
> Signed-off-by: Gabriel Fernandez
> ---
> drivers/phy/Kconfig
On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote:
> The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
> or USB3 devices.
>
> Signed-off-by: alexandre torgue
> Signed-off-by: Giuseppe Cavallaro
> Signed-off-by: Gabriel Fernandez
> ---
> .../devicetree/bindings/p
Hi,
On Wednesday 13 August 2014 09:04 PM, Gabriel FERNANDEZ wrote:
> This provides the shared header file which will be reference from both
> the MiPHY28lp driver and its associated Device Tree node(s).
>
> Signed-off-by: alexandre torgue
> Signed-off-by: Gabriel Fernandez
> ---
> include/dt-b
On Wed, Aug 20, 2014 at 11:32 PM, Geert Uytterhoeven
wrote:
> On Wed, Aug 20, 2014 at 4:28 PM, Geert Uytterhoeven
> wrote:
>> This series cleans up interrupt-parent use, to match common use.
>> It makes sure there's an "interrupt-parent = <&gic>;" at the top, which is
>> thus inherited by all chi
Hi,
On Wednesday 23 July 2014 12:57 AM, Sergei Shtylyov wrote:
.
.
.
.
> Index: linux-phy/drivers/phy/phy-rcar-gen2.c
> ===
> --- /dev/null
> +++ linux-phy/drivers/phy/phy-rcar-gen2.c
> @@ -0,0 +1,341 @@
> +/*
> + * Renesas R-Car Ge
Hi Jacek,
On Thu, Aug 14, 2014 at 10:25:28AM +0200, Jacek Anaszewski wrote:
> On 08/14/2014 06:34 AM, Sakari Ailus wrote:
> >Hi Jacek,
> >
> >On Mon, Aug 11, 2014 at 03:27:22PM +0200, Jacek Anaszewski wrote:
> >
> >...
> >
> >>diff --git a/include/media/v4l2-flash.h b/include/media/v4l2-flash.
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