- irq_set_chained_handler(irq, dwapb_irq_handler);
- irq_set_handler_data(irq, gpio);
+ if (!pp-irq_shared) {
+ irq_set_chained_handler(pp-irq, dwapb_irq_handler);
+ irq_set_handler_data(pp-irq, gpio);
+ } else {
+ /*
+ * Request a shared
Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-factors.c | 3 +++
drivers/clk/sunxi/clk-factors.h | 1 +
2
Hi everyone,
This series unifies the mux and divider parts of the AHB1 clock found
on sun6i and sun8i, while also adding support for the pre-divider on
the PLL6 input.
The rate calculation logic must factor in which parent it is using to
calculate the rate, to decide whether to use the
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi
The sun6i DMA controller requires the AHB1 bus clock to be
clocked from PLL6. This was originally done by the dmaengine
driver during probe time. The AHB1 clock driver has since been
unified, so the original code does not work.
Remove the clk muxing code, and replace it with DT clk default
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
The N factor for PLL6 counts from 1 to 32, as specified in the A23
manual, and shown in Allwinner's original A31 code.
Also the PLL6 factors alone calculate the clock rate for PLL6x2, not
the normal halved output for PLL6. This is what the factors clk
.recalc_rate callback expects.
This patch
The DMA controller requires AHB1 bus clock to be clocked from PLL6.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 8eb2c6d..1117989
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
Hi Greg,
(Ccing mvebu guys, full discussion here:
http://www.spinics.net/lists/devicetree/msg47806.html)
On 05 Sep 11:11 PM, Greg Ungerer wrote:
On 05/09/14 17:36, Geert Uytterhoeven wrote:
No, the other way around (from most-specific to least-specific):
compatible =
Hello,
On Sat, 6 Sep 2014 09:06:00 -0300, Ezequiel Garcia wrote:
Confirmed. Judging from the specs, seems the same SPI IP is on all the
Armada SoCs; you can do the 'armada-spi' compatible addition on 375 and 38x.
However, I believe a compatible string like armada-370-spi should be
used
On Fri, Sep 05, 2014 at 11:05:37AM +0200, Anders Berg wrote:
Well, the problem with adding this to the spi-pl022 driver (as a
vendor specific extension) is that this IP block unfortunately isn't
distinguishable from the standard ARM PL022 implementation (same
values in the PrimeCell
On Fri, Sep 5, 2014 at 6:25 PM, Tanmay Inamdar tinam...@apm.com wrote:
This patch adds support for AppliedMicro X-Gene PCIe host controller. The
driver is tested on X-Gene platform with different gen1/2/3 PCIe endpoint
cards.
X-Gene PCIe controller driver has depedency on the pcie arm64 arch
On Fri, Sep 05, 2014 at 05:21:56PM +0300, Grygorii Strashko wrote:
I think we have some misunderstanding here :(
1) All new properties a optional and should be specified for SPI Slave devices
2) Seems we are talking using different terms:
- you referring to the term transfers - sequence of
On Fri, Sep 05, 2014 at 10:55:07AM +0900, Gyungoh Yoo wrote:
On Mon, Sep 01, 2014 at 11:31:58AM +0100, Mark Brown wrote:
Why is this a good idea - can this driver be used for anything other
than a sky81452?
Yes. There is a possibility that this driver will be used by similar
device with
Hello Ceasar,
On Wed, Sep 03, 2014 at 10:10:36AM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing to register for direct control.
Automaic mode
Hi Olof,
Sorry for the late reply.
On 08/28/2014 12:01 AM, Olof Johansson wrote:
On Thu, Aug 14, 2014 at 2:46 AM, Daniel Mack zon...@gmail.com wrote:
The vendor prefix was renamed from mrvl to marvell. Follow this
change in the dts file.
Signed-off-by: Daniel Mack zon...@gmail.com
---
Hello Geert,
On Thu, Aug 28, 2014 at 10:12:32AM +0200, Geert Uytterhoeven wrote:
- r8a7792 (R-Car V2H)
- r8a7793 (R-Car M2-N)
- r8a7794 (R-Car E2)
r8a7791 is now called R-Car M2-W.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
I don't have any concerns on this patch
From: Evgeny Boger bo...@contactless.ru
Add option to use with watchdog timers which are always enabled
in hardware, i.e. there is no way to enable/disable it via GPIO pin.
The driver will start pinging WDT immediately upon loading
and will continue to do so even after stopping the watchdog.
Hi all,
This series introduces a bit of clean-up (reduce magic numbers) and
new features for the VT8500 serial driver.
Firstly, in a new generation of WonderMedia SoC's the UART module
changed slightly, and now requires one more bit to be set in its
line control register to function properly.
Current code relies on the UART clock pre-divisor to be already
configured in the baud rate register. Calculate it in the driver
and set explicitly instead, also return the real effective baud
rate, which is generally slightly different from the requested value.
While at this, also ensure that
This adds simple polling functions for single-character transmit
and receive, as used by kgdb.
Signed-off-by: Alexey Charkov alch...@gmail.com
---
drivers/tty/serial/vt8500_serial.c | 31 +++
1 file changed, 31 insertions(+)
diff --git
Signed-off-by: Alexey Charkov alch...@gmail.com
---
drivers/tty/serial/vt8500_serial.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/tty/serial/vt8500_serial.c
b/drivers/tty/serial/vt8500_serial.c
index f225719..47e74f9 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++
Hi Eduardo,
On Sat, Sep 6, 2014 at 6:13 PM, Eduardo Valentin edubez...@gmail.com wrote:
On Thu, Aug 28, 2014 at 10:12:32AM +0200, Geert Uytterhoeven wrote:
- r8a7792 (R-Car V2H)
- r8a7793 (R-Car M2-N)
- r8a7794 (R-Car E2)
r8a7791 is now called R-Car M2-W.
Signed-off-by: Geert
On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
Signed-off-by: Carlo Caione ca...@caione.org
---
Ping
--
On Sat, Sep 06, 2014 at 08:28:04PM +0200, Carlo Caione wrote:
On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be powered off.
On sab, set 06, 2014 at 11:38:34 -0700, Greg KH wrote:
On Sat, Sep 06, 2014 at 08:28:04PM +0200, Carlo Caione wrote:
On dom, ago 17, 2014 at 12:49:49 +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B,
Hi,
Following Ben's report and fix for RN102, I did some tests
on RN104 and RN2120 (they have the same Hynix H27U1G8F2BTR
flash and setup) and came up w/ the exact same fixes for
their respective .dts files. With those patches, it is now
possible to update kernel from userland and u-boot will
The bootloader on the Netgear ReadyNAS RN104 uses Hardware BCH
ECC (strength = 4), while the pxa3xx NAND driver by default uses
Hamming ECC (strength = 1).
This patch changes the ECC mode on these machines to match that
of the bootloader and of the stock firmware. That way, it is
now possible to
The bootloader on the Netgear ReadyNAS RN2120 uses Hardware BCH
ECC (strength = 4), while the pxa3xx NAND driver by default uses
Hamming ECC (strength = 1).
This patch changes the ECC mode on these machines to match that
of the bootloader and of the stock firmware. That way, it is
now possible
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