On Thu, Sep 11, 2014 at 11:29:39AM +0800, Anson Huang wrote:
Anson Huang (3):
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: dts: imx6: make gpt per clock can be from OSC
ARM: imx: source gpt per clk from OSC for system timer
Applied all, thanks.
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To unsubscribe from this list: send the
On Thu, Sep 11, 2014 at 07:01:19AM -0500, Nishanth Menon wrote:
Hi Dimtry,
On 14:13-20140910, Dmitry Torokhov wrote:
On Thu, Aug 21, 2014 at 02:01:43PM -0500, Nishanth Menon wrote:
On 08/21/2014 01:03 PM, Dmitry Torokhov wrote:
I believe I have taken care of other concerns on v2,
Hi Bryan,
Thanks for a review.
On 09/12/2014 03:11 AM, Bryan Wu wrote:
On Wed, Aug 20, 2014 at 6:41 AM, Jacek Anaszewski
j.anaszew...@samsung.com wrote:
Add a mechanism for locking LED subsystem sysfs interface.
This patch prepares ground for addition of LED Flash Class
extension, whose API
Document the 'fast charge timer' setting exported by max14577 driver
through sysfs entry.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Andrew Morton a...@linux-foundation.org
---
Documentation/ABI/testing/sysfs-class-power | 14
Add document describing device tree bindings for MAX14577 MFD
drivers: MFD core, extcon, regulator and charger.
Both MAX14577 and MAX77836 chipsets are documented.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Cc:
Prepare for adding support for MAX77836 charger to the max14577 charger
driver by adding necessary new defines and prefixes to existing ones.
The MAX77836 uses slightly different values for ChgTyp field of STATUS2
register. On the MAX14577 value of 0x6 is reserved and 0x7 dead battery.
On the
MAX77836 has the same Fuel Gauge as MAX17040/17048. The max17040 driver
can be safely re-used. The patch adds MAX77836 device to the array of
i2c_device_id. Additionally it removes the id associated with MAX17040
device as the value is not used.
Signed-off-by: Krzysztof Kozlowski
This patch prepares for changing the max14577 charger driver to allow
configuring battery-dependent settings from DTS.
The patch moves from regulator driver to MFD core driver and exports:
- function for calculating register value for charger's current;
- table of limits for chargers (MAX14577,
Add support for MAX77836 charger to the max14577 driver. The MAX77836
charger is almost the same as 14577 model except:
- No dead-battery detection;
- Support for special charger (like in MAX77693);
- Support for DX over-voltage protection (like in MAX77693);
- Lower values of charging current
Remove hard-coded values for:
- Fast Charge current,
- End Of Charge current,
- Fast Charge timer,
- Overvoltage Protection Threshold,
- Battery Constant Voltage,
and use DTS or sysfs to configure them. This allows using the max14577 charger
driver with different batteries.
Now the charger
Hi,
This is a sixth version of patches adding support for
MAX77836 device to the max14577 drivers.
This patchset has been on the lists for quite long time and was already
reviewed by all necessary maintainers except power supply.
I need acks from power supply subsystem (patches: 3, 5-8).
Add a maxim,max14577-charger of_compatible to the mfd_cell so the
MFD child device (the charger) will have its own of_node set. This will
be used by the max14577 charger driver in next patches to obtain battery
configuration from DTS.
Signed-off-by: Krzysztof Kozlowski k.kozlow...@samsung.com
Cc:
On Thu, Sep 11, 2014 at 11:25 PM, Greg KH gre...@linuxfoundation.org wrote:
On Thu, Sep 11, 2014 at 10:11:34PM +0200, Carlo Caione wrote:
The SoC has four fully functional UARTs which use the same programming
model. They are named UART_A, UART_B, UART_C and UART_AO (Always-On)
which cannot be
On Friday 12 September 2014 02:59 AM, Lennart Sorensen wrote:
I have the mac but I don't want to use both ports on the 2 port switch.
In fact in our case ethernet1 is a pru_eth interface. Can a board dts
override the alias for ethernet1 or is that a syntax error? I don't
think I tried that
Hi,
On 09/11/2014 10:18 PM, Maxime Ripard wrote:
Hi everyone,
Here is an attempt at improving the MMC clock support in the Allwinner
SoCs.
Until now, the MMC clocks were having a custom phase function that was
directly setting an obscure value in the right register, because we
were not
This patch to add driver for rockchip board using a max98090.
Tested on RK3288 using a max98090.
Jianqun (2):
ASoC: rockchip-max98090: add documentation for rockchip-max98090
driver
ASoC: rockchip-max98090: add driver for rockchip board using a
max98090
Add documentation for rockchip-max98090 driver, which is need by rockchip
board using a max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
.../sound/rockchip,rockchip-audio-max98090.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
The driver is used for rockchip board using a max98090.
Test on RK3288 with max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
sound/soc/rockchip/Kconfig | 9 +
sound/soc/rockchip/Makefile| 5 +-
sound/soc/rockchip/rockchip_max98090.c | 308
This introduces device tree bindings for the PL08x DMA controllers
when used with fixed signal assignment per channel, i.e. if each
channel on the PL08x is assigned precisely one burst/single signal
set.
In many incarnations that exist in the wild, a mux had been put
in front of the signals so
On Thu, Sep 11, 2014 at 03:26:50PM -0700, Jacob Pan wrote:
Mark Brown broo...@debian.org wrote:
but is it really worth the effort of renaming everything? That's
going to cause problems for things like the stable workflow.
sorry for the late reply. IMHO, consistent and correct naming has
The driver is used for rockchip board using a max98090.
Test on RK3288 with max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
sound/soc/rockchip/Kconfig | 9 +
sound/soc/rockchip/Makefile| 5 +-
sound/soc/rockchip/rockchip_max98090.c | 326
The driver is used for rockchip board using a max98090.
Test on RK3288 with max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
sound/soc/rockchip/Kconfig | 9 +
sound/soc/rockchip/Makefile| 5 +-
sound/soc/rockchip/rockchip_max98090.c | 326
Am Donnerstag, 11. September 2014, 16:54:22 schrieb Wolfram Sang:
On Thu, Sep 11, 2014 at 04:52:22PM +0200, Marc Dietrich wrote:
Am Donnerstag, 11. September 2014, 16:40:04 schrieb Wolfram Sang:
b) could be seen as a configuration thing since the functionality
backend could be changed
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
Suman Tripathi (1):
ahci_xgene: Fix the error print invalid resource for APM X-Gene SoC
AHCI SATA Host Controller driver.
drivers/ata/ahci_xgene.c | 4 ++--
1 file changed, 2 insertions(+), 2
This patch fixes the error print invalid resource for the APM X-Gene
SoC AHCI SATA Host Controller driver. This print was due to the fact
that the controller 3 don't have a mux resource. This didn't result
in any errors but the print seems like meaningless.
Signed-off-by: Loc Ho l...@apm.com
Hi Marc,
On Fri, Sep 12, 2014 at 9:51 AM, Marc Dietrich marvi...@gmx.de wrote:
Am Donnerstag, 11. September 2014, 16:54:22 schrieb Wolfram Sang:
On Thu, Sep 11, 2014 at 04:52:22PM +0200, Marc Dietrich wrote:
Am Donnerstag, 11. September 2014, 16:40:04 schrieb Wolfram Sang:
b) could be
Add dt for rk3288 i2s controller, since i2s clock pins and data pins
default to be GPIO, this patch also add pinctrl to mux them.
Tested on RK3288 board.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 26 ++
1 file changed, 26
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
This is my version 10 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information to
configure themselves. This version reverses v9's attempt to create one function
to drive the whole process of
On Wed, 2014-09-10 at 21:56 +0200, Uwe Kleine-König wrote:
of_device_ids (i.e. compatible strings and the respective data) are not
supposed to change at runtime. All functions working with of_device_ids
provided by linux/of.h work with const of_device_ids. This allows to
mark all struct
Why do you want DT to be involved at all?
Imagine a device which supports both, slave or master mode. The driver needs
to know in which mode it should operate. This cannot be hard coded, because
on
different boards, different modes can be used.
Okay, it sounds weird to me that a
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/r7s72100.dtsi | 202
1 file changed, 101 insertions(+), 101 deletions(-)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 1d28d01..6a0e57e
Hi!
Here's a bunch of DT files sorted by address only. I hope nobody sees a
need to break those down any further.
None of these patches depend on each other, or anything else for that
matter, so feel free to pick and choose.
Olof, is there a consensus on other sort criteria? I'm thinking of
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/emev2-kzm9d.dts | 62 +++
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts
b/arch/arm/boot/dts/emev2-kzm9d.dts
index
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/r8a73a4.dtsi | 232 -
1 file changed, 116 insertions(+), 116 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fba39a2..2b7735c
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/emev2.dtsi | 120 +--
1 file changed, 60 insertions(+), 60 deletions(-)
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index 00eeed3..41d2da7 100644
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 26 -
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
Signed-off-by: Ulrich Hecht ulrich.hecht+rene...@gmail.com
---
arch/arm/boot/dts/r8a73a4-ape6evm.dts | 36 +--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index
Hi Ulrich,
I know this is not your fault, but...
On Fri, Sep 12, 2014 at 10:51 AM, Ulrich Hecht
ulrich.hecht+rene...@gmail.com wrote:
+ reg_1p8v: regulator@0 {
As there is no reg property, the @0 must not be present.
However, in the absence of a unit-address, the node name must be
Hi Ulrich,
I know this is not your fault, but...
On Fri, Sep 12, 2014 at 10:51 AM, Ulrich Hecht
ulrich.hecht+rene...@gmail.com wrote:
+ dmac: dma-multiplexer@0 {
As there is no reg property, the @0 must not be present.
+ compatible = renesas,shdma-mux;
+
Hi Ulrich,
I know this is not your fault, but...
On Fri, Sep 12, 2014 at 10:51 AM, Ulrich Hecht
ulrich.hecht+rene...@gmail.com wrote:
+ ape6evm_fixed_3v3: fixedregulator@0 {
As there is no reg property, the @0 must not be present.
+ compatible = regulator-fixed;
+
Am Freitag, 12. September 2014, 10:33:48 schrieb Wolfram Sang:
Why do you want DT to be involved at all?
Imagine a device which supports both, slave or master mode. The driver
needs to know in which mode it should operate. This cannot be hard coded,
because on different boards,
Add documentation for rockchip-max98090 driver, which is need by rockchip
board using a max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
changes since v1:
- modify error text from Tegra to rockchip
.../sound/rockchip,rockchip-audio-max98090.txt | 23 ++
1
On Thu, Sep 11, 2014 at 11:57:43PM +0100, Tanmay Inamdar wrote:
This patch adds the AppliedMicro X-Gene SOC PCIe host controller driver.
X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
X-Gene SOC supports maximum 5 PCIe ports.
Signed-off-by: Tanmay Inamdar
On Fri, Sep 12, 2014 at 09:25:13AM +0100, Suravee Suthikulpanit wrote:
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
This is my version 10 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information to
configure themselves. This version
Hi,
On 05/09/14 07:48, Xiubo Li wrote:
Some Freescale SoCs, there has an DVI/HDMI controller and a PHY,
attached to one of their display controller unit's LCDC interfaces.
This patch adds a preliminary static support for such controllers.
This will support for many modes and a dynamic
On 09/11/2014 09:33 PM, Mark Brown wrote:
On Thu, Sep 11, 2014 at 03:03:50PM +0200, Javier Martinez Canillas wrote:
This can be easily worked around (and probably why it never was an issue) if
the OF and SPI tables are kept in sync but I don't know if that is a hard
requirement for all
Add simple power off driver for i.mx6, including:
- add basic imx-snvs-poweroff driver in drivers/power/reset
- add device node in all dts files of i.mx6.
- enable in config file
Robin Gong (3):
ARM: dts: imx6: add pm_power_off support for i.mx6 chips
power: reset: imx-snvs-poweroff: add
Add power off driver in config file.
Signed-off-by: Robin Gong b38...@freescale.com
---
arch/arm/configs/imx_v6_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/arch/arm/configs/imx_v6_v7_defconfig
index 16cfec4..a310e61 100644
---
All chips of i.mx6 can be powered off by programming SNVS.
For example :
On i.mx6q-sabresd board, PMIC_ON_REQ connect with external
pmic ON/OFF pin, that will cause the whole PMIC powered off
except VSNVS. And system can restart once PMIC_ON_REQ goes
high by push POWRER key.
Signed-off-by: Robin
ok, take our embedded controller driver (in staging/nvec) as an example. It's
basicly an MFD connecting keyboard, mouse, power, gpio, and some other stuff
to the soc. The MFD operates in master mode while the SOC is the I2C slave.
Theoretically, these roles could also switch (but that's
On 9/12/2014 4:30 AM, Liviu Dudau wrote:
On Fri, Sep 12, 2014 at 09:25:13AM +0100, Suravee Suthikulpanit wrote:
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
This is my version 10 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information to
Hi Jianqun,
Am Freitag, 12. September 2014, 17:10:55 schrieb Jianqun:
Add documentation for rockchip-max98090 driver, which is need by rockchip
board using a max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
changes since v1:
please make sure to also include the version in the
Add simple power off driver for i.mx6.
Signed-off-by: Robin Gong b38...@freescale.com
---
drivers/power/reset/Kconfig | 6 +++
drivers/power/reset/Makefile| 1 +
drivers/power/reset/imx-snvs-poweroff.c | 69 +
3 files changed, 76
Hi Wolfram,
On Fri, Sep 12, 2014 at 11:58 AM, Wolfram Sang w...@the-dreams.de wrote:
2) Slave mode is needed for board bringup
Some other components need a specific I2C slave to be present before
userspace is available, otherwise the system is unusable. This is IMO
then a hardware
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
If the firmware has not assigned all the bus resources and
we are not just probing the PCIe busses, it makes sense to
assign the unassigned resources in pci_scan_root_bus().
Cc: Bjorn Helgaas bhelg...@google.com
Cc: Arnd Bergmann a...@arndb.de
Cc: Jason
在 09/12/2014 06:04 PM, Heiko Stübner 写道:
Hi Jianqun,
Am Freitag, 12. September 2014, 17:10:55 schrieb Jianqun:
Add documentation for rockchip-max98090 driver, which is need by rockchip
board using a max98090.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
changes since v1:
This patch adds clock names for rk3288 eDP.
Signed-off-by: Mark yao mark@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 6 +++---
include/dt-bindings/clock/rk3288-cru.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
On 12/09/14 01:01, Doug Anderson wrote:
Stephen,
On Thu, Sep 11, 2014 at 4:56 PM, Stephen Boyd sb...@codeaurora.org wrote:
On 09/11/14 10:43, Marc Zyngier wrote:
If I was suicidal, I'd suggest you could pass a parameter to the command
line, interpreted by the timer code... But I since I'm
On Fri, Sep 12, 2014 at 4:18 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Add the sample and output clocks for the MMC phase support.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun4i-a10.dtsi | 104
This patch adds clock names for rk3288 HDMI.
Signed-off-by: Mark yao mark@rock-chips.com
---
drivers/clk/rockchip/clk-rk3288.c | 6 +++---
include/dt-bindings/clock/rk3288-cru.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c
DT pseudocode:
i2c {
compatible = nvidia, tegra-i2c;
ec-slave@42 {
compatible = nvidia, ax100-ec-slave;
reg = 0x42;
};
};
So distinguishing between drivers
Daniel, Lorenzo,
On Thu, Sep 11, 2014 at 10:32:48AM +0100, Daniel Lezcano wrote:
On 09/11/2014 10:57 AM, Lorenzo Pieralisi wrote:
There is no ARM code in my series. So to sum it up:
a) I send a pull request to Catalin for arm64 patches on top of the branch
you are creating with my
The rk3288 have two vop, and each vop has three softresets were axi_reset,
ahb_reset and dclk_reset.
Signed-off-by: Mark yao mark@rock-chips.com
---
include/dt-bindings/clock/rk3288-cru.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
On Fri, Sep 12, 2014 at 11:13:51AM +0100, Suravee Suthikulpanit wrote:
On 9/8/2014 8:54 AM, Liviu Dudau wrote:
If the firmware has not assigned all the bus resources and
we are not just probing the PCIe busses, it makes sense to
assign the unassigned resources in pci_scan_root_bus().
Add dt for rk3288 i2s controller, since i2s clock pins and data pins
default to be GPIO, this patch also add pinctrl to mux them.
Tested on RK3288 board.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
change since v1:
- move i2s relate codes later in order by CPU address map
Hi Mark,
Am Freitag, 12. September 2014, 18:33:23 schrieb Mark yao:
The rk3288 have two vop, and each vop has three softresets were axi_reset,
ahb_reset and dclk_reset.
I'm not sure about renaming the indices, since they're part of the devicetree-
binding. We know that so far no device in the
On 2014年09月12日 18:41, Heiko Stübner wrote:
Hi Mark,
Am Freitag, 12. September 2014, 18:33:23 schrieb Mark yao:
The rk3288 have two vop, and each vop has three softresets were axi_reset,
ahb_reset and dclk_reset.
I'm not sure about renaming the indices, since they're part of the devicetree-
On Fri, Sep 12, 2014 at 11:32:57AM +0100, Catalin Marinas wrote:
Daniel, Lorenzo,
On Thu, Sep 11, 2014 at 10:32:48AM +0100, Daniel Lezcano wrote:
On 09/11/2014 10:57 AM, Lorenzo Pieralisi wrote:
There is no ARM code in my series. So to sum it up:
a) I send a pull request to Catalin
Am Freitag, 12. September 2014, 11:58:21 schrieb Wolfram Sang:
ok, take our embedded controller driver (in staging/nvec) as an example.
It's basicly an MFD connecting keyboard, mouse, power, gpio, and some
other stuff to the soc. The MFD operates in master mode while the SOC is
the I2C
Hi Marc,
On 09/11/2014 01:43 PM, Marc Zyngier wrote:
On 11/09/14 18:29, Doug Anderson wrote:
Marc,
On Thu, Sep 11, 2014 at 10:22 AM, Marc Zyngier marc.zyng...@arm.com wrote:
We would need to run this code potentially at processor bringup and
after suspend/resume, but that seems possible
The patch add the rest of the indices of the additional reset
registers from the updated TRM.
Signed-off-by: Mark yao mark@rock-chips.com
---
include/dt-bindings/clock/rk3288-cru.h | 43 ++
1 file changed, 43 insertions(+)
diff --git
The MAX77693 is a companion power management IC for smart phones and tablets.
The MAX77693 contains input over-voltage protection (OVP),
a fully-integrated 2.5A switching charger for Lithium Ion battery with
integrated battery disconnect, OTG/accessory 5V output power,
a high-current white LED
Am I missing something? Board properties can be encoded within the
compatible entries (ax100-ec, ax200-ec...). I'd think this means
mostly different protocols, though.
well, ac100 is the name of the board and nvec is the name of the protocol.
Yes, the driver could be named nvec, yet
Hi Christopher,
On 12/09/14 12:43, Christopher Covington wrote:
Hi Marc,
On 09/11/2014 01:43 PM, Marc Zyngier wrote:
On 11/09/14 18:29, Doug Anderson wrote:
Marc,
On Thu, Sep 11, 2014 at 10:22 AM, Marc Zyngier marc.zyng...@arm.com wrote:
We would need to run this code potentially at
This clock drives the INTCA irqpin controller modules.
Before, it was assumed enabled by the bootloader or reset state.
Signed-off-by: Geert Uytterhoeven geert+rene...@glider.be
Cc: devicetree@vger.kernel.org
---
arch/arm/boot/dts/r8a7740.dtsi| 14 ++
On Thu, Aug 28, 2014 at 03:35:30PM +0100, Lee Jones wrote:
Hi Wolfram,
Placing this firmly back on your plate. I truly hope we don't miss
another merge-window. This patch-set has the support of some pretty
senior kernel maintainers, so I hope acceptance shouldn't be too
difficult.
As
On Thu, Aug 28, 2014 at 03:35:32PM +0100, Lee Jones wrote:
A great deal of I2C devices are currently matched via DT node name, and
as such the compatible naming convention of 'vendor,device' has gone
somewhat awry - some nodes don't supply one, some supply an arbitrary
string and others the
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 79b674d..c8240e5 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -125,7 +125,8 @@ extern s32 i2c_smbus_write_i2c_block_data(const struct
i2c_client *client,
* struct i2c_driver - represent an I2C device driver
Changes since v3:
- Removed aliases for serial controllers from dtsi file and moved it
into board specific dts file as suggested by Arnd.
- Based this series on Robert Richter's patches for adding vendor
device tree sub-directories for arm64.
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have
From: Alim Akhtar alim.akh...@samsung.com
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos7 SoC.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin
From: Pankaj Dubey pankaj.du...@samsung.com
Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to
match the ones in ARM architectures so that preprocessed device
tree files can include various useful constant definitions.
See commit c58299aa8754 (kbuild: create an include
Allow Samsung serial driver to be usable on Exynos 64-bit SoC based
platforms.
Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig |2 +-
1 file
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the USART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile
Changes since v3:
- Removed aliases for serial controllers from dtsi file and moved it
into board specific dts file as suggested by Arnd.
- Based this series on Robert Richter's patches for adding vendor
device tree sub-directories for arm64.
From: Murali Karicheri m-kariche...@ti.com
This patch adds ability to configure delay between transmission of
words over SPI bus if it's required by SPI slave devices.
New optional SPI slave's property:
- ti,spi-word-delay : delay between transmission of words
(SPIFMTn.WDELAY,
On 11/09/14 11:47, Philipp Zabel wrote:
Am Mittwoch, den 10.09.2014, 16:46 +0300 schrieb Dmitry Lavnikevich:
Since pins and frequency are specific to module (pfla02), not base board
(pbab02), it is better to be initialized in corresponding dts file.
Signed-off-by: Dmitry Lavnikevich
On Fri, 12 Sep 2014, Chen, Alvin wrote:
On Tue, 9 Sep 2014, Weike Chen wrote:
struct dwapb_gpio;
+struct dwapb_context;
struct dwapb_gpio_port {
struct bgpio_chip bgc;
boolis_registered;
struct dwapb_gpio *gpio;
+ struct
On Wed, 2014-09-10 at 15:26 -0600, Stephen Warren wrote:
No, definitely not; this patch has significant semantic changes since I
reviewed it.
OK, sorry. Admittedly this was probably a little bit too quick a shot.
The solution looked so clean and on first sight worked just fine.
I'm not sure
Rafael,
Doug Anderson diand...@chromium.org writes:
From: Heiko Stübner he...@sntech.de
IO domain voltages on some Rockchip SoCs are variable but need to be
kept in sync between the regulators and the SoC using a special
register.
A specific example using rk3288:
- If the regulator
On Tue, Sep 9, 2014 at 1:21 AM, Tomeu Vizoso to...@tomeuvizoso.net wrote:
On 8 September 2014 18:22, Andrew Bresticker abres...@chromium.org wrote:
On Mon, Sep 8, 2014 at 8:34 AM, Tomeu Vizoso to...@tomeuvizoso.net wrote:
On 2 September 2014 23:34, Andrew Bresticker abres...@chromium.org wrote:
On Fri, Sep 12, 2014 at 1:49 PM, Janusz Uzycki j.uzy...@elproma.com.pl wrote:
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the USART controller doesn't handle DTR/DSR/DCD/RI signals,
You meant
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
Qualcomm platforms. This driver uses the generic PHY framework and will
interact with the DWC3 controller.
Signed-off-by: Andy Gross agr...@codeaurora.org
---
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
Signed-off-by: Andy
From: Ivan T. Ivanov iiva...@mm-sol.com
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov iiva...@mm-sol.com
[adding Sjoerd as cc who was the one that raised the module auto-loading issue]
Hello,
On Fri, Sep 12, 2014 at 3:46 PM, Wolfram Sang w...@the-dreams.de wrote:
Placing this firmly back on your plate. I truly hope we don't miss
another merge-window. This patch-set has the support of some
Hi,
On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
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