On Thursday 18 September 2014 08:55 AM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Wed, Sep 17, 2014 at 10:24 PM, Kishon Vijay Abraham I
> wrote:
>>
>>
>> On Tuesday 16 September 2014 10:32 AM, Vivek Gautam wrote:
>>> Currently the DP_PHY_ENABLE register is mapped in the driver,
>>> and access
Hi Tomi,
On Wed, Sep 17, 2014 at 9:52 PM, Tomi Valkeinen wrote:
> On 17/09/14 17:29, Ajay kumar wrote:
>> Hi Tomi,
>>
>> Thanks for your comments.
>>
>> On Wed, Sep 17, 2014 at 5:22 PM, Tomi Valkeinen
>> wrote:
>>> On 27/08/14 17:39, Ajay Kumar wrote:
Add documentation for DT properties su
On Tue, 16 Sep 2014, Jacob Pan wrote:
> X-Powers AXP288 is a customized PMIC for Intel Baytrail-CR platforms. Similar
> to AXP202/209, AXP288 comes with USB charger, more LDO and BUCK channels, and
> AD converters. It also provides extended status and interrupt reporting
> capabilities than the de
On 09/17/2014 06:17 PM, Mark Rutland wrote:
> On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
>> From: Peter Crosthwaite
>>
>> Modern TTC implementations can extend the timer width to 32 bit. This
>> feature is not self identifying so the driver needs to be made aware
>> via device t
On Wed, Sep 17, 2014 at 2:49 PM, Srinivas Kandagatla
wrote:
>
>
> On 17/09/14 20:18, Josh Cartwright wrote:
>>
>> On Wed, Sep 17, 2014 at 12:03:37PM -0700, Kumar Gala wrote:
[..]
>>> Hmm, this doesn?t seem to work for me.
>>
>>
>> I don't see how it could with qcom_defconfig, as we set
>> CONFIG_A
On Thu, Sep 18, 2014 at 4:42 AM, Zi Shen Lim wrote:
> On Wed, Sep 17, 2014 at 2:48 PM, Nathan Lynch wrote:
>> On 09/17/2014 03:56 AM, Ganapatrao Kulkarni wrote:
>>> From: Ganapatrao Kulkarni
>>>
>>> This patch adds property "nid" to memory node to provide the memory range to
>>> numa node id map
Hi Kishon,
On Wed, Sep 17, 2014 at 10:24 PM, Kishon Vijay Abraham I wrote:
>
>
> On Tuesday 16 September 2014 10:32 AM, Vivek Gautam wrote:
>> Currently the DP_PHY_ENABLE register is mapped in the driver,
>> and accessed to control power to the PHY.
>> With mfd-syscon and regmap interface availa
The A23 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints and physical channels. Add the proper
config data and compatible string to support it.
A slight difference in sun8i is an undocumented register needs
to be toggled for dma to function.
Signed-off-by: Chen-Y
This patch adds support for hardware parameters tied to compatible
strings, so similar hardware can reuse the driver.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
drivers/dma/sun6i-dma.c | 96 +++--
1 file changed, 61 insertions(+), 35 dele
Hi everyone,
This is v2 of my sun8i DMA controller support series. This series
adds support for the DMA controller found in the Allwinner A23 SoC.
It is the same hardware as found in the A31 (sun6i) SoC. In addition
to reduced physical channels and endpoints, the controller in the A23
requires an
Add the DMA controller node and DMA bindings to the supported devices.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index cc8c650..46a8
Hi,
In this patch series we use winkle for offlined cores. I successfully
tested the working of this with subcore functionality.
Test scenario was as follows:
1. Set SMT mode to 1, Set subores-per-core to 1
2. Offline a core, in this case cpu 32 (sending it to winkle)
3. Set subcores-per-core to
在 2014年09月18日 04:13, Dmitry Torokhov 写道:
On Wed, Sep 17, 2014 at 12:48:16PM -0700, Doug Anderson wrote:
Caesar,
On Tue, Sep 16, 2014 at 8:59 PM, Caesar Wang wrote:
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: C
From: Suravee Suthikulpanit
NOTE: Resend w/ proper subject for the 2/2 patch.
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports f
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
arch
On Wed, Sep 17, 2014 at 06:52:44PM +0100, Mark Rutland wrote:
> On Wed, Sep 17, 2014 at 10:57:59AM +0100, Robin Gong wrote:
> > This driver register pm_power_off with snvs power off function. If
> > your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use
> > other pin to do, please dis
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
arch
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v10 00/10] Support for creati
On Wed, Sep 17, 2014 at 11:55 PM, Maxime Ripard
wrote:
> On Tue, Sep 16, 2014 at 10:13:27PM +0800, Chen-Yu Tsai wrote:
>> >> + /*
>> >> + * sun8i variant requires us to toggle an undocumented register,
>> >> + * as seen in Allwinner's SDK.
>> >
>> > The BSP I have has this:
>> >
>> >
If the firmware has not assigned all the bus resources and
we are not just probing the PCIe busses, it makes sense to
assign the unassigned resources in pci_scan_root_bus().
Cc: Bjorn Helgaas
Cc: Arnd Bergmann
Cc: Jason Gunthorpe
Cc: Rob Herring
Signed-off-by: Liviu Dudau
---
drivers/pci/pro
Some architectures do not have a simple view of the PCI I/O space
and instead use a range of CPU addresses that map to bus addresses.
For some architectures these ranges will be expressed by OF bindings
in a device tree file.
This patch introduces a pci_register_io_range() helper function with
a g
Introduce a default implementation for remapping PCI bus I/O resources
onto the CPU address space. Architectures with special needs may
provide their own version, but most should be able to use this one.
Cc: Bjorn Helgaas
Cc: Arnd Bergmann
Cc: Rob Herring
Reviewed-by: Catalin Marinas
Signed-of
Hi,
This patch adds support for PCIe to AArch64. It depends on my v11 patch
that adds support for creating generic host bridge resources from device
trees. With that in place, I was able to boot a platform that
has PCIe host bridge support and use a PCIe network card.
Changes from v10:
- Added C
This is my version 11 of the attempt at adding support for generic PCI host
bridge controllers that make use of device tree information to
configure themselves. It contains minor cleanups compared with v10 to address
the existing comments.
I'm going to ask for this series to be included in -next.
Add of_pci_get_domain_nr() to retrieve the PCI domain number
of a given device from DT. If the information is not present,
the function can be requested to allocate a new domain number.
Cc: Bjorn Helgaas
Cc: Arnd Bergmann
Cc: Grant Likely
Cc: Rob Herring
Reviewed-by: Catalin Marinas
Signed-of
The inline version of ioport_map() that gets used when !CONFIG_GENERIC_IOMAP
is wrong. It returns a mapped (i.e. virtual) address that can start from
zero and completely ignores the PCI_IOBASE and IO_SPACE_LIMIT that most
architectures that use !CONFIG_GENERIC_MAP define.
Signed-off-by: Liviu Duda
Before commit 7b5436635800 the pci_host_bridge was created before the root bus.
As that commit has added a needless dependency on the bus for
pci_alloc_host_bridge()
the creation order has been changed for no good reason. Revert the order of
creation as we are going to depend on the pci_host_bridg
Use the generic PCI domain and OF functions
to provide support for PCI Express on arm64.
Acked-by: Catalin Marinas
Signed-off-by: Liviu Dudau
---
arch/arm64/Kconfig | 22 ++-
arch/arm64/include/asm/Kbuild| 1 +
arch/arm64/include/asm/io.h | 3 +-
arch/arm64/
Provide a function to parse the PCI DT ranges that can be used to
create a pci_host_bridge structure together with its associated
bus.
Cc: Bjorn Helgaas
Cc: Arnd Bergmann
Cc: Grant Likely
Cc: Rob Herring
Cc: Catalin Marinas
Signed-off-by: Liviu Dudau
---
drivers/of/of_pci.c| 108 +++
The ranges property for a host bridge controller in DT describes
the mapping between the PCI bus address and the CPU physical address.
The resources framework however expects that the IO resources start
at a pseudo "port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.
The conversion fr
From: Catalin Marinas
The handling of PCI domains (or PCI segments in ACPI speak) is
usually a straightforward affair but its implementation is
currently left to the architectural code, with pci_domain_nr(b)
querying the value of the domain associated with bus b.
This patch introduces CONFIG_PCI
This is needed for calls into OF code that parses PCI ranges.
It signals support for memory mapped PCI I/O accesses that
are described be device trees.
Cc: Russell King
Cc: Arnd Bergmann
Cc: Rob Herring
Reviewed-by: Catalin Marinas
Signed-off-by: Liviu Dudau
---
arch/arm/include/asm/io.h | 1
On 18 September 2014 01:43, Dmitry Torokhov wrote:
> On Thu, Sep 18, 2014 at 01:20:49AM +0200, Ulf Hansson wrote:
>> On 17 September 2014 22:10, Dmitry Torokhov
>> wrote:
>> > On Wed, Sep 17, 2014 at 08:25:44PM +0200, Ulf Hansson wrote:
>> >> On 16 September 2014 01:36, Rafael J. Wysocki wrote:
On Mon, Aug 18, 2014 at 03:08:40PM +0800, Josh Wu wrote:
> If there is no PMECC lookup table stored in ROM, or lookup table offset is
> not specified, PMECC driver should build it in DDR by itself.
>
> That make the PMECC driver work for some board which doesn't has PMECC
> lookup table in ROM.
>
On Thu, Sep 18, 2014 at 01:20:49AM +0200, Ulf Hansson wrote:
> On 17 September 2014 22:10, Dmitry Torokhov wrote:
> > On Wed, Sep 17, 2014 at 08:25:44PM +0200, Ulf Hansson wrote:
> >> On 16 September 2014 01:36, Rafael J. Wysocki wrote:
> >> > On Monday, September 15, 2014 09:53:59 AM Dmitry Toro
On 17 September 2014 22:10, Dmitry Torokhov wrote:
> On Wed, Sep 17, 2014 at 08:25:44PM +0200, Ulf Hansson wrote:
>> On 16 September 2014 01:36, Rafael J. Wysocki wrote:
>> > On Monday, September 15, 2014 09:53:59 AM Dmitry Torokhov wrote:
>> >> On Sun, Sep 14, 2014 at 06:38:58PM +0200, Rafael J.
On Thu, 18 Sep 2014 00:20:00 +0200
Hartmut Knaack wrote:
> Jacob Pan schrieb, Am 17.09.2014 02:11:
> > Platform driver for X-Powers AXP288 ADC, which is a sub-device of
> > the customized AXP288 PMIC for Intel Baytrail-CR platforms. GPADC
> > device enumerates as one of the MFD cell devices. It u
On Wed, Sep 17, 2014 at 2:48 PM, Nathan Lynch wrote:
> On 09/17/2014 03:56 AM, Ganapatrao Kulkarni wrote:
>> From: Ganapatrao Kulkarni
>>
>> This patch adds property "nid" to memory node to provide the memory range to
>> numa node id mapping.
>>
>> Signed-off-by: Ganapatrao Kulkarni
>>
>> ---
>>
Hartmut Knaack schrieb, Am 18.09.2014 00:20:
> Jacob Pan schrieb, Am 17.09.2014 02:11:
>> Platform driver for X-Powers AXP288 ADC, which is a sub-device of the
>> customized AXP288 PMIC for Intel Baytrail-CR platforms. GPADC device
>> enumerates as one of the MFD cell devices. It uses IIO infrastru
On Sep 17, 2014, at 9:26 AM, Yaniv Gardi wrote:
> This change depends on draviv [PATCH v3] series of 16 changes that was
> already uploaded.
> Soon draviv will uploaded again as [PATCH v4] that contain 17 patches, and
> this change will be dependent on this serie,
>
> Thanks,
> Yaniv
>
> -
Jacob Pan schrieb, Am 17.09.2014 02:11:
> Platform driver for X-Powers AXP288 ADC, which is a sub-device of the
> customized AXP288 PMIC for Intel Baytrail-CR platforms. GPADC device
> enumerates as one of the MFD cell devices. It uses IIO infrastructure
> to communicate with userspace and consumer
On 17/09/14 20:18, Josh Cartwright wrote:
On Wed, Sep 17, 2014 at 12:03:37PM -0700, Kumar Gala wrote:
On Sep 16, 2014, at 11:34 PM, Pramod Gurav wrote:
On Wednesday 17 September 2014 11:06 AM, Srinivas Kandagatla wrote:
This patch adds memory details of IFC6410 as this is necessary to
fix t
On 09/17/2014 03:56 AM, Ganapatrao Kulkarni wrote:
> From: Ganapatrao Kulkarni
>
> This patch adds property "nid" to memory node to provide the memory range to
> numa node id mapping.
>
> Signed-off-by: Ganapatrao Kulkarni
>
> ---
> Documentation/devicetree/bindings/numa.txt | 58
> +
On Wed, 17 Sep 2014, Sebastian Reichel wrote:
> On Wed, Sep 17, 2014 at 08:44:00AM -0700, Lee Jones wrote:
> > On Wed, 17 Sep 2014, Nishanth Menon wrote:
> > > ti,system-power-controller is more or less the standard way of
> > > indicating that the PMIC is the system wide power controller and henc
On Wed, 17 Sep 2014, Nishanth Menon wrote:
> ti,system-power-controller is more or less the standard way of
> indicating that the PMIC is the system wide power controller and hence
> may be used to switch off the system. Almost ALL TI PMIC drivers and
> many Maxim PMIC drivers follow the same styl
On Wed, 17 Sep 2014, Boris BREZILLON wrote:
> On Wed, 17 Sep 2014 09:34:05 -0700
> Lee Jones wrote:
>
> > On Thu, 11 Sep 2014, Boris BREZILLON wrote:
> >
> > > The GPBR block provides a set of battery-backed registers that can be used
> > > to save data which need to be kept when the system is p
On Wed, 17 Sep 2014, Doug Anderson wrote:
> On Wed, Sep 17, 2014 at 6:08 AM, Chris Zhong wrote:
> > Document the st-pwm regulator
> >
> > Signed-off-by: Chris Zhong
> >
> > ---
> >
> > .../devicetree/bindings/regulator/st-pwm.txt | 35
> >
> > 1 file changed, 35 ins
On 09/17/2014 10:41 PM, Mark Brown wrote:
On Tue, Sep 16, 2014 at 11:40:17PM +0300, Jyri Sarha wrote:
Adds configuration option for HDMI audio support for AM33XX based
boards with NXP TDA998x HDMI transmitter. The audio is connected to
NXP TDA998x trough McASP running in i2s mode.
So, Jean-Fra
On Wed, Sep 17, 2014 at 12:48:16PM -0700, Doug Anderson wrote:
> Caesar,
>
> On Tue, Sep 16, 2014 at 8:59 PM, Caesar Wang
> wrote:
> > This add the necessary binding documentation for the thermal
> > found on Rockchip SoCs
> >
> > Signed-off-by: zhaoyifeng
> > Signed-off-by: Caesar Wang
> > --
On Wed, Sep 17, 2014 at 08:25:44PM +0200, Ulf Hansson wrote:
> On 16 September 2014 01:36, Rafael J. Wysocki wrote:
> > On Monday, September 15, 2014 09:53:59 AM Dmitry Torokhov wrote:
> >> On Sun, Sep 14, 2014 at 06:38:58PM +0200, Rafael J. Wysocki wrote:
> >> > On Friday, September 12, 2014 02:0
The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface. While there is only a single
physical channel, messages sent by the controller can be divided
into two groups: those intended for the PHY driver and those intended
for the host-controller
This series adds support for xHCI on NVIDIA Tegra SoCs. This includes:
- patches 1 and 2: adding a driver for the mailbox used to communicate
with the xHCI controller's firmware,
- patches 3 and 4: extending the XUSB pad controller driver to support
the USB PHY types (UTMI, HSIC, and USB3)
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Dropped channel specifier.
- Add
Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Added mbox-names property.
Changes from v1:
- Updated to use common mailbox bindings.
- Add
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
The xHCI controller will also send messages intended for the PHY driver,
so request and listen
Assign USB ports previously owned by the EHCI controllers to the xHCI
controller. There is a mini-PCIe USB port (UTMI port 1) and a USB A
connector (UTMI port 2, USB3 port 0). PCIe lane 0 is used for USB3
port 0.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
Changes from v3:
Add nodes for the Tegra XUSB mailbox and Tegra xHCI controller and
add the PHY mailbox channel to the XUSB padctl node.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Dropped channel specifier from mailbox bindings.
- Added mbox-names pr
Add support for the on-chip xHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The hardware also supports device mode
as well as powerg
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
Changes from v2:
- Added nvidia,otg-hs-curr-level-offset property.
- Dropped "-ot
Assign ports previously owned by the EHCI controllers to the xHCI
controller. There are two external USB ports (UTMI ports 0/2 and
USB3 ports 0/1) and an internal USB port (UTMI port 1). PCIe lanes
0 and 1 are used by the USB3 ports.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
On Wed, Sep 17, 2014 at 02:12:28AM +0100, Kever Yang wrote:
> Hi Mark,
>
> Thanks for your comment.
> On 09/17/2014 02:54 AM, Mark Rutland wrote:
> > On Tue, Sep 16, 2014 at 11:44:28AM +0100, Kever Yang wrote:
> >> This add documentation for rk3288 smp dt binding
> >>
> >> Signed-off-by: Keve
Caesar,
On Tue, Sep 16, 2014 at 8:59 PM, Caesar Wang wrote:
> This add the necessary binding documentation for the thermal
> found on Rockchip SoCs
>
> Signed-off-by: zhaoyifeng
> Signed-off-by: Caesar Wang
> ---
> .../bindings/thermal/rockchip-thermal.txt | 41
>
On Wed, Sep 17, 2014 at 07:16:23PM +0100, Doug Anderson wrote:
> Chris,
>
> On Wed, Sep 17, 2014 at 6:08 AM, Chris Zhong wrote:
> > Document the st-pwm regulator
> >
> > Signed-off-by: Chris Zhong
> >
> > ---
> >
> > .../devicetree/bindings/regulator/st-pwm.txt | 35
> > +++
On Tue, Sep 16, 2014 at 11:40:17PM +0300, Jyri Sarha wrote:
> Adds configuration option for HDMI audio support for AM33XX based
> boards with NXP TDA998x HDMI transmitter. The audio is connected to
> NXP TDA998x trough McASP running in i2s mode.
So, Jean-Francois is also trying to do things with t
On Wed, Sep 17, 2014 at 04:37:30PM +0100, Kumar Gala wrote:
>
> On Sep 17, 2014, at 1:56 AM, Ganapatrao Kulkarni
> wrote:
>
> > From: Ganapatrao Kulkarni
> >
> > This patch adds property "nid" to memory node to provide the memory range to
> > numa node id mapping.
> >
> > Signed-off-by: Gana
On Wed, Sep 17, 2014 at 12:03:37PM -0700, Kumar Gala wrote:
> On Sep 16, 2014, at 11:34 PM, Pramod Gurav
> wrote:
> > On Wednesday 17 September 2014 11:06 AM, Srinivas Kandagatla wrote:
> >> This patch adds memory details of IFC6410 as this is necessary to
> >> fix the in-correct memory start com
On Sep 16, 2014, at 11:34 PM, Pramod Gurav wrote:
> Hi Srini,
>
> Thanks for the patch.
> Tested-by: Pramod Gurav
>
> A minor nit.
> On Wednesday 17 September 2014 11:06 AM, Srinivas Kandagatla wrote:
>> This patch adds memory details of IFC6410 as this is necessary to
>> fix the in-correct m
On Wed, Sep 17, 2014 at 11:19:40AM -0700, Bjorn Andersson wrote:
> The regulator driver have a strong dependency on the mfd driver, but Kconfig
> will make sure it's not selectable until the two parts merges again, so it
> should be fine. But I guess it's up to Mark?
Yes, that's the normal approa
On Wed, Sep 17, 2014 at 11:16:23AM -0700, Doug Anderson wrote:
> I _think_ that the "regulators" subnode and the "pwm-regulator"
> subnode are not needed at all and should be removed. Other instances
> of devices that are "just" regulators don't have it (like
> fixed-regulator, gpio-regulator, et
On Tue, Sep 16, 2014 at 02:52:33PM +0300, Mika Westerberg wrote:
> From: "Rafael J. Wysocki"
>
> Add a uniform interface by which device drivers can request device
> properties from the platform firmware by providing a property name
> and the corresponding data type. The purpose of it is to help
On 16 September 2014 01:36, Rafael J. Wysocki wrote:
> On Monday, September 15, 2014 09:53:59 AM Dmitry Torokhov wrote:
>> On Sun, Sep 14, 2014 at 06:38:58PM +0200, Rafael J. Wysocki wrote:
>> > On Friday, September 12, 2014 02:05:53 PM Dmitry Torokhov wrote:
>> > > Hi Ulf,
>> > >
>> > > On Tue, S
On Wed 17 Sep 09:15 PDT 2014, Lee Jones wrote:
> On Tue, 26 Aug 2014, Lee Jones wrote:
>
> > On Mon, 25 Aug 2014, Bjorn Andersson wrote:
> >
> > > Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660,
> > > 8960 and 8064 based devices. The binding currently describes the rpm
>
Chris,
On Wed, Sep 17, 2014 at 6:08 AM, Chris Zhong wrote:
> Document the st-pwm regulator
>
> Signed-off-by: Chris Zhong
>
> ---
>
> .../devicetree/bindings/regulator/st-pwm.txt | 35
>
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicet
On Wed, Sep 17, 2014 at 06:47:19PM +0100, Rob Herring wrote:
> On Wed, Sep 17, 2014 at 12:03 PM, Will Deacon wrote:
> > On Wed, Sep 17, 2014 at 12:56:07PM +0100, Robin Murphy wrote:
> >> Commit 591c1e ("of: configure the platform device dma parameters)
> >> introduced a common mechanism to configu
Hi Lee,
On Wed, 17 Sep 2014 09:34:05 -0700
Lee Jones wrote:
> On Thu, 11 Sep 2014, Boris BREZILLON wrote:
>
> > The GPBR block provides a set of battery-backed registers that can be used
> > to save data which need to be kept when the system is powered down and
> > VDD-core is maintained by an
On Wed, Sep 17, 2014 at 10:57:59AM +0100, Robin Gong wrote:
> This driver register pm_power_off with snvs power off function. If
> your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use
> other pin to do, please disable the driver in dts, otherwise, your
> pm_power_off maybe overwrote
On Wed, Sep 17, 2014 at 12:03 PM, Will Deacon wrote:
> On Wed, Sep 17, 2014 at 12:56:07PM +0100, Robin Murphy wrote:
>> Commit 591c1e ("of: configure the platform device dma parameters)
>> introduced a common mechanism to configure DMA from DT properties.
>> AMBA devices created from DT can take a
On Wed, Sep 17, 2014 at 8:41 AM, Stephen Warren wrote:
> On 09/16/2014 05:51 PM, Andrew Bresticker wrote:
>>
>> On Tue, Sep 16, 2014 at 4:15 PM, Stephen Warren
>> wrote:
>>>
>>> On 09/16/2014 04:46 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 9:57 AM, Andrew Bresticker
On 16 September 2014 20:48, Geert Uytterhoeven wrote:
> While a PM domain can enable PM runtime management of its devices' module
> clocks by setting
>
> genpd->dev_ops.stop = pm_clk_suspend;
> genpd->dev_ops.start = pm_clk_resume;
>
> this also requires registering the clocks with
On Wed, Sep 17, 2014 at 12:56:07PM +0100, Robin Murphy wrote:
> Commit 591c1e ("of: configure the platform device dma parameters)
> introduced a common mechanism to configure DMA from DT properties.
> AMBA devices created from DT can take advantage of this, too.
>
> Signed-off-by: Robin Murphy
Hi Caesar,
On Wed, Sep 17, 2014 at 11:59:10AM +0800, Caesar Wang wrote:
> Thermal is TS-ADC Controller module supports
> user-defined mode and automatic mode.
>
> User-defined mode refers,TSADC all the control signals entirely by
> software writing to register for direct control.
>
> Automaic mo
On 18:55-20140917, Sebastian Reichel wrote:
> On Wed, Sep 17, 2014 at 08:44:00AM -0700, Lee Jones wrote:
> > On Wed, 17 Sep 2014, Nishanth Menon wrote:
> > > ti,system-power-controller is more or less the standard way of
> > > indicating that the PMIC is the system wide
On Tuesday 16 September 2014 10:32 AM, Vivek Gautam wrote:
> Currently the DP_PHY_ENABLE register is mapped in the driver,
> and accessed to control power to the PHY.
> With mfd-syscon and regmap interface available at our disposal,
> it's wise to use that instead of using a 'reg' property for th
On Wed, Sep 17, 2014 at 08:44:00AM -0700, Lee Jones wrote:
> On Wed, 17 Sep 2014, Nishanth Menon wrote:
> > ti,system-power-controller is more or less the standard way of
> > indicating that the PMIC is the system wide power controller and hence
> > may be used to switch off the system. Almost ALL
On Thu, 11 Sep 2014, Boris BREZILLON wrote:
> The GPBR block provides a set of battery-backed registers that can be used
> to save data which need to be kept when the system is powered down and
> VDD-core is maintained by an external battery.
>
> A typical usage is the RTT block (when used as an
On 17/09/14 17:29, Ajay kumar wrote:
> Hi Tomi,
>
> Thanks for your comments.
>
> On Wed, Sep 17, 2014 at 5:22 PM, Tomi Valkeinen wrote:
>> On 27/08/14 17:39, Ajay Kumar wrote:
>>> Add documentation for DT properties supported by ps8622/ps8625
>>> eDP-LVDS converter.
>>>
>>> Signed-off-by: Ajay
Sorry for top posting...in a keynote. I have a patch that does this I have sent
to APM separately for testing something else. Assuming that works, they can
send on or I will today.
--
Computer Architect | Sent from my #ARM Powered Mobile device
On Sep 17, 2014 9:04 AM, Catalin Marinas wrote:
On Wed, Sep 17, 2014 at 03:30:49PM +0100, Michal Simek wrote:
> From: Peter Crosthwaite
>
> Modern TTC implementations can extend the timer width to 32 bit. This
> feature is not self identifying so the driver needs to be made aware
> via device tree.
>
> Signed-off-by: Peter Crosthwaite
> Sign
On Tue, 26 Aug 2014, Lee Jones wrote:
> On Mon, 25 Aug 2014, Bjorn Andersson wrote:
>
> > Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660,
> > 8960 and 8064 based devices. The binding currently describes the rpm
> > itself and the regulator subnodes.
> >
> > Signed-off-by
On 09/17/2014 12:43 AM, Linus Walleij wrote:
On Wed, Sep 3, 2014 at 10:05 AM, Grygorii Strashko
wrote:
This series intended to integrate Keystone 2 DSP GPIO controller functionality
into gpio-syscon driver (drivers/gpio/gpio-syscon.c) as requested
by Linus Walleij in [1].
OK no comments on D
On Tue, Sep 16, 2014 at 09:02:11PM +0100, Tanmay Inamdar wrote:
> On Fri, Sep 12, 2014 at 2:18 AM, Liviu Dudau wrote:
> > On Thu, Sep 11, 2014 at 11:57:43PM +0100, Tanmay Inamdar wrote:
> >> This patch adds the AppliedMicro X-Gene SOC PCIe host controller driver.
> >> X-Gene PCIe controller suppor
On Tue, Sep 16, 2014 at 10:13:27PM +0800, Chen-Yu Tsai wrote:
> >> + /*
> >> + * sun8i variant requires us to toggle an undocumented register,
> >> + * as seen in Allwinner's SDK.
> >
> > The BSP I have has this:
> >
> > static void sunxi_dma_hw_init(struct sunxi_dmadev *dev)
> > {
>
On Wed, 17 Sep 2014, Nishanth Menon wrote:
> ti,system-power-controller is more or less the standard way of
> indicating that the PMIC is the system wide power controller and hence
> may be used to switch off the system. Almost ALL TI PMIC drivers and
> many Maxim PMIC drivers follow the same styl
On 09/16/2014 05:51 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 4:15 PM, Stephen Warren wrote:
On 09/16/2014 04:46 PM, Andrew Bresticker wrote:
On Tue, Sep 16, 2014 at 9:57 AM, Andrew Bresticker
wrote:
On Tue, Sep 16, 2014 at 8:26 AM, Stephen Warren
wrote:
On 09/15/2014 01:30 P
On Sep 17, 2014, at 1:56 AM, Ganapatrao Kulkarni
wrote:
> From: Ganapatrao Kulkarni
>
> This patch adds property "nid" to memory node to provide the memory range to
> numa node id mapping.
>
> Signed-off-by: Ganapatrao Kulkarni
>
> —
Adding the PPC guys as they’ve been doing NUMA on IBM P
On 16 September 2014 23:56, Hauke Mehrtens wrote:
> This driver is used by the bcm53xx ARM SoC code. Now it is possible to
> give the address of the chipcommon core in device tree and bcma will
> search for all the other cores.
Did you get any answer from Arend about detecting IRQs?
If not:
Aren
On Wed, Sep 17, 2014 at 12:56:07PM +0100, Robin Murphy wrote:
> Commit 591c1e ("of: configure the platform device dma parameters)
> introduced a common mechanism to configure DMA from DT properties.
> AMBA devices created from DT can take advantage of this, too.
>
> Signed-off-by: Robin Murphy
I
On 08:39-20140903, Nishanth Menon wrote:
> On 08/19/2014 08:54 AM, Nishanth Menon wrote:
> > From: Lucas Weaver
> >
> > DRA74x and DRA72x family of processors vary slightly in the number
> > of CPUs. So, add different instances of PMU for each of these processor
> > groups. Further, since the int
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