Hi Boris,
On Mon, Aug 18, 2014 at 07:26:26PM +0200, Boris BREZILLON wrote:
> This patch series adds support for the sunxi NAND Flash Controller (NFC)
> block.
>
> These two patches only add support for the basic NAND stuff:
> - NAND controller operations
> - SW and HW ECC handling (with both sy
On Thursday 18 September 2014, Liviu Dudau wrote:
>
> Add of_pci_get_domain_nr() to retrieve the PCI domain number
> of a given device from DT. If the information is not present,
> the function can be requested to allocate a new domain number.
>
> Cc: Bjorn Helgaas
> Cc: Arnd Bergmann
> Cc: Gra
On Friday 19 September 2014, Bjorn Helgaas wrote:
> On Thu, Sep 18, 2014 at 02:30:25AM +0100, Liviu Dudau wrote:
> PCI_IOBASE is a virtual address. So PCI_IOBASE + res->start is also a
> virtual address (only for IORESOURCE_IO).
>
> Since res->start is normally a *physical* address, I think it w
On Thursday 18 September 2014, Liviu Dudau wrote:
> This is needed for calls into OF code that parses PCI ranges.
> It signals support for memory mapped PCI I/O accesses that
> are described be device trees.
>
> Cc: Russell King
> Cc: Arnd Bergmann
> Cc: Rob Herring
> Reviewed-by: Catalin Marin
On Fri, 19 Sep 2014, Tony Lindgren wrote:
> * Thomas Gleixner [140919 12:47]:
> > Why on earth are you wanting tasklets in there? That's just silly,
> > really.
>
> Lack of a framework on driver side to cope with this in a generic
> way? :p
So instead of creating such a thing we rather have a co
On 09/17/2014 08:30 PM, Liviu Dudau wrote:
> Introduce a default implementation for remapping PCI bus I/O resources
> onto the CPU address space. Architectures with special needs may
> provide their own version, but most should be able to use this one.
>
> Cc: Bjorn Helgaas
> Cc: Arnd Bergmann
>
On 09/19/2014 04:06 PM, Bjorn Helgaas wrote:
> On Thu, Sep 18, 2014 at 02:30:23AM +0100, Liviu Dudau wrote:
>> Provide a function to parse the PCI DT ranges that can be used to
>> create a pci_host_bridge structure together with its associated
>> bus.
>>
>> Cc: Bjorn Helgaas
>> Cc: Arnd Bergmann
On Fri, Sep 19, 2014 at 1:47 AM, Mark yao wrote:
> diff --git a/include/uapi/drm/rockchip_drm.h b/include/uapi/drm/rockchip_drm.h
> new file mode 100644
> index 000..8f8e60e
> --- /dev/null
> +++ b/include/uapi/drm/rockchip_drm.h
> @@ -0,0 +1,97 @@
> +/*
> + *
> + * Copyright (c) Fuzhou Rockch
On Tue, Sep 16, 2014 at 03:33:41PM -0700, Tanmay Inamdar wrote:
> This patch adds the AppliedMicro X-Gene SOC PCIe host controller driver.
> X-Gene PCIe controller supports maximum up to 8 lanes and GEN3 speed.
> X-Gene SOC supports maximum 5 PCIe ports.
>
> Reviewed-by: Liviu Dudau
> Signed-off-
Hi Suravee,
On Thu, Sep 18 2014 at 03:14:46 AM, "suravee.suthikulpa...@amd.com"
wrote:
> From: Suravee Suthikulpanit
>
> ARM GICv2m specification extends GICv2 to support MSI(-X) with
> a new set of register frame. This patch introduces support for
> the non-secure GICv2m register frame. Curren
On Thu, Sep 18, 2014 at 02:30:15AM +0100, Liviu Dudau wrote:
> This is my version 11 of the attempt at adding support for generic PCI host
> bridge controllers that make use of device tree information to
> configure themselves. It contains minor cleanups compared with v10 to address
> the existing
On Thu, Sep 18, 2014 at 02:30:25AM +0100, Liviu Dudau wrote:
> Introduce a default implementation for remapping PCI bus I/O resources
> onto the CPU address space. Architectures with special needs may
> provide their own version, but most should be able to use this one.
I see that this is used by
On Thu, Sep 18 2014 at 03:14:45 AM, "suravee.suthikulpa...@amd.com"
wrote:
> From: Suravee Suthikulpanit
>
> This patch implelments the ARM64 version of arch_setup_msi_irqs(),
> which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
>
> Cc: Mark Rutland
> Cc: Marc Zyngier
> Cc: Jason Co
On Thu, Sep 18, 2014 at 02:30:23AM +0100, Liviu Dudau wrote:
> Provide a function to parse the PCI DT ranges that can be used to
> create a pci_host_bridge structure together with its associated
> bus.
>
> Cc: Bjorn Helgaas
> Cc: Arnd Bergmann
> Cc: Grant Likely
> Cc: Rob Herring
> Cc: Catalin
On Thu, Sep 18, 2014 at 02:30:22AM +0100, Liviu Dudau wrote:
> Add of_pci_get_domain_nr() to retrieve the PCI domain number
> of a given device from DT. If the information is not present,
> the function can be requested to allocate a new domain number.
Is of_pci_get_domain_nr() used somewhere? If
On Thu, Sep 18, 2014 at 02:30:19AM +0100, Liviu Dudau wrote:
> The ranges property for a host bridge controller in DT describes
> the mapping between the PCI bus address and the CPU physical address.
> The resources framework however expects that the IO resources start
> at a pseudo "port" address
On Thu, Sep 18, 2014 at 02:30:17AM +0100, Liviu Dudau wrote:
> Some architectures do not have a simple view of the PCI I/O space
> and instead use a range of CPU addresses that map to bus addresses.
> For some architectures these ranges will be expressed by OF bindings
> in a device tree file.
>
>
Dear Sebastian Hesselbarth,
On Fri, 19 Sep 2014 22:14:39 +0200, Sebastian Hesselbarth wrote:
> Armada XP pinctrl node gained an alias, make use of it.
>
> Signed-off-by: Sebastian Hesselbarth
Acked-by: Thomas Petazzoni
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel an
Dear Sebastian Hesselbarth,
On Fri, 19 Sep 2014 22:14:38 +0200, Sebastian Hesselbarth wrote:
> In other MVEBU SoCs, the pin controller node is called pin-ctrl with
> its base address added. Also, we have a node alias to access the pinctrl
> node easily. Fix this for Armada XP pinctrl nodes to be c
Dear Sebastian Hesselbarth,
On Fri, 19 Sep 2014 22:14:37 +0200, Sebastian Hesselbarth wrote:
> All current Armada XP SoCs have their pin controller at 0x18000/0x38.
> Move the common properties of pinctrl nodes to armada-xp.dtsi to allow
> to share pinctrl settings later.
>
> Signed-off-by: Sebas
Chris,
On Fri, Sep 19, 2014 at 1:02 AM, Chris Zhong wrote:
> Document the st-pwm regulator
>
> Signed-off-by: Chris Zhong
>
> ---
>
> Changes in v3:
> Adviced by Doug Anderson
> - update the Example
>
> Changes in v2:
> Adviced by Lee Jones
> - rename the documentation
> Adviced by Doug Anderson
Chris,
On Fri, Sep 19, 2014 at 1:02 AM, Chris Zhong wrote:
> Get voltage & duty table from device tree might be better, other platforms
> can also use this
> driver without any modify.
>
> Signed-off-by: Chris Zhong
>
> ---
>
> Changes in v3:
> Adviced by Doug Anderson
> - Make Kconfig & Makefi
Hello everyone,
Today I cobbled together a rudimentary devicetree major mode for
emacs. At this point it's pretty much limited to rather basic syntax
highlighting but works fairly well all things considered. It can be
found on Github[1]. Patches are of course quite welcome.
Please CC me on repli
Pinctrl settings for GE0 and GE1 are not only usable on RD-AXPWiFiAP.
Moreover, naming the RGMII settings pmx-ge{0,1} is not precise enough
as there is also a GMII setting for GE0.
Move the pinctrl sub-nodes to the common pinctrl node and rename them
to pmx-ge{0,1}-rgmii.
Signed-off-by: Sebastian
In other MVEBU SoCs, the pin controller node is called pin-ctrl with
its base address added. Also, we have a node alias to access the pinctrl
node easily. Fix this for Armada XP pinctrl nodes to be consistent with
other SoCs.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew L
Armada XP pinctrl node gained an alias, make use of it.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Ezequiel Garcia
Cc: Thomas Petazzoni
Cc: devicetree@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.
All current Armada XP SoCs have their pin controller at 0x18000/0x38.
Move the common properties of pinctrl nodes to armada-xp.dtsi to allow
to share pinctrl settings later.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Ezequiel Garcia
Cc: T
Lenovo ix4-300d has two ethernet PHYs connected via RGMII. Add the
corresponding pinctrl settings.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Ezequiel Garcia
Cc: Thomas Petazzoni
Cc: Benoit Masson
Cc: devicetree@vger.kernel.org
Cc: linu
There is a GMII setting for GE0, add it to the common pinctrl node.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Ezequiel Garcia
Cc: Thomas Petazzoni
Cc: devicetree@vger.kernel.org
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@
There is an I2C eeprom connected on Lenovo ix4-300d, add the
corresponding node.
Signed-off-by: Sebastian Hesselbarth
---
IIRC, the eeprom contains some register init pairs (address, data) for
and is empty otherwise. I'll have to check the boot loader code again,
but (again) IIRC, stock u-boot al
There is only one 74hc595 connected to GPIO but two were given
in the registers-number property. Fix it up.
Signed-off-by: Sebastian Hesselbarth
---
Cc: Jason Cooper
Cc: Andrew Lunn
Cc: Gregory Clement
Cc: Ezequiel Garcia
Cc: Thomas Petazzoni
Cc: Benoit Masson
Cc: devicetree@vger.kernel.org
Guys,
this is a patch set preparing barebox support for ix4-300d. As usual,
I stumbled upon a few nice-to-haves before actually touching ix4-300d
dts. As it is a mach-mvebu thing, I just added the related mailing
lists instead of each of the DT maintainers.
First 5 patches consolidate SoC-specifi
* Thomas Gleixner [140919 12:47]:
> On Fri, 19 Sep 2014, Tony Lindgren wrote:
> > * Thomas Gleixner [140919 10:37]:
> > >From hardware point of view the wake-up events behave like interrupts
> > and could also be used as the only interrupt in some messed up cases.
> > That avoids all kinds of cus
Per NVidia, this clock rate should be around 70MHz in
order to properly sample reads on data lane 0. In order
to achieve this rate, we need to reparent the clock from
clk_m which can only achieve 12MHz. Add parent_lp to the
dts bindings and set the parent & rate on init.
Signed-off-by: Sean Paul
This patch adds the lp_parent clk to the dsi node for
tegra114. The TRM states that PLLP should be used
upstream of the low power dsi clock.
Signed-off-by: Sean Paul
---
arch/arm/boot/dts/tegra114.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra1
Add documentation for device-tree binding of arm PXA 27x udc (usb
device) driver.
Signed-off-by: Robert Jarzmik
Cc: devicetree@vger.kernel.org
---
Since V1: change OF id mrvl,pxa27x_udc -> marvell,pxa27x-udc
This is a consequence of other DT reviews on the marvell
namings.
Si
Add support for device-tree device discovery. If devicetree is not
provided, fallback to legacy platform data "discovery".
Signed-off-by: Robert Jarzmik
Cc: devicetree@vger.kernel.org
---
Since V1: change OF id mrvl,pxa27x_udc -> marvell,pxa27x-udc
This is a consequence of other DT rev
On Fri, 19 Sep 2014, Tony Lindgren wrote:
> * Thomas Gleixner [140919 10:37]:
> >From hardware point of view the wake-up events behave like interrupts
> and could also be used as the only interrupt in some messed up cases.
> That avoids all kinds of custom APIs from driver point.
>
> The re-entra
* Thomas Gleixner [140919 10:37]:
> On Fri, 19 Sep 2014, Nishanth Menon wrote:
> > On 08:37-20140919, Thomas Gleixner wrote:
> > > The other omap drivers using this have the same issue ... And of
> > > course they are subtly different.
> > >
> > > The
On Sep 18, 2014, at 3:52 AM, Archit Taneja wrote:
> Add compatible string for BAM v1.3.0 in the DT bindings documentation.
> Mentioned
> a few more SoCs which have BAM v1.4.0 in them.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Archit Taneja
> ---
> Documentation/devicetree/bindings/d
Hi Ulf,
On Fri, Sep 19, 2014 at 08:27:33PM +0200, Ulf Hansson wrote:
> Changes in v5:
> - Converted dev_pm_domain_detach() to a void function
> - Added a ->detach() callback to the PM domain struct, invoked from the
> dev_pm_domain_detach().
> - Make ACPI and genpd both a
Hi Rob,
On 06/22/2014 10:40 PM, Santosh Shilimkar wrote:
On Friday 20 June 2014 03:46 PM, Rob Herring wrote:
On Fri, Jun 20, 2014 at 2:02 PM, Santosh Shilimkar
wrote:
On Friday 20 June 2014 02:56 PM, Arnd Bergmann wrote:
On Friday 20 June 2014 13:17:43 Santosh Shilimkar wrote:
+
The ->detach() callback for the PM domain has now been fully adopted,
thus there no users left of the acpi_dev_pm_detach() API. This allow us
to convert it into a static function.
Signed-off-by: Ulf Hansson
---
drivers/acpi/device_pm.c | 69
inclu
From: Tomasz Figa
This patch moves Exynos PM domain code to use the new generic PM domain
look-up framework introduced in previous patches, thus also allowing
the new code to be compiled with CONFIG_ARCH_EXYNOS.
This patch was originally submitted by Tomasz Figa when he was employed
by Samsung.
AMBA devices may on some SoCs resides in PM domains. To be able to
manage these devices from there, let's try to attach devices to their
corresponding PM domain during the probe phase.
To reverse these actions at the remove phase, we try to detach the
device from its PM domain.
Signed-off-by: Ulf
Previously only the ACPI PM domain was supported by the i2c bus.
Let's convert to the common attach/detach functions for PM domains,
which currently means we are extending the support to include the
generic PM domain as well.
Cc: linux-...@vger.kernel.org
Signed-off-by: Ulf Hansson
Reviewed-by:
Previously only the ACPI PM domain was supported by the sdio bus.
Let's convert to the common attach/detach functions for PM domains,
which currently means we are extending the support to include the
generic PM domain as well.
Cc: linux-...@vger.kernel.org
Signed-off-by: Ulf Hansson
Reviewed-by:
Previously only the ACPI PM domain was supported by the platform bus.
Let's convert to the common attach/detach functions for PM domains,
which currently means we are extending the support to include the
generic PM domain as well.
Signed-off-by: Ulf Hansson
Tested-by: Philipp Zabel
Reviewed-by:
Previously only the ACPI PM domain was supported by the spi bus.
Let's convert to the common attach/detach functions for PM domains,
which currently means we are extending the support to include the
generic PM domain as well.
Cc: linux-...@vger.kernel.org
Signed-off-by: Ulf Hansson
Reviewed-by:
As as preparation to simplify the detachment of devices from their PM
domains, we assign the ->detach() callback to genpd_dev_pm_detach().
Signed-off-by: Ulf Hansson
---
drivers/acpi/device_pm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_
The intent of this callback is to simplify detachment of devices from
their PM domains. Further patches will show the benefit.
Signed-off-by: Ulf Hansson
---
include/linux/pm.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 72c0fe0..ef4e16f 1006
To maintain scalability let's add common methods to attach and detach
a PM domain for a device, dev_pm_domain_attach|detach().
Typically dev_pm_domain_attach() shall be invoked from subsystem level
code at the probe phase to try to attach a device to its PM domain.
The reversed actions may be done
From: Tomasz Figa
This patch introduces generic code to perform PM domain look-up using
device tree and automatically bind devices to their PM domains.
Generic device tree bindings are introduced to specify PM domains of
devices in their device tree nodes.
Backwards compatibility with legacy Sa
Changes in v5:
- Converted dev_pm_domain_detach() to a void function
- Added a ->detach() callback to the PM domain struct, invoked from the
dev_pm_domain_detach().
- Make ACPI and genpd both assign the ->detach() callback at successfull
attachment.
Please discard this and before resend. Sorry.
I've used bad domain for linux-arm-kernel list...
The next one is ok.
best regards
Janusz
W dniu 2014-09-19 20:08, Janusz Uzycki pisze:
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line
Hi ARM SoC maintainers,
this is the push forward for DT on the ARM RealView boards.
I've tried to fix up the patches and get ACKs from the maintainers
as far as possible.
Outstanding issue: no ACK from LED maintainers Bryan Wu or
Richard Purdie on the syscon LED stuff. I have requested this
early
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the AUART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the CTS/RTS/
Enables PPS support in mxs-auart serial driver to make PPS API working.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index c2f24f8..9381732 100644
--
When using mxs-auart based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there,
this patch just simply enable it.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers
Handle CTS/DSR/RI/DCD GPIO interrupts in mxs-auart.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 146 ++-
1 file changed, 143 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 4690200..c2
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the AUART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the CTS/RTS/
When using mxs-auart based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there,
this patch just simply enable it.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers
Handle CTS/DSR/RI/DCD GPIO interrupts in mxs-auart.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 146 ++-
1 file changed, 143 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 4690200..c2
Enables PPS support in mxs-auart serial driver to make PPS API working.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index c2f24f8..9381732 100644
--
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the AUART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the CTS/RTS/
Enables PPS support in mxs-auart serial driver to make PPS API working.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index c2f24f8..9381732 100644
--
Handle CTS/DSR/RI/DCD GPIO interrupts in mxs-auart.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 146 ++-
1 file changed, 143 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 4690200..c2
When using mxs-auart based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there,
this patch just simply enable it.
Signed-off-by: Janusz Uzycki
---
drivers/tty/serial/mxs-auart.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers
On Fri, 19 Sep 2014, Nishanth Menon wrote:
> On 08:37-20140919, Thomas Gleixner wrote:
> > The other omap drivers using this have the same issue ... And of
> > course they are subtly different.
> >
> > The uart one handles the actual device interrupt, which is violat
On Fri, Sep 5, 2014 at 7:53 AM, Weike Chen wrote:
> This patch enables suspend and resume mode for the power management, and
> it is based on Josef Ahmad's previous work.
>
> Reviewed-by: Hock Leong Kweh
> Reviewed-by: Shevchenko, Andriy
> Signed-off-by: Weike Chen
(...)
> +/* Store GPIO cont
Hi,
thanks for the submission.
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-hix5hd2.c
> @@ -0,0 +1,573 @@
> +/*
> + * Copyright (c) 2014 Linaro Ltd.
> + * Copyright (c) 2014 Hisilicon Limited.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the te
Hi Ming Lei,
On Thu, Sep 18, 2014 at 8:08 PM, Ming Lei wrote:
> Hi Tanmay,
>
> On Wed, Sep 17, 2014 at 6:33 AM, Tanmay Inamdar wrote:
>> This patch adds support for AppliedMicro X-Gene PCIe host controller. The
>> driver is tested on X-Gene platform with different gen1/2/3 PCIe endpoint
>> cards
On Fri, Sep 19, 2014 at 11:25:50AM -0500, Josh Cartwright wrote:
> On Thu, Sep 18, 2014 at 08:41:43PM -0700, Guenter Roeck wrote:
> > On 09/18/2014 08:24 PM, Josh Cartwright wrote:
> > >On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote:
> > >>On 09/18/2014 03:26 PM, Josh Cartwright wrot
On Wed, Sep 17, 2014 at 09:53:12AM +0100, Joerg Roedel wrote:
> Hi Will,
Hello Joerg,
> On Mon, Sep 08, 2014 at 05:51:36PM +0100, Will Deacon wrote:
> > On Fri, Sep 05, 2014 at 11:52:56AM +0100, Joerg Roedel wrote:
> > > From: Joerg Roedel
> > >
> > > Cc: Will Deacon
> > > Signed-off-by: Joerg
On Thu, Sep 18, 2014 at 04:08:03PM +0800, Josh Wu wrote:
> On 9/18/2014 8:32 AM, Brian Norris wrote:
> >On Mon, Aug 18, 2014 at 03:08:40PM +0800, Josh Wu wrote:
> >>+static int pmecc_build_galois_table(int mm,
> >>+ int16_t *index_of, int16_t *alpha_to)
> >>+{
...
> >>+}
> >Is this algori
On Thu, Sep 18, 2014 at 08:41:43PM -0700, Guenter Roeck wrote:
> On 09/18/2014 08:24 PM, Josh Cartwright wrote:
> >On Thu, Sep 18, 2014 at 07:41:17PM -0700, Guenter Roeck wrote:
> >>On 09/18/2014 03:26 PM, Josh Cartwright wrote:
> >>>Add a driver for the watchdog timer block found in the Krait Proc
On 08:37-20140919, Thomas Gleixner wrote:
> On Thu, 18 Sep 2014, Nishanth Menon wrote:
> > On 17:57-20140918, Thomas Gleixner wrote:
> >
> > I suppose I can improve the commit message to elaborate this better?
> > Will that help?
>
> You also want to improve the
On Thu, 18 Sep 2014, Nishanth Menon wrote:
> On 17:57-20140918, Thomas Gleixner wrote:
>
> I suppose I can improve the commit message to elaborate this better?
> Will that help?
You also want to improve the comment in the empty handler.
> >
> > > + */
> > > + return IRQ_NONE;
And it still doe
--
Goede dag,
We zijn Diamond Zwitserse lening bedrijf geven van leningen per
post advertentie. Wij bieden verschillende soorten leningen (korte en
lange termijn leningen, persoonlijke leningen, leningen aan bedrijven
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2014-09-19 15:47 GMT+02:00 Joe.C :
> On Fri, 2014-09-19 at 19:48 +0800, srv_hongzhou.y...@mediatek.com wrote:
>> +
>> +static const struct pinmux_ops mt_pmx_ops = {
>> + .get_functions_count= mt_pmx_get_funcs_cnt,
>> + .get_function_name = mt_pmx_get_func_name,
>> + .get_functi
On 19/09/14 16:59, Ajay kumar wrote:
> I am not really able to understand, what's stopping us from using this
> bridge on a board with "complex" display connections. To use ps8622 driver,
> one needs to "attach" it to the DRM framework. For this, the DRM driver
Remember that when we talk about DT
On Fri, Sep 19, 2014 at 01:30:56PM +0100, Robert Richter wrote:
> On 16.09.14 20:49:18, Andrew Bresticker wrote:
> > > Robert Richter (6):
> > > dts, arm64: Add dtbs_install make target
> > > dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
> > > dts, arm/arm64: Remove dtbs buil
On 09/19/2014 04:24 PM, Tomi Valkeinen wrote:
On 17/09/14 10:51, Jyri Sarha wrote:
On 09/17/2014 04:06 AM, Dave Airlie wrote:
On 17 September 2014 06:40, Jyri Sarha wrote:
Changes since v2:
- Change compatible property from "ti,gpio-clock" to
"ti,gpio-gate-clock"
- Some minor cleanups
The co
On Fri, Sep 19, 2014 at 6:24 PM, Tomi Valkeinen wrote:
> On 18/09/14 08:50, Ajay kumar wrote:
>
Why do we need a complex graph when it can be handled using a simple
phandle?
>>>
>>> Maybe in your case you can handle it with simple phandle. Can you
>>> guarantee that it's enough for ever
Am Freitag, 19. September 2014, 19:48:26 schrieb
srv_hongzhou.y...@mediatek.com:
> From: Hongzhou Yang
>
> Add devicetree bindings for Mediatek SoC pinctrl driver.
>
> Signed-off-by: Hongzhou Yang
> ---
> .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 92
> ++ 1 file
On 15/09/14 05:17, li.xi...@freescale.com wrote:
> Hi Tomi,
>
> Thanks very much for your comments.
>
>
>> Subject: Re: [PATCH] fbdev: fsl-sii902x: HDMI support for Freescale SoCs
>>
>> Hi,
>>
>> On 05/09/14 07:48, Xiubo Li wrote:
>>> Some Freescale SoCs, there has an DVI/HDMI controller and a P
On 19/09/14 16:12, Nishanth Menon wrote:
> On 09/19/2014 08:07 AM, Tomi Valkeinen wrote:
>> On 16/09/14 23:40, Jyri Sarha wrote:
>>> The added ti,gpio-gate-clock is a basic clock that can be enabled and
>>> disabled trough a gpio output. The DT binding document for the clock
>>> is also added. For
On 17/09/14 10:51, Jyri Sarha wrote:
> On 09/17/2014 04:06 AM, Dave Airlie wrote:
>> On 17 September 2014 06:40, Jyri Sarha wrote:
>>> Changes since v2:
>>> - Change compatible property from "ti,gpio-clock" to
>>> "ti,gpio-gate-clock"
>>> - Some minor cleanups
>>>
>>> The code has a functional dep
On Mon, Aug 25, 2014 at 07:45:38PM +0200, Stephen Warren wrote:
> On 08/07/2014 05:01 PM, Tuomas Tynkkynen wrote:
> > Some mach-specific drivers that don't require their own node in the device
> > tree
> > (for example drivers/soc/*, cpufreq, cpuidle etc.) want to match on the
> > device
> > tree
On 09/19/2014 08:07 AM, Tomi Valkeinen wrote:
> On 16/09/14 23:40, Jyri Sarha wrote:
>> The added ti,gpio-gate-clock is a basic clock that can be enabled and
>> disabled trough a gpio output. The DT binding document for the clock
>> is also added. For EPROBE_DEFER handling the registering of the cl
Hi
On Mon, Sep 8, 2014 at 10:43 AM, Boris BREZILLON
wrote:
[snip]
> +static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
> + if (ret)
> + return ret;
> +
> + re
On 16/09/14 23:40, Jyri Sarha wrote:
> The added ti,gpio-gate-clock is a basic clock that can be enabled and
> disabled trough a gpio output. The DT binding document for the clock
> is also added. For EPROBE_DEFER handling the registering of the clock
> has to be delayed until of_clk_get() call tim
Hi
On Fri, Sep 19, 2014 at 7:47 AM, Mark yao wrote:
[snip]
> +static int rockchip_drm_bind(struct device *dev)
> +{
> + return drm_platform_init(&rockchip_drm_driver,
> to_platform_device(dev));
Please avoid drm_platform_*() usage. We're about to drop all the
drm_bus midlayers. See the te
On 09/19/2014 04:48 AM, Lokesh Vutla wrote:
> +linux-omap, linux-arm-kernel, devicetree
> On Friday 19 September 2014 03:16 PM, Lokesh Vutla wrote:
>> On some Soc's RTC is powered by an external power regulator.
>> e.g. RTC on DRA7 SoC. Make the OMAP RTC driver support a
>> power regulator.
>> And
On 18/09/14 08:50, Ajay kumar wrote:
>>> Why do we need a complex graph when it can be handled using a simple
>>> phandle?
>>
>> Maybe in your case you can handle it with simple phandle. Can you
>> guarantee that it's enough for everyone, on all platforms?
> Yes, as of now exynos5420-peach-pit an
On Rockchip RK3188 SoCs the platform driver emac_rockchip is used. This variant
driver
enables this regulator when the device driver is loaded. The phy no longer needs
to be always on.
Signed-off-by: Romain Perier
---
arch/arm/boot/dts/rk3188-radxarock.dts | 1 -
1 file changed, 1 deletion(-)
On 16.09.14 20:49:18, Andrew Bresticker wrote:
> > Robert Richter (6):
> > dts, arm64: Add dtbs_install make target
> > dts, kbuild: Factor out dtbs install rules to Makefile.dtbinst
> > dts, arm/arm64: Remove dtbs build rules in sub-makes
> > dts, kbuild: Implement support for dtb vendor
Hi Kiran,
On Fri, 2014-09-19 at 15:49 +0530, Kiran Padwal wrote:
> Hi Ivan,
>
> On Thursday 18 September 2014 06:45 PM, Ivan T. Ivanov wrote:
> > The current ADC is peripheral of Qualcomm SPMI PMIC chips. It has
> > 16 bits resolution and register space inside PMIC accessible across
> > SPMI bus
Naveen Krishna Chatradhi wrote:
>
> Add initial device tree nodes for EXYNOS7 SoC and board dts file
> to support Espresso board based on Exynos7 SoC.
>
> Signed-off-by: Naveen Krishna Chatradhi
> Cc: Rob Herring
> Cc: Catalin Marinas
Looks good to me,
Acked-by: Kukjin Kim
Thanks,
Kukjin
On 19/09/14 05:04, Joe.C wrote:
> This is v3 of adding basic device tree support for MT8127 & MT8135.
> This series is based on Matthias' pull request for mediatek support [1]
>
> We are planning to upstream drivers for MT8127 & MT8135 SoCs.
> MT8135 is a tablet soc featuring 2 CA7 + 2 CA15. MT8
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