add qe node to ls1021atwr fdt.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/arm/boot/dts/ls1021a-twr.dts | 24 +++
arch/arm/boot/dts/ls1021a.dtsi| 64 +++
2 files changed, 88 insertions(+)
diff --git
On Friday 10 October 2014 10:22:34 Y Vo wrote:
APM: There are 6 GPIOs which can support IRQ, they are fixed to use
external IRQ from XGIC. (The XGIC is based on the ARM Generic
Interrupt Controller Architecture Specification, Architecture version
2.0, The XGIC provides the mechanism to
Hi Kumar,
As I've understand from Kevin's letter, we can submit the DT only
platforms addition also for 3.18.
Can we please have this one applied?
Thanks!
On 10/01/14 19:09, Mike Rapoport wrote:
CM-QS600 is a APQ8064 based computer on module.
The details are available at
According to the RK3066 and RK3188 TRM, the two SPI controllers support DMA
handshake interface. Add the DMA properties so they can be used when needed.
Signed-off-by: Julien CHAUVEAU julien.chauv...@neo-technologies.fr
---
arch/arm/boot/dts/rk3xxx.dtsi | 4
1 file changed, 4 insertions(+)
Ping. Any objections? Thanks
On Tue, Sep 30, 2014 at 10:17 PM, Marek Belisko ma...@goldelico.com wrote:
Following series add support to tsc2007 touchscreen driver for
pre-calibration,
flipping and rotation. Added bindings are documented and used in gta04 device
tree.
Marek Belisko (3):
On Thursday 09 October 2014 15:44:25 Scott Branden wrote:
From: Jonathan Richardson jonat...@broadcom.com
Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.
Reviewed-by: Ray Jui r...@broadcom.com
On Thursday 09 October 2014 15:44:31 Scott Branden wrote:
Enabled Broadcom Cygnus SoC family in multi_v7_defconfig by using
CONFIG_ARCH_BCM_CYGNUS=y.
Signed-off-by: Scott Branden sbran...@broadcom.com
---
arch/arm/configs/multi_v7_defconfig |1 +
1 file changed, 1 insertion(+)
diff
On Thursday 09 October 2014 15:44:29 Scott Branden wrote:
+
+ lcpll: lcpll@0301d02c {
+ #clock-cells = 0;
+ compatible = brcm,cygnus-lcpll-clk;
+ reg = 0x0301d02c 0x1c;
+ clocks = osc;
+
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing to register for direct control.
Automaic mode refers to the module automatically poll TSADC output,
and the results were
This series patchs tested on rk3288 SDK board and pinky-v1,v2 board.
I believe the driver can be used on the rk3288-evb board.
Add this driver, The system can reset the entire chip when
the thermal temperture over 120C, In case of rising over 125C
when tha hardware shorting,The sodftware will
This patch changes a dtsi file to contain the thermal data
on RK3288 and later SoCs. This data will
enable a thermal shutdown over 125C.
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
---
arch/arm/boot/dts/rk3288-thermal.dtsi | 57 +++
1 file changed, 57
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng z...@rock-chips.com
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
---
.../bindings/thermal/rockchip-thermal.txt | 45 ++
1 file changed, 45
when a thermal temperature over TSHUT.Default to via
CRU reset the entire chip on rk3288-evb Board
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
---
arch/arm/boot/dts/rk3288-evb.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi
This patch is depend on rk3288-thermal.dtsi,or
it will compile error.
If the temperature over a period of time High,over 120C
the resulting TSHUT gave CRU module,let it reset
the entire chip,or via GPIO give PMIC.
Signed-off-by: Caesar Wang caesar.w...@rock-chips.com
---
When using mxs-auart based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there,
this patch just simply enable it.
Signed-off-by: Janusz Uzycki j.uzy...@elproma.com.pl
---
Changes from v1 (the initial version of the patch):
* the patch was
The regulation_constraints structure includes specific field to support
suspend state for global PMIC SUSPEND/HIBERNATE mode. This patch add support
for parsing regulator_state for suspend state.
Cc: Mark Brown broo...@kernel.org
Cc: Liam Girdwood lgirdw...@gmail.com
Signed-off-by: Chanwoo Choi
This patch add sleep mode of regulator for exynos3250-rinato board to optimize
power-consumption in sleep state.
The power-consumption in suspend state is 0.6mA after applied this patch.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin
On Fri, Oct 10, 2014 at 8:13 AM, Janusz Uzycki j.uzy...@elproma.com.pl wrote:
When using mxs-auart based console, sometime we need the sysrq function
to help debugging kernel. The sysrq code is basically there,
this patch just simply enable it.
Signed-off-by: Janusz Uzycki
The regulators would set different state/mode according to the kind of suspend
state. So regulation_constraints structure has already regulator suspend state
filed.
This patch parse regulator suspend state from devicetree file.
I tested this patch on Rinato board (Samsung Gear 2) included
This patch add regulator suspend state to constraint in dt file. The regulation_
constraints structure already has regulator suspend state field as following.
The regulator suspend state control the state of regulator according to
PM (Power Management) state.
- struct regulator_state state_disk
-
On Tue, Oct 7, 2014 at 8:43 PM, PERIER Romain romain.per...@gmail.com wrote:
This is not the final location, I have no idea exactly where I might
put this helper function. This is why I ask you your opinion (and
also, this is why that's a proposal)
2014-10-07 21:45 GMT+02:00 Romain Perier
On Fri, Oct 10, 2014 at 12:47:08PM +0100, Grant Likely wrote:
This is an extremely simple wrapper. It may be best to simply make it
a static inline. It is also generic enough that I don't have a problem
with it living in include/linux/of.h; but of_regulator.h would be fine
too.
I think of.h
What I'm more concerned about is the semantics of the property. What
do the generic code paths gain by standardizing this property? Is it
expected that
We really need to come up with a standard property for this and document
it rather than continuing to add individual device specific
Hi Grant,
Am Freitag, 10. Oktober 2014, 12:47:08 schrieb Grant Likely:
What I'm more concerned about is the semantics of the property. What
do the generic code paths gain by standardizing this property? Is it
expected that
[seems to be missing some text in the original mail]
We currently see
Hello,
because Mikko's internship is over and he's short of time these days, I have
taken his patches witht he intention of moving this work forward.
It depends on Thierry's MC patches at [0] and a branch can be found at [1]. So
far it has been tested only on a Jetson TK1.
The comments from
From: Mikko Perttunen mperttu...@nvidia.com
This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main Jetson TK1 device tree.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso
From: Mikko Perttunen mperttu...@nvidia.com
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
.../bindings/memory-controllers/tegra-emc.txt | 41
From: Mikko Perttunen mperttu...@nvidia.com
Implements functionality needed to change the rate of the memory bus clock.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
drivers/memory/Kconfig | 10 +
drivers/memory/Makefile |1 -
From: Mikko Perttunen mperttu...@nvidia.com
This adds a node for the EMC memory controller. It is always enabled, but only
provides read-only functionality without board-specific timing tables.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt
This series is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
DECON(Display and Enhancement Controller) is the new IP
in exynos7 SOC for generating video signals using pixel data.
DECON driver can be used to drive 2
On Wed, Oct 8, 2014 at 12:39 PM, Thierry Reding
thierry.red...@gmail.com wrote:
On Tue, Oct 07, 2014 at 05:49:24PM +0300, Laurent Pinchart wrote:
Hi Ajay,
On Tuesday 07 October 2014 16:06:55 Ajay kumar wrote:
On Tue, Oct 7, 2014 at 4:00 PM, Tomi Valkeinen wrote:
On 20/09/14 14:22, Ajay
On Fri, Oct 10, 2014 at 01:46:55PM +0100, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
On Thu, Oct 09, 2014 at 04:19:47PM +0100, Javier Martinez Canillas wrote:
Hello Mark,
On 10/09/2014 12:27 PM, Mark Rutland wrote:
Well, is not fairly obvious to me. One can also say the opposite, why the
kernel is documenting a DT binding that is not (currently) implemented?
Hi Suravee,
On Sun, Sep 28, 2014 at 09:53:27PM +0100, suravee.suthikulpa...@amd.com wrote:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform
To check: how is it possible to make use of a DTB generated from this
dts? Can a user
On Thu, Oct 09, 2014 at 11:51:43AM +0100, Arnd Bergmann wrote:
[...]
Last changes where introduced by commit 8c05cd08a, whose commit log adds
to my confusion:
[...] I think what we want here is for pci_start to be 0 when mmap_api ==
PCI_MMAP_PROCFS.[...]
But that's not what the
On Thu, 9 Oct 2014, Steffen Trumtrar wrote:
Hi Steffen,
Hi!
On Thu, Oct 09, 2014 at 09:57:49AM -0500, atull wrote:
On Thu, 9 Oct 2014, Steffen Trumtrar wrote:
On Thu, Oct 09, 2014 at 08:16:18AM -0500, Dinh Nguyen wrote:
Hi Philipp,
On 10/9/14, 4:03 AM, Philipp Zabel
Enables PPS support in mxs-auart serial driver to make PPS API working.
Signed-off-by: Janusz Uzycki j.uzy...@elproma.com.pl
---
v3 - v4 changelog:
* coding style: braces in both branches of condition
v2 - v3 changelog:
* no changes
---
drivers/tty/serial/mxs-auart.c | 11 +++
1 file
Handle CTS/DSR/RI/DCD GPIO interrupts in mxs-auart.
Signed-off-by: Janusz Uzycki j.uzy...@elproma.com.pl
---
v3 - v4 changelog:
* rebased
v2 - v3 changelog:
* introduces mctrl_prev instead of removed ctrl
* mxs_auart_modem_status() moved from [3/4]
* mxs_auart_modem_status() interrupt_enabled
Russell King:
The only thing which the .get_mctrl method is supposed to do is
to return the state of the /input/ lines, which are CTS, DCD, DSR, RI.
The output line state is stored in port-mctrl, and is added to
the returned value by serial_core when it's required.
RTS output state should not be
It contains improved version of the old v3 patchset
[PATCH v3] serial: mxs-auart: gpios as modem signals (dirty)
v3 - v4 changelog:
[PATCH 1/4] serial: mxs-auart: clean get_mctrl and set_mctrl
* renamed from serial: mxs-auart: ctrl removed from mxs_auart_port
* mxs_auart_get_mctrl() read back RTS
Dedicated CTS and RTS pins are unusable together with a lot of other
peripherals because they share the same line. Pinctrl is limited.
Moreover, the AUART controller doesn't handle DTR/DSR/DCD/RI signals,
so we have to control them via GPIO.
This patch permits to use GPIOs to control the
On Tue, Sep 2, 2014 at 8:40 AM, Georgi Djakov gdja...@mm-sol.com wrote:
Enable support for the two SD host controllers on the APQ8084 platform
by adding the required nodes to the DT files.
On the IFC6540 board, the first controller is connected to the onboard
eMMC and the second is connected
Hi Matt,
On Thu, Oct 09, 2014 at 09:23:02PM -0700, Matt Ranostay wrote:
@@ -63,7 +60,25 @@ struct cap11xx_priv {
struct input_dev *idev;
/* config */
- unsigned short keycodes[CAP11XX_NUM_CHN];
+ unsigned int num_channels;
+ u32 keycodes[];
Any particular reason
Hi Caesar,
On Fri, Oct 10, 2014 at 06:19:37PM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing to register for direct control.
Automaic mode
HI,
On Thu, Oct 09, 2014 at 09:06:22PM +0200, Johan Hovold wrote:
This series fixes a few issues with the omap rtc-driver, cleans up a bit
and finally adds support for the PMIC control feature found in some
revisions of this RTC IP block.
Ultimately, this allows for powering off the
On Thu, Oct 09, 2014 at 09:06:23PM +0200, Johan Hovold wrote:
Make sure not to reset the clock-source configuration when enabling the
32kHz clock mux.
Until the clock source can be configured through device tree we must not
overwrite settings made by the bootloader (e.g. clock-source
On Thu, Oct 09, 2014 at 09:06:24PM +0200, Johan Hovold wrote:
The platform device must be registered as wakeup capable before
registering the class device, or the wakealarm attribute will not be
created.
Also make sure to unregister the wakeup source on probe errors.
Fixes: 1d2e2b65d098
On Thu, Oct 09, 2014 at 09:06:27PM +0200, Johan Hovold wrote:
Remove redundant debug message.
The corresponding error has already been logged by rtc core.
Signed-off-by: Johan Hovold jo...@kernel.org
Reviewed-by: Felipe Balbi ba...@ti.com
---
drivers/rtc/rtc-omap.c | 6 ++
1 file
On Thu, Oct 09, 2014 at 09:06:25PM +0200, Johan Hovold wrote:
Make sure not to register the class device until after it has been
configured and interrupt handlers registered at probe.
Currently, the device is not fully configured (e.g. 24-hour mode) when
the class device is registered,
On Thu, Oct 09, 2014 at 09:06:28PM +0200, Johan Hovold wrote:
Use dev_info and dev_dbg rather than pr_info and pr_debug.
Signed-off-by: Johan Hovold jo...@kernel.org
thanks!
Reviewed-by: Felipe Balbi ba...@ti.com
---
drivers/rtc/rtc-omap.c | 19 +--
1 file changed, 9
On Thu, Oct 09, 2014 at 09:06:29PM +0200, Johan Hovold wrote:
Some legacy RTC IP revisions has a power-up reset flag in the status
register that later revisions lack.
As this flag is always read back as set on later revisions (or is
overloaded with a different flag), make sure to only clear
On Thu, Oct 09, 2014 at 09:06:26PM +0200, Johan Hovold wrote:
Remove register-base define, which is no longer used.
Signed-off-by: Johan Hovold jo...@kernel.org
Reviewed-by: Felipe Balbi ba...@ti.com
---
drivers/rtc/rtc-omap.c | 2 --
1 file changed, 2 deletions(-)
diff --git
Hi,
On Thu, Oct 09, 2014 at 09:06:30PM +0200, Johan Hovold wrote:
Make sure to restore local irq state when reading the timer/calendar
(TC) registers, so that omap_rtc_read_time() can be called with
interrupts disabled.
Signed-off-by: Johan Hovold jo...@kernel.org
---
On Fri, Oct 10, 2014 at 01:00:54PM -0500, Felipe Balbi wrote:
On Thu, Oct 09, 2014 at 09:06:29PM +0200, Johan Hovold wrote:
Some legacy RTC IP revisions has a power-up reset flag in the status
register that later revisions lack.
As this flag is always read back as set on later revisions
Hi,
On Thu, Oct 09, 2014 at 09:06:31PM +0200, Johan Hovold wrote:
@@ -124,11 +138,18 @@
*/
#define OMAP_RTC_HAS_POWER_UP_RESET BIT(3)
+/*
+ * Some RTC IP revisions can control an external PMIC via the pmic_power_en
+ * pin.
+ */
+#define OMAP_RTC_HAS_PMIC_MODE BIT(4)
On Thu, Oct 09, 2014 at 09:06:32PM +0200, Johan Hovold wrote:
The ALARM interrupt must not be disabled during shutdown in order to be
able to power up the system using an RTC alarm.
Signed-off-by: Johan Hovold jo...@kernel.org
nicely done!
Reviewed-by: Felipe Balbi ba...@ti.com
---
On Fri, 2014-10-10 at 14:49 +0800, Zhao Qiang wrote:
add qe node to ls1021atwr fdt.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
arch/arm/boot/dts/ls1021a-twr.dts | 24 +++
arch/arm/boot/dts/ls1021a.dtsi| 64
+++
2 files changed,
On Thu, Oct 09, 2014 at 09:06:33PM +0200, Johan Hovold wrote:
Enable am33xx specific RTC features (e.g. PMIC control) by adding
ti,am3352-rtc to the compatible property of the rtc node.
Signed-off-by: Johan Hovold jo...@kernel.org
Reviewed-by: Felipe Balbi ba...@ti.com
---
On Thu, Oct 09, 2014 at 09:06:34PM +0200, Johan Hovold wrote:
Configure the RTC as system-power controller, which allows the system to
be powered off as well as woken up again on subsequent RTC alarms.
Note that the PMIC needs to be put in SLEEP (rather than OFF) mode to
maintain RTC power.
The rk3288 has several iommus. Each iommu belongs to a single master
device. There is one device (ISP) that has two slave iommus, but that
case is not yet supported by this driver.
At subsys init, the iommu driver registers itself as the iommu driver for
the platform bus. The master devices
On Friday 10 October 2014 14:58:04 Lorenzo Pieralisi wrote:
On Thu, Oct 09, 2014 at 11:51:43AM +0100, Arnd Bergmann wrote:
Last changes where introduced by commit 8c05cd08a, whose commit log adds
to my confusion:
[...] I think what we want here is for pci_start to be 0 when
Add binding documentation for Rockchip IOMMU.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Signed-off-by: Simon Xue x...@rock-chips.com
---
.../devicetree/bindings/iommu/rockchip,iommu.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644
Add device nodes for the VOP iommus.
Device nodes for other iommus will be added in later patches.
The iommu nodes use the #iommu-cells property as described in:
Documentation/devicetree/bindings/iommu/iommu.txt
Signed-off-by: Daniel Kurtz djku...@chromium.org
Signed-off-by: Simon Xue
From: Iyappan Subramanian isubraman...@apm.com
Date: Thu, 9 Oct 2014 18:32:01 -0700
Adding 10GbE support to APM X-Gene SoC ethernet driver.
v4: Address comments from v3
* dtb: resolved merge conflict for the net tree
v3: Address comments from v2
* dtb: changed to use all-zeros for the
On 14-10-10 02:50 AM, Arnd Bergmann wrote:
On Thursday 09 October 2014 15:44:25 Scott Branden wrote:
From: Jonathan Richardson jonat...@broadcom.com
Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.
On 14-10-10 03:08 AM, Arnd Bergmann wrote:
On Thursday 09 October 2014 15:44:29 Scott Branden wrote:
+
+ lcpll: lcpll@0301d02c {
+ #clock-cells = 0;
+ compatible = brcm,cygnus-lcpll-clk;
+ reg = 0x0301d02c 0x1c;
+
On 14-10-10 02:59 AM, Arnd Bergmann wrote:
On Thursday 09 October 2014 15:44:31 Scott Branden wrote:
Enabled Broadcom Cygnus SoC family in multi_v7_defconfig by using
CONFIG_ARCH_BCM_CYGNUS=y.
Signed-off-by: Scott Branden sbran...@broadcom.com
---
arch/arm/configs/multi_v7_defconfig |1 +
Adding SGMII based 1GbE basic support to APM X-Gene SoC ethernet driver.
v1:
* Initial version
---
Iyappan Subramanian (3):
dtb: Add SGMII based 1GbE node to APM X-Gene SoC device tree
drivers: net: xgene: Add SGMII based 1GbE support
drivers: net: xgene: Add SGMII based 1GbE ethtool
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
.../net/ethernet/apm/xgene/xgene_enet_ethtool.c| 25 +++---
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
arch/arm64/boot/dts/apm-mustang.dts | 4
arch/arm64/boot/dts/apm-storm.dtsi | 24
2 files changed, 28 insertions(+)
diff --git
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
drivers/net/ethernet/apm/xgene/Makefile | 2 +-
drivers/net/ethernet/apm/xgene/xgene_enet_hw.c| 1 -
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h| 2 +-
The TPS65217C used on the boneblack defaults to 1.5v on startup for dcdc1_reg.
While 1.35v ddr3 memory is actually used. This was discovered by a user during
a schematic review of his beaglebone-black clone, a u-boot patch will also also
be submitted.
Signed-off-by: Robert Nelson
No just an oversight..
Thanks,
Matt
On Fri, Oct 10, 2014 at 10:29 AM, Dmitry Torokhov
dmitry.torok...@gmail.com wrote:
Hi Matt,
On Thu, Oct 09, 2014 at 09:23:02PM -0700, Matt Ranostay wrote:
@@ -63,7 +60,25 @@ struct cap11xx_priv {
struct input_dev *idev;
/* config */
-
Hi Linus,
Here are the device tree changes I have queued up for v3.18. Pretty
small set this time. Please pull.
g.
The following changes since commit fe82dcec644244676d55a1384c958d5f67979adb:
Linux 3.17-rc7 (2014-09-28 14:29:07 -0700)
are available in the git repository at:
This patch add intmem node des which is needed by platsmp.c
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- remove 'enable-method' from this patch
- add compitable name rockchip,rk3288-pmu-sram for pmu-intmem
Changes in v2:
This patch add pmu reference and enable-method for smp
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- add this patch
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
We use the rockchip,rk3066-pmu for rk3288 instead of creat
a new one.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
Changes in v3:
- add this patch in version 3
Changes in v2: None
arch/arm/boot/dts/rk3288.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
rk3288 is qual-core CPU Soc, we enable the smp in this patch.
In version 3 we use regmap and pmu syscon for cpu power on/off.
This should be work after Pankaj Dubey's patch applied:
(https://lkml.org/lkml/2014/9/30/156)
Changes in v3:
- add pmu regmap patches in version 3
- use one ops and
Iyappan Subramanian isubraman...@apm.com :
[...]
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
index c8f3824..63ea194 100644
--- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
+++
For the CA12/CA17 MPCore multiprocessor, the active processors might be
stalled when the individual processor is powered down.
For rk3288, we can avoid this prolbem by softreset the processor before
power it down.
Kever Yang (2):
ARM: rockchip: fix up rk3288 smp cpu hotplug
ARM: dts:
This patch add reset for CPU nodes to use the reset controller.
Signed-off-by: Kever Yang kever.y...@rock-chips.com
---
arch/arm/boot/dts/rk3288.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 5e9c56d..291014d
On 21/09/14 13:17, Jonathan Cameron wrote:
On 16/09/14 09:58, Naveen Krishna Chatradhi wrote:
Changes since v1:
1. Rebased on top of togreg branch of IIO git.
This patch set does the following
1. Use the syscon and Regmap API instead of ioremappaing the
ADC_PHY register from PMU.
2.
Changes from v5:
* Removed redundant num_channel from the private structure
Matt Ranostay (3):
cap11xx: make driver generic for variant support
cap11xx: Add support for various cap11xx devices
cap11xx: support for irq-active-high option
.../devicetree/bindings/input/cap1106.txt
Several other variants of the cap11xx device exists with a varying
number of capacitance detection channels. Add support for creating
the channels dynamically.
Signed-off-by: Matt Ranostay mranos...@gmail.com
---
.../devicetree/bindings/input/cap11xx.txt | 3 +-
Some applications need to use the irq-active-high push-pull option.
This allows it be enabled in the device tree child node.
Signed-off-by: Matt Ranostay mranos...@gmail.com
---
Documentation/devicetree/bindings/input/cap11xx.txt | 4
drivers/input/keyboard/cap11xx.c| 8
cap1106 driver can support much more one device make the driver
generic for support of similar parts.
Signed-off-by: Matt Ranostay mranos...@gmail.com
---
.../devicetree/bindings/input/cap1106.txt | 53
.../devicetree/bindings/input/cap11xx.txt | 54
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