On Fri, Oct 24, 2014 at 7:41 PM, Yoshihiro Shimoda
wrote:
> Since the PHY of USB3.0 and EHCI/OHCI ch2 are the same, the USB3.0
> driver cannot use the phy driver when the EHCI/OHCI ch2 already used it:
>
> phy phy-e6590100.usb-phy.3: phy init failed --> -16
> xhci-hcd: probe of ee00.usb failed
Hi,
Just a ping for this patch.
Best Regards,
Josh Wu
On 10/11/2014 6:01 PM, Josh Wu wrote:
From: Josh Wu
If there is no PMECC lookup table stored in ROM, or lookup table offset is
not specified, PMECC driver should build it in DDR by itself.
That make the PMECC driver work for some board w
Dear Sirs,
Missed the first paragraph, sorry for extra mail.
This series is the first version of Mediatek SoCs I2C controller common
bus driver, it is Request for Comment.
Because the clock driver for mediatek SoC is not ready yet(still work in
progress), so I delete the related clock code in dts
On Tue, Oct 28, 2014 at 11:26:21AM +, Qais Yousef wrote:
> +
> +/* Register I/F */
> +#define AXD_REG_VERSION
> 0x
> +#define AXD_REG_CONFIG0
> 0x0004
> +#define AXD_REG_CONFIG1
On Wed, Oct 29, 2014 at 10:50:19AM +0800, Greg Kroah-Hartman wrote:
> On Tue, Oct 28, 2014 at 03:05:16PM +, Qais Yousef wrote:
> > On 10/28/2014 02:13 PM, Greg Kroah-Hartman wrote:
> > >On Tue, Oct 28, 2014 at 01:18:28PM +, Qais Yousef wrote:
> > >>On 10/28/2014 11:55 AM, Clemens Ladisch wr
On Tue, Oct 28, 2014 at 10:13:48PM +0800, Greg Kroah-Hartman wrote:
> On Tue, Oct 28, 2014 at 01:18:28PM +, Qais Yousef wrote:
> > On 10/28/2014 11:55 AM, Clemens Ladisch wrote:
> > >Qais Yousef wrote:
> > >>AXD Audio Processing IP performs audio decoding, encoding, mixing,
> > >>equalisation,
On Tue, Oct 28, 2014 at 01:18:28PM +, Qais Yousef wrote:
> On 10/28/2014 11:55 AM, Clemens Ladisch wrote:
> >Qais Yousef wrote:
> >>AXD Audio Processing IP performs audio decoding, encoding, mixing,
> >>equalisation,
> >>synchronisation and playback.
> >What exactly do you mean with "synchroni
On Wed, Oct 29, 2014 at 7:27 AM, Andrew Bresticker
wrote:
> This series adds support for xHCI on NVIDIA Tegra SoCs. This includes:
> - patches 1 and 2: adding a driver for the mailbox used to communicate
>with the xHCI controller's firmware,
> - patches 3 and 4: extending the XUSB pad contr
Add I2C node to mt8135.dtsi and mt8127.dtsi
Signed-off-by: Xudong Chen
---
arch/arm/boot/dts/mt8127.dtsi | 27 +++
arch/arm/boot/dts/mt8135.dtsi | 51 +++
2 files changed, 78 insertions(+)
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/a
Add devicetree bindings for Mediatek Soc I2C driver.
Signed-off-by: Xudong Chen
---
.../devicetree/bindings/i2c/i2c-mt6577.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-mt6577.txt
diff --git a/Documentatio
The mediatek SoCs have I2C controller that handle I2C transfer.
This patch include common I2C bus driver.
This driver is compatible with I2C controller on mt65xx/mt81xx.
Signed-off-by: Xudong Chen
Change-Id: Icc17e326b9df46a226d536956e103f17b0382b6e
---
drivers/i2c/busses/Kconfig | 9 +
d
This driver is based on 3.18-rc1 & Hongzhou's gpio patch.
MTK I2C HW has some limitation.
1. If the i2c_msg number is more than one, STOP will be issued instead of
RS(Repeat Start) between each message.
Such as: "START + ADDR + DATA_n + STOP + START + ADDR + DATA_n + STOP ..."
2. Mediatek I2C con
Julien,
On Tue, Oct 28, 2014 at 3:36 AM, Julien CHAUVEAU
wrote:
> According to the I2C bus specification, it is required to use pull-up
> resistors
> on the clock and data lines. Probing the I2C busses with i2cdetect results in
> bad results when no devices are connected and no external resistor
On Thu, Oct 23, 2014 at 7:31 AM, Kevin Cernekee wrote:
>> I think we'd just have to add a noearlycon option instead if we made
>> it the default. It's never been the default before, so I don't think
>> we should change now. There's also an implicit requirement that the
>> bootloader has configured
A couple of accesses to IRQEN (base+0x00) just used "base" directly, so
they would break if IRQEN ever became nonzero. Make sure that all
reads/writes specify the register offset constant.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-bcm7120-l2.c | 6 +++---
1 file changed, 3 insertion
The irq-brcmstb-l2 driver has a single dependency on the ARM code, the
do_bad_IRQ macro. Expand this macro in-place so that the driver can be
built on non-ARM platforms.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-brcmstb-l2.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(
This keeps things consistent between the "core" bcm7120-l2 driver and the
helpers in generic-chip.c.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-bcm7120-l2.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchi
This check may be prone to race conditions, e.g.
1) Some external event (e.g. GPIO level) causes an IRQ to become pending
2) Peripheral asserts the L2 IRQ
3) CPU takes an interrupt
4) The event from #1 goes away
5) bcm7120_l2_intc_irq_handle() reads back a 0 status
Unlike the hardware supported b
This can compile for MIPS (or anything else) now.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6f0e80b..6a03c65 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconf
The cached value already incorporates irq_fwd_mask, and was saved the
last time an IRQ was enabled/disabled.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-bcm7120-l2.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drive
Some chips, such as BCM6328, only require the former driver. Some
BCM7xxx STB configurations only require the latter driver. Treat them
as two separate entities, and update the mach-bcm dependencies to
reflect the change.
Signed-off-by: Kevin Cernekee
---
arch/arm/mach-bcm/Kconfig| 1 +
This mask should have been 0x_, not 0x0fff_.
The change should not have an effect on current users (STB) because bits
31:27 are unused.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-bcm7120-l2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqc
Most implementations of the bcm7120-l2 controller only have a single
32-bit enable word + 32-bit status word. But some instances have added
more enable/status pairs in order to support 64+ IRQs (which are all
ORed into one parent IRQ input). Make the following changes to allow
the driver to suppo
This change was just made on bcm7120-l2, so let's keep things consistent
between the two drivers.
Signed-off-by: Kevin Cernekee
---
drivers/irqchip/irq-brcmstb-l2.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/dri
On big-endian systems readl/writel may perform an unwanted endian swap,
breaking generic-chip.c. Let the platform code opt to use the __raw_
variants by selecting RAW_IRQ_ACCESSORS.
This is required in order for bcm3384 to use GENERIC_IRQ_CHIP. Several
existing irqchip drivers also use the __raw
在 2014年10月29日 07:46, Dmitry Torokhov 写道:
On Tue, Oct 28, 2014 at 04:51:24PM +0800, Caesar Wang wrote:
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
Added.
Thank you!
Dmitry,
Fixed and sent in patch v16.
在 2014年10月29日 07:46, Dmitry Torokhov 写道:
Hi Caesar,
On Tue, Oct 28, 2014 at 04:51:23PM +0800, Caesar Wang wrote:
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals enti
On Tue, Oct 28, 2014 at 03:05:16PM +, Qais Yousef wrote:
> On 10/28/2014 02:13 PM, Greg Kroah-Hartman wrote:
> >On Tue, Oct 28, 2014 at 01:18:28PM +, Qais Yousef wrote:
> >>On 10/28/2014 11:55 AM, Clemens Ladisch wrote:
> >>>Qais Yousef wrote:
> AXD Audio Processing IP performs audio de
Thermal is TS-ADC Controller module supports
user-defined mode and automatic mode.
User-defined mode refers,TSADC all the control signals entirely by
software writing to register for direct control.
Automaic mode refers to the module automatically poll TSADC output,
and the results were checked.I
This patch changes a dtsi file to contain the thermal data
on RK3288 and later SoCs. This data will
enable a thermal shutdown over 120C.
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
arch/arm/boot/dts/rk3288-thermal.dtsi | 65 +++
1 file changed, 65
This add the necessary binding documentation for the thermal
found on Rockchip SoCs
Signed-off-by: zhaoyifeng
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
.../bindings/thermal/rockchip-thermal.txt | 62 ++
1 file changed, 62 insertions(+)
create mod
This patch is depend on rk3288-thermal.dtsi,or
it will compile error.
If for some reason we are unable to shut it down
in orderly fashion (kernel is stuck holding a lock or
similar), then hardware TSHUT will reset it.
If the temperature over a period of time High,over 125C
the resulting TSHUT gav
when a thermal temperature over TSHUT.Default to via
CRU reset the entire chip on rk3288-evb Board,
TSHUT is low active on rk3288-evb board.
Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
---
arch/arm/boot/dts/rk3288-evb.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/ar
This series patchs tested on rk3288 SDK board and pinky-v1,v2 board.
I believe the driver can be used on the rk3288-evb board.
Add this driver, The system will shutdown when
the thermal temperture over 120C.If for some reason we are unable to
shut it down in orderly fashion (kernel is stuck holdin
On Wed, Oct 29, 2014 at 5:47 AM, Maxime Ripard
wrote:
> Hi Roman,
>
> Thanks for your patches
>
> On Mon, Oct 27, 2014 at 10:43:01PM +0100, Roman Byshko wrote:
>> The driver for sun4i USB phys currently supports
>> only phy1 and phy2 which are used for USB host
>> controllers. This patch adds supp
在 2014/10/28 7:39, Dmitry Torokhov 写道:
On Fri, Oct 24, 2014 at 09:44:31AM -0700, Dmitry Torokhov wrote:
Hi Jinkun,
On Fri, Oct 24, 2014 at 12:29:19AM -0700, jinkun.hong wrote:
+static int rockchip_pd_power(struct rockchip_domain *pd, bool power_on)
+{
+ int ret = 0;
+ struct rockc
Add device-tree support for the MIPS GIC. Update the GIC irqdomain's
xlate() callback to handle the three-cell specifier described in the
MIPS GIC binding document.
Signed-off-by: Andrew Bresticker
---
Changes from v2:
- rebased on GIC irqchip cleanups
- updated for change in bindings
- only
The Global Interrupt Controller (GIC) present on certain MIPS systems
can be used to route external interrupts to individual VPEs and CPU
interrupt vectors. It also supports a timer and software-generated
interrupts.
Signed-off-by: Andrew Bresticker
---
Changes from v2:
- added third cell to sp
ce drivers,
respectively.
Based on next-20141028, which includes part 1 [0] and part 2 [1] of my
GIC cleanup series.
Changes from v2:
- added back third cell to specifier to differentiate between shared and
local interrupts
- added timer sub-node and it's properties
- changed compatible string
Parse the GIC timer frequency and interrupt from the device-tree.
Signed-off-by: Andrew Bresticker
---
New for v3.
---
drivers/clocksource/Kconfig | 1 +
drivers/clocksource/mips-gic-timer.c | 37 +---
2 files changed, 31 insertions(+), 7 deletions(-)
d
Add the vendor prefix "mti" for MIPS Technologies, Inc.
Signed-off-by: Andrew Bresticker
---
I'll update the users of the "mips" prefix to use "mti" instead once
this lands.
No changes from v2.
New for v2.
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insert
On Tue, Oct 28, 2014 at 04:51:24PM +0800, Caesar Wang wrote:
> This add the necessary binding documentation for the thermal
> found on Rockchip SoCs
>
> Signed-off-by: zhaoyifeng
> Signed-off-by: Caesar Wang
Reviewed-by: Dmitry Torokhov
> ---
> .../bindings/thermal/rockchip-thermal.txt
Hi Caesar,
On Tue, Oct 28, 2014 at 04:51:23PM +0800, Caesar Wang wrote:
> Thermal is TS-ADC Controller module supports
> user-defined mode and automatic mode.
>
> User-defined mode refers,TSADC all the control signals entirely by
> software writing to register for direct control.
>
> Automaic mo
On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> Signed-off-by: Emil Medve
> Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
Please remove gerrit stuff prior to submitting.
> diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
> b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dts
Am Mittwoch, 29. Oktober 2014, 02:50:06 schrieb Daniel Kurtz:
> Heiko,
>
> Does this version work for you on 3.18-rc1?
the iommu and drm driver using it did probe sucessfully, so
Tested-by: Heiko Stuebner
>
> On Oct 27, 2014 8:44 PM, "Daniel Kurtz" wrote:
> > The rk3288 has several iommus.
On Wed, 2014-10-22 at 09:42 -0500, Emil Medve wrote:
> Signed-off-by: Emil Medve
> Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
> ---
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 17
> +++--
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/D
remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels.
Signed-off-by: Scott Branden
---
arch/arm/configs/bcm_defconfig |3 ++-
arch/arm/configs/multi_v7_def
Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.
Signed-off-by: Scott Branden
---
arch/arm/mach-bcm/Kconfig | 37 -
1 file changed, 16 insertions(+)
From: Jonathan Richardson
Reviewed-by: Arun Parameswaran
Tested-by: Jonathan Richardson
Reviewed-by: JD (Jiandong) Zheng
Reviewed-by: Ray Jui
Signed-off-by: Scott Branden
---
.../devicetree/bindings/arm/bcm/cygnus.txt | 31 ++
.../devicetree/bindings/clock/bcm-cygn
From: Ray Jui
Enable Broadcom Cygnus platform support in multi_v7_defconfig
Signed-off-by: Ray Jui
Signed-off-by: Scott Branden
---
arch/arm/configs/multi_v7_defconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/con
DT files to enable cygnus consisting on reference designs
and cygnus core configuration.
Reviewed-by: Ray Jui
Reviewed-by: Arun Parameswaran
Tested-by: Jonathan Richardson
Reviewed-by: JD (Jiandong) Zheng
Signed-off-by: Scott Branden
---
arch/arm/boot/dts/Makefile |4 ++
arc
From: Jonathan Richardson
Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Reviewed-by: Ray Jui
Reviewed-by: Desmond Liu
Reviewed-by: JD (Jiandong) Zheng
Tested-by: Jonathan Richardson
Signed-off-by: Scott Branden
---
arch/arm/mach-bcm/Kconfig | 32 +
From: Jonathan Richardson
This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC. It also enables
debug configs which should be disabled if optimal performance is
desired.
Tested-by: Jonathan Richardson
Reviewed-by: JD (Jiandong)
Acked-by: Jonathan Richardson
Signed-off-by: Scott Branden
---
MAINTAINERS | 14 ++
1 file changed, 14 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index dab92a7..15a3d89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2129,6 +2129,20 @@ L: linux-s...@vger.kernel.org
This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations f
On Fri, 2014-10-17 at 11:27 +0200, Valentin Longchamp wrote:
> With "fsl-i2c" compatibility the i2c frequency is not set
> correctly, because it sets no prescaler. According to the AN2919 from
> Freescale and the QorIQ (P2041) documentation, the source clock is 1/2
> the platform clock. This implie
The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface. While there is only a single
physical channel, messages sent by the controller can be divided
into two groups: those intended for the PHY driver and those intended
for the host-controller
On Mon, Oct 27, 2014 at 01:11:48PM +0100, Krzysztof Kozlowski wrote:
> Introduce simple helper for calculating the shift for OPMODE field in
> registers. This allows storing the current value of opmode in
> non-shifted form and simplifies a little set_suspend_disable and enable
> functions. Additio
On Mon, Oct 27, 2014 at 01:11:47PM +0100, Krzysztof Kozlowski wrote:
> Add defines for regulator operating modes which should be more readable,
> especially if one does not have Maxim 77686 datasheet.
Applied, thanks.
signature.asc
Description: Digital signature
On Mon, Oct 27, 2014 at 01:11:49PM +0100, Krzysztof Kozlowski wrote:
> @@ -247,6 +250,8 @@ static struct regulator_ops max77686_ldo_ops = {
> .set_voltage_sel= regulator_set_voltage_sel_regmap,
> .set_voltage_time_sel = regulator_set_voltage_time_sel,
> .set_suspend_mod
This series adds support for xHCI on NVIDIA Tegra SoCs. This includes:
- patches 1 and 2: adding a driver for the mailbox used to communicate
with the xHCI controller's firmware,
- patches 3 and 4: extending the XUSB pad controller driver to support
the USB PHY types (UTMI, HSIC, and USB3)
Assign USB ports previously owned by the EHCI controllers to the xHCI
controller. There is a mini-PCIe USB port (UTMI port 1) and a USB A
connector (UTMI port 2, USB3 port 0). PCIe lane 0 is used for USB3
port 0.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
Changes from v3:
Add nodes for the Tegra XUSB mailbox and Tegra xHCI controller and
add the PHY mailbox channel to the XUSB padctl node.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Dropped channel specifier from mailbox bindings.
- Added mbox-names pr
Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Added mbox-names property.
Changes from v1:
- Updated to use common mailbox bindings.
- Add
Add support for the on-chip xHCI host controller present on Tegra SoCs.
The driver is currently very basic: it loads the controller with its
firmware, starts the controller, and is able to service messages sent
by the controller's firmware. The hardware also supports device mode
as well as powerg
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
The xHCI controller will also send messages intended for the PHY driver,
so request and listen
Add new bindings used for USB support by the Tegra XUSB pad controller.
This includes additional PHY types, USB-specific pinconfig properties, etc.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
Changes from v2:
- Added nvidia,otg-hs-curr-level-offset property.
- Dropped "-ot
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
---
No changes from v3.
Changes from v2:
- Dropped channel specifier.
- Add
Assign ports previously owned by the EHCI controllers to the xHCI
controller. There are two external USB ports (UTMI ports 0/2 and
USB3 ports 0/1) and an internal USB port (UTMI port 1). PCIe lanes
0 and 1 are used by the USB3 ports.
Signed-off-by: Andrew Bresticker
Reviewed-by: Stephen Warren
Am 2014-10-26 15:57, schrieb Jingchang Lu:
>>> ---
>>> changes in v6:
>>> add dts patch description.
>>> remove '-' from QDS and TWR board dts name for consistence with u-boot.
>
>>I'm not sure it's a good idea. The most idiomatic DTS naming schema is
> just -.dts.
> Many our PowerPC platforms
On Tue, 28 Oct 2014, atull wrote:
> On Fri, 24 Oct 2014, Steffen Trumtrar wrote:
> >
> > > + - init-val : 0 if driver should disable bridge at startup
> > > +1 if driver should enable bridge at startup
> > > +driver leaves bridge in current state if
On Mon, Oct 27, 2014 at 10:43:02PM +0100, Roman Byshko wrote:
> Until now the regulator nodes for powering USB VBUS
> existed only for the two host controllers. Now the regulator
> is added for USB OTG too.
> ---
> arch/arm/boot/dts/sunxi-common-regulators.dtsi | 19 +++
> 1 file c
Hi Roman,
Thanks for your patches
On Mon, Oct 27, 2014 at 10:43:01PM +0100, Roman Byshko wrote:
> The driver for sun4i USB phys currently supports
> only phy1 and phy2 which are used for USB host
> controllers. This patch adds support for USB phy0,
> which is used by the musb hdrc USB controller.
On Tue, Oct 28, 2014 at 09:11:34PM +0300, Max Filippov wrote:
> On Tue, Oct 28, 2014 at 8:38 PM, Mark Brown wrote:
> > You *really* need to explain how it's supposed to work - right now it's
> > not at all obvious, like I say the fact that this is a rarely used idiom
> > is not helping. For exam
On Tuesday, October 28, 2014 04:26:25 PM Linus Walleij wrote:
> On Fri, Oct 17, 2014 at 2:11 PM, Rafael J. Wysocki wrote:
>
> > From: Mika Westerberg
> >
> > GPIO descriptors are the preferred way over legacy GPIO numbers
> > nowadays. Convert the driver to use GPIO descriptors internally but
>
On Fri, 24 Oct 2014, Steffen Trumtrar wrote:
> Hi!
>
Hi,
I see that my documentation sucks and needs cleanup. I'll try to
answer some of the flames and get a more coherent version out soon.
> On Thu, Oct 23, 2014 at 06:51:06PM -0500, at...@opensource.altera.com wrote:
> > From: Alan Tull
>
On Tue, 28 Oct 2014 09:36:33 +0100 Johan Hovold wrote:
> > But it doesn't explain *why* we want the alarm to trigger before
> > returning.
>
> Should we really require every power-off handler to document arch
> behaviour (even if its inconsistent and currently undocumented); in
> this case that
The pinctrl bindings / API allow you to specify that:
- a pin should be an output
- a pin should have its input path enabled / disabled
...but they don't allow you to tell a pin to stop outputting. Lets
add a new setting for that just in case the bootloader (or the default
state) left a pin as an
This patch adds overlay tests to the OF selftest.
It tests overlay device addition/removal and whether
the apply revert sequence is correct.
Changes since V1:
* Added local fixups entries.
Signed-off-by: Pantelis Antoniou
---
Documentation/devicetree/bindings/selftest.txt | 14 +
drivers/of/s
Introduce of_reconfig_get_state_change() which allows an of notifier
to query about device state changes.
Signed-off-by: Pantelis Antoniou
---
drivers/of/dynamic.c | 96
include/linux/of.h | 1 +
2 files changed, 97 insertions(+)
diff --gi
Add OF notifier handler needed for creating/destroying platform devices
according to dynamic runtime changes in the DT live tree.
Signed-off-by: Pantelis Antoniou
---
drivers/base/platform.c | 18 +--
drivers/of/platform.c | 78 +
inc
Add a runtime interface to using configfs for generic device tree overlay
usage.
A device-tree configfs entry is created in /config/device-tree/overlays
* To create an overlay you mkdir the directory:
# mkdir /config/device-tree/overlays/foo
* Either you echo the overlay firmware file t
Add OF notifier handler needed for creating/destroying i2c devices
according to dynamic runtime changes in the DT live tree.
Signed-off-by: Pantelis Antoniou
---
drivers/i2c/i2c-core.c | 79 +-
1 file changed, 78 insertions(+), 1 deletion(-)
diff
Dynamically inserting i2c client device nodes requires the use
of a single device registration method. Rework and export it.
Signed-off-by: Pantelis Antoniou
---
drivers/i2c/i2c-core.c | 99 +++---
include/linux/i2c.h| 10 +
2 files changed, 64
Add OF notifier handler needed for creating/destroying spi devices
according to dynamic runtime changes in the DT live tree.
Signed-off-by: Pantelis Antoniou
---
drivers/spi/spi.c | 78 ++-
1 file changed, 77 insertions(+), 1 deletion(-)
diff
Dynamically inserting spi device nodes requires the use of a single
device registration method. Rework and export it.
Methods to lookup a device/master using a device node are added
as well, of_find_spi_master_by_node() & of_find_spi_device_by_node().
Signed-off-by: Pantelis Antoniou
---
driver
Introduce DT overlay support.
Makes it possible to dynamically overlay a part of the kernel's
tree with another tree that's been dynamically loaded.
Removal of nodes and properties is also possible.
The hard part of applying and reverting the overlay is performed
using changesets.
Documentation
The following patchset introduces Device Tree overlays, a method
of dynamically altering the kernel's live Device Tree, along with
a generic interface to use it in a board agnostic manner.
It is against linux mainline as of today 28/10/2014
"f7e87a44ef60ad379e39b45437604141453bf0ec"
Merge tag 'med
The original resolver format is way too cryptic, switch
to using a tree based format that gets rid of repetitions,
is more compact and readable.
Signed-off-by: Pantelis Antoniou
---
drivers/of/resolver.c | 191 +++---
1 file changed, 165 insertions(+),
Update the selftests to using the new (and more readable) local
fixups format.
Signed-off-by: Pantelis Antoniou
---
drivers/of/testcase-data/testcases.dts | 61 +-
1 file changed, 37 insertions(+), 24 deletions(-)
diff --git a/drivers/of/testcase-data/testcases.d
Make sure we call notifier only when the node is attached.
When a detatched tree is being constructed we do not want the
notifiers to fire at all.
Signed-off-by: Pantelis Antoniou
---
drivers/of/base.c| 9 ++---
drivers/of/dynamic.c | 5 +
2 files changed, 7 insertions(+), 7 deletion
The notifier now includes the old_prop argument when updating
properties, propagate this API to changeset internals while
also retaining the old behaviour of retrieving the old_property
when NULL is passed.
Signed-off-by: Pantelis Antoniou
---
drivers/of/dynamic.c | 18 ++
drive
The following patch-series implements a number of fixes to the
dynamic DT handling of the kernel, and provides infrastructure that
the upcoming Device Tree Overlay patchset will use.
Pantelis Antoniou (5):
of: resolver: Switch to new local fixups format.
of: testcases: Update with new local fi
Hi Brian,
On Tue, 28 Oct 2014 11:13:11 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Tue, Oct 21, 2014 at 03:08:41PM +0200, Boris Brezillon wrote:
> > +static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
> > + struct nand_ecc_ctrl *ecc,
> > +
On Tuesday 28 October 2014 13:06:28 Scott Branden wrote:
> On 14-10-28 01:01 PM, Arnd Bergmann wrote:
> > On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
> >> From: Ray Jui
> >>
> >> Enable Broadcom Cygnus platform support in multi_v7_defconfig
> >>
> >> Signed-off-by: Ray Jui
> >> Signe
On 14-10-28 01:01 PM, Arnd Bergmann wrote:
On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
From: Ray Jui
Enable Broadcom Cygnus platform support in multi_v7_defconfig
Signed-off-by: Ray Jui
Signed-off-by: Scott Branden
Just to be sure: did you check that multi_v7_defconfig conta
On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
> From: Ray Jui
>
> Enable Broadcom Cygnus platform support in multi_v7_defconfig
>
> Signed-off-by: Ray Jui
> Signed-off-by: Scott Branden
>
Just to be sure: did you check that multi_v7_defconfig contains
all the drivers you need that
Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.
Signed-off-by: Scott Branden
---
arch/arm/mach-bcm/Kconfig | 37 -
1 file changed, 16 insertions(+)
remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels.
Signed-off-by: Scott Branden
---
arch/arm/configs/bcm_defconfig |3 ++-
arch/arm/configs/multi_v7_def
DT files to enable cygnus consisting on reference designs
and cygnus core configuration.
Reviewed-by: Ray Jui
Reviewed-by: Arun Parameswaran
Tested-by: Jonathan Richardson
Reviewed-by: JD (Jiandong) Zheng
Signed-off-by: Scott Branden
---
arch/arm/boot/dts/Makefile |4 ++
arc
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