This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
for kernel boot as following:
- PLL/MMC/UART/MCT/I2C/SPI
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC
based on Octal core CPUs (quad Cortex-A57 and quad Cortex-A53).
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c |
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc: Linus Walleij
Signed-off-by: Chanwoo Choi
Acked-by: Geuns
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
d
This patch add binding documentation for Exynos5433 clock controller.
Exynos5433 has various clock domains So, this documentation explains
the detailed clock domains ans usage guide.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
--
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock contro
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and use
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Ac
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos5433 SoC.
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Chanwoo Choi
Acked-by: Geunsik Lim
Acked-by: Inki Dae
---
arch/arm64/Kconfig | 10 ++
1 file changed, 10 insertions(+)
diff --git a/
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must n
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
d
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergma
From: Jaehoon Chung
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim
Cc: Mark Rutland
Cc: Arnd Bergmann
Cc: Olof Johansson
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Jaehoon Chu
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drivers/clk/samsung/clk-exynos5433.c | 285 ++
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
drive
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Acked-by: Geunsik Lim
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
[ideal.song: Change clk flags of to pclk_gpio_* c
On Thu, Nov 20, 2014 at 9:37 PM, Vincent Yang
wrote:
> Driver for Fujitsu MB86S7x SoCs that have a memory mapped GPIO controller.
>
> Signed-off-by: Andy Green
> Signed-off-by: Jassi Brar
> Signed-off-by: Vincent Yang
> Signed-off-by: Tetsuya Nuriya
> ---
> .../bindings/gpio/fujitsu,mb86s70-g
On 4 November 2014 at 04:35, Suman Anna wrote:
> The OMAP mailbox driver and its existing clients (remoteproc
> for OMAP4+) are adapted to use the generic mailbox framework.
>
> The main changes for the adaptation are:
> - The tasklet used for Tx is replaced with the state machine from
> the
On 2014年11月27日 10:12, Dave Airlie wrote:
Hi Dave
Do you mean that I need send you a branch, based on drm-next, merge with
iommu tree and rockchip drm?
Yes, grab drm-next, git pull the arm/rockchip branch from Joerg's
tree, put rockchip drm
patches on top, send me pull request.
I'll valid
Hi Dave
this pull request is for rockchip drm v14, based on Joerg's iommu
arm/rockchip branch.
The following changes since commit 656d7077d8ffd1c2492d4a0a354367ab2e545059:
dt-bindings: iommu: Add documentation for rockchip iommu (2014-11-03
17:29:09 +0100)
are available in the git re
On Wed, 2014-11-26 at 19:39 -0800, Greg KH wrote:
> Are you going to resend a changed version of this?
Yes, I've been distracted by a few other things, but I suppose I should
do it :-)
Possibly tomorrow. Arnd, are you doing that helper you suggested to get
to the of_node or should I ?
Cheers,
B
Hi Sudeep,
On 26 November 2014 at 22:30, Sudeep Holla wrote:
> On 26/11/14 08:46, Viresh Kumar wrote:
>> We only need to have one entry in cpus@cpu0 node which will match with
>> drivers
>> name.
> This seems fundamentally broken as the driver always needs to
> unconditionally refer to cpu0. Fur
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v12:
- Minor fixes
- Added Reviewed-by
Changes since v11:
- Address review comments on
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
On 26 November 2014 at 22:04, santosh shilimkar
wrote:
> Its really not 'dvfs-method' but really the actual driver which you
> want to probe. Also we should just have one global way to parse
> DT vs non-DT cpufreq drivers. In other words, instead of matching
> multiple driver strings for different
On 26 November 2014 at 22:08, Sudeep Holla wrote:
>
>
> On 26/11/14 16:20, Jassi Brar wrote:
>>
>> On 26 November 2014 at 19:30, Sudeep Holla wrote:
>>>
>>> On 26/11/14 05:37, Jassi Brar wrote:
>>
>> It seems you still don't get my point that the driver should
>> manage
This commit adds support for ImgTec PowerDown Controller Watchdog Timer.
Signed-off-by: Naidu Tellapati
Signed-off-by: Jude.Abraham
Reviewed-by: Andrew Bresticker
Reviewed-by: Ezequiel Garcia
---
drivers/watchdog/Kconfig | 11 ++
drivers/watchdog/Makefile |1 +
drivers/watchdog
Add the devicetree binding document for ImgTec PDC Watchdog Timer.
Signed-off-by: Naidu Tellapati
Signed-off-by: Jude Abraham
Reviewed-by: Andrew Bresticker
---
No changes from v5.
---
.../devicetree/bindings/watchdog/imgpdc-wdt.txt| 18 ++
1 files changed, 18 insertions(
This patchset provides support for the PowerDown Controller (PDC) Watchdog Timer
found on Pistachio SOC from Imagination Technologies (ImgTec).
The series is based on 3.18-rc5.
I am re-sending the series with correct Signed-off-by headers.
Changes from v5:
* Removed unused struct pdc_wdt_dev v
Hi Paul,
On Wednesday 26 November 2014 12:34 PM, Paul Walmsley wrote:
> Hi Lokesh
>
> On Tue, 25 Nov 2014, Lokesh Vutla wrote:
>
>> Hi Paul,
>> On Thursday 20 November 2014 10:26 PM, Paul Walmsley wrote:
>>> On Thu, 20 Nov 2014, Lokesh Vutla wrote:
>>>
On Monday 17 November 2014 10:13 AM, L
On Monday 24 November 2014 06:05 PM, Sebastian Andrzej Siewior wrote:
> On 11/24/2014 01:16 PM, Vignesh R wrote:
>
>> I have tried running both IIO and TSC at the same time. But I have never
>> seen WARN_ON() even after running for close to 30 min. Can you send me
>> the exact script, so that it
Few nits..
On 26 November 2014 at 23:20, Eduardo Valentin wrote:
> Signed-off-by: Eduardo Valentin
> ---
The normal practice is to write the non-commitable part here ...
> drivers/thermal/cpu_cooling.c | 5 +
> drivers/thermal/db8500_cpufreq_cooling.c | 5 -
On Thu, Nov 13, 2014 at 12:10:47PM +1100, Benjamin Herrenschmidt wrote:
> So I've been annoyed lately with having a bunch of devices such as i2c
> eeproms (for use by VPDs, server world !) and other bits and pieces that
> I want to be able to identify from userspace, and possibly provide
> addition
On Thursday 27 November 2014 12:13 AM, Kukjin Kim wrote:
On 11/24/14 17:47, Pankaj Dubey wrote:
This patch adds syscon based phandle to i2c device nodes of exynos5250
and exynos5420. These phandles will be used to save restore i2c sysreg
configuration register during s2r from i2c driver.
CC: Ro
On Mon, Nov 17, 2014 at 04:06:08PM +0530, Ankit Jindal wrote:
> Currently, three types of mem regions are supported: UIO_MEM_PHYS,
> UIO_MEM_LOGICAL and UIO_MEM_VIRTUAL. Among these UIO_MEM_PHYS helps
> UIO driver export physcial memory to user space as non-cacheable
> user memory. Typcially memory
Hi,
On Wed, 2014-11-26 at 08:14 -0800, Doug Anderson wrote:
> Yingjoe,
>
> On Wed, Nov 26, 2014 at 6:41 AM, Yingjoe Chen
> wrote:
> > Sorry for the (very) late reply.
> > I just realize today MT8135 need this and the other patch [1] to boot
> > SMP correctly. I've applied both patches and they
>>
>>
> Hi Dave
> Do you mean that I need send you a branch, based on drm-next, merge with
> iommu tree and rockchip drm?
Yes, grab drm-next, git pull the arm/rockchip branch from Joerg's
tree, put rockchip drm
patches on top, send me pull request.
I'll validate it then.
Dave.
--
To unsubscr
On 2014年11月27日 06:53, Dave Airlie wrote:
On 26 November 2014 at 17:34, Joerg Roedel wrote:
On Wed, Nov 26, 2014 at 01:37:51AM +0100, Heiko Stübner wrote:
Joerg, is your arm/rockchip branch [0] considered stable?
[0]
https://git.kernel.org/cgit/linux/kernel/git/joro/iommu.git/log/?h=arm/rockc
(Looping backlight class subsystem maintainers)
Hi Sean,
Please see my comments below. Thanks!
On 11/27/2014 4:11 AM, Sean Paul wrote:
This patch adds a supply regulator to the lp855x platform data to facilitate
powering on/off the 3V rail attached to the controller.
Cc: Stéphane Marchesin
Cc
(Looping backlight class subsystem maintainers)
Hi Sean,
Thanks for checking this. I'd like to describe why the original code is
preferred.
The original code is copying the values of the lp855x platform data from
the DT in advance of allocating lp855x data.
It guarantees returning quickly i
These clocks represent the physical clocks (including phases) and they will
later be used for clock phase tuning.
Suggested-by: Heiko Stuebner
Signed-off-by: Alexandru M Stan
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
include/dt-bindings/clock/rk3288-cru.h | 10 ++
This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).
The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adju
For now all I have is the getter and setter for the phase, nothing that uses it
(that is ready). You can test the getter like this:
localhost ~ # cat /sys/kernel/debug/clk/clk_summary|grep sample -C 1
sclk_sdio1002400 0 0
sdio1_sample
On 11/25/2014 02:07 PM, Mark Brown wrote:
> On Wed, Nov 19, 2014 at 10:52:47AM -0800, Kenneth Westfield wrote:
>
>> +++ b/sound/soc/qcom/Kconfig
>> @@ -0,0 +1,43 @@
...
>> +# Permission to use, copy, modify, and/or distribute this software for any
>> +# purpose with or without fee is hereby grante
On Wed, Nov 26 2014 at 17:53 -0700, Kevin Hilman wrote:
Lina Iyer writes:
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The
On 11/27/2014 06:52 AM, Doug Anderson wrote:
Chris,
On Mon, Nov 24, 2014 at 11:32 PM, Chris Zhong wrote:
vcc_ddr: DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
reg
On 11/26/2014 04:13 PM, Lina Iyer wrote:
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
imple
Lina Iyer writes:
> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrupt at the GIC, wh
On Wed, Nov 26 2014 at 17:13 -0700, Lina Iyer wrote:
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v11:
- Address review comments on spm.c
- Commenting style fixes
- Added Reviewed-by
Ch
On Wed, Nov 26 2014 at 15:42 -0700, Stephen Boyd wrote:
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance
On Wed, Nov 26, 2014 at 10:53:28AM -0700, Jim Davis wrote:
> Building with the attached random configuration file,
>
> drivers/built-in.o: In function `meson_spifc_probe':
> spi-meson-spifc.c:(.text+0x14b4a8): undefined reference to
> `devm_regmap_init_mmio_clk'
> make: *** [vmlinux] Error 1
Hi,
On Wed, Nov 26, 2014 at 1:28 PM, Arnd Bergmann wrote:
>> For the BMIPS case:
>>
>> plat_map_dma_mem* and plat_dma_addr_to_phys are just performing
>> remapping, so dma-ranges would work.
>>
>> plat_unmap_dma_mem is used to perform an extra BMIPS-specific
>> cacheflush operation.
>
> Yes, the cache
On 26 November 2014 at 17:34, Joerg Roedel wrote:
> On Wed, Nov 26, 2014 at 01:37:51AM +0100, Heiko Stübner wrote:
>>
>> Joerg, is your arm/rockchip branch [0] considered stable?
>>
>> [0]
>> https://git.kernel.org/cgit/linux/kernel/git/joro/iommu.git/log/?h=arm/rockchip
>>
>
> Yes, this branch w
Chris,
On Mon, Nov 24, 2014 at 11:32 PM, Chris Zhong wrote:
> vcc_ddr: DCDC_REG3 {
> regulator-always-on;
> regulator-boot-on;
> regulator-name = "vcc_ddr";
> +
On 11/26/2014 02:28 PM, Lina Iyer wrote:
+
+static struct platform_driver qcom_cpuidle_plat_driver = {
+ .probe = qcom_cpuidle_probe,
+ .driver = {
+ .name = "qcom_cpuidle",
+ },
+};
+
+module_platform_driver(qcom_cpuidle_plat_driver);
Said this a few reviews ag
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed-by:
Hi,
On Tue, Nov 25, 2014 at 12:10 AM, Addy Ke wrote:
> This patch add a new quirk to add a s/w timer to notify the driver
> to terminate current transfer and report a data timeout to the core,
> if DTO interrupt does NOT come within the given time.
>
> dw_mmc call mmc_request_done func to finish
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
Reviewed
On 11/26/2014 02:28 PM, Lina Iyer wrote:
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
imple
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 20
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 16 +
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 20 +++
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +
Add ARM common idle states device bindings for cpuidle support for APQ
8074/8974.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++
Add cpuidle driver interface to allow cpus to go into idle states. Use
the cpuidle DT interface, common across ARM architectures, to provide
the idle state information to the cpuidle framework.
Supported modes at this time are Standby and Standalone Power Collapse.
Signed-off-by: Lina Iyer
Acked
Dependent patchsets -
https://lkml.org/lkml/2014/8/4/767
http://www.spinics.net/lists/linux-arm-msm/msg10799.html
http://www.spinics.net/lists/linux-arm-msm/msg10795.html
Changes since v10:
[ https://www.mail-archive.com/devicetree@vger.kernel.org/msg51880.html ]
- Address
Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer
Reviewed-by: Stephen Boyd
---
arch/arm/mach-qcom/Makefile | 1 -
arch/arm/mach-qcom/platsmp.c
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer
---
arch/arm/boot/dts/qcom-msm8974.dtsi | 26
Quad core SoCs like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warm boot addresses for secondary cores.
We do not need to export the warmboot flags. Move them into the
implementation file.
Signed-off-by: Lina Iyer
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
On Wed, Nov 26, 2014 at 09:06:33PM +, Grant Likely wrote:
> On Wed, Nov 26, 2014 at 5:40 PM, Leif Lindholm
> wrote:
> > Update of_find_node_by_path():
> > 1) Ignore any part of the path beyond and including the ':' separator.
> > 2) Set the new provided pointer argument to the beginning of th
Add binding for the Qualcomm Resource Power Manager (RPM) found in 8660,
8960 and 8064 based devices.
Signed-off-by: Bjorn Andersson
---
Removed regulator definition from this patch, as these needs more discussion to
be able to implement SoC assisted power save features of the Qualcomm
platforms
With all the requisite changes in place we can now enable basic
PM support for AM33xx. This patch updates the various OMAP files
to enable suspend-resume on AM33xx.
Because the suspend resume functionality is different on AM33xx
than other OMAP platforms due to the need for M3 firmware and an
IPC
From: Vaibhav Bedia
OMAP timer code registers two timers - one as clocksource
and one as clockevent. Since AM33XX has only one usable timer
in the WKUP domain one of the timers needs suspend-resume
support to restore the configuration to pre-suspend state.
commit adc78e6b9946 ("timekeeping: Add
In preparation for suspend-resume support for AM33XX, add
the assembly file with the code which is copied to internal
memory (OCMC RAM) during bootup and runs from there.
As part of the low power entry (DeepSleep0 mode in AM33XX TRM),
the code running from OCMC RAM does the following
1. Calls rout
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x Technical Reference Manual.
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system reboot and is mapped as
the suspend state in the kernel. In this state, MPU and
PER domains a
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