From: Gyungoh Yoo jack@skyworksinc.com
This patch set includes regulator and backlight driver for SKY81452.
Also it includes documents for device tree and module.
The initial version of sky81452-regulator was applied. Fo this, incremental
patches are included.
v9:
Removed the change to
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Made up the example for backlight DT
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Changed DT for regulator : 'lout' node should be defined under
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Changed DT for regulator : 'lout' node should be defined under 'regulator'
Removed compatible string
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Removed the change to remove MODULE_VERSION()
Changes v8:
Changed the DT parsing of regulator using regulator_node and of_match
Changes v7:
Modified licensing text to GPLv2
Splitted
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added vendor prefix for Skyworks
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Add SKY81452 to the Trivial Devices
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for GPIO
Made up the example for backlight DT
Changes v7:
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for GPIO
Changes v7:
Modified licensing text to GPLv2
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
Acked-by: Lee Jones lee.jo...@linaro.org
---
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Modified licensing text to GPLv2
Changes v6:
Added new line character at the end of line of dev_err()
Hello Kukjin,
On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com wrote:
DP PHY now require pmu-system-controller to handle PMU register
to control PHY's power isolation. Adding the same to dp-phy
node.
Signed-off-by: Vivek Gautam gautam.vi...@samsung.com
Reviewed-by:
Dear Arnd Bergmann,
On Mon, 01 Dec 2014 15:59:14 +0100, Arnd Bergmann wrote:
I still don't see where it does that. All I see for mvebu is
platform_device_register_simple(cpufreq-dt, -1, NULL, 0);
without any platform data. I see this patch
On December 1, 2014 9:11:21 PM CET, a...@natisbad.org wrote:
Uwe Kleine-König u...@kleine-koenig.org writes:
For patch 1: Maybe point out that the issue with the century bit
isn't
that critical, because this bit is not expected to be set before year
2100.
It has:
This was tested by
On Tue, 2014-12-02 at 15:17 +0900, Heesub Shin wrote:
Hello Simons,
On 12/01/2014 09:59 PM, Sjoerd Simons wrote:
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free
On Tuesday, December 02, 2014 5:17 PM, Javier Martinez Canillas wrote:
Hello Kukjin,
On Mon, Nov 24, 2014 at 6:41 AM, Vivek Gautam gautam.vi...@samsung.com
wrote:
DP PHY now require pmu-system-controller to handle PMU register
to control PHY's power isolation. Adding the same to dp-phy
On Tuesday 02 December 2014 14:43:51 Zhou Wang wrote:
how about a patch like this, we read the base from the dts here.
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index e8e98ca..0c40f53 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -107,11 +107,16
Add USB nodes to zc702, zc706 and zed device trees.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
v2:
- remove '@0' from phy node name
- don't add bogus space
---
arch/arm/boot/dts/zynq-7000.dtsi | 20
arch/arm/boot/dts/zynq-zc702.dts | 11 +++
The EBI (External Bus Interface) is used to access external peripherals
(NOR, SRAM, NAND, and other specific devices like ethernet controllers).
Each device is assigned a CS line and an address range and can have its
own configuration (timings, access mode, bus width, ...).
This driver provides a
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds SPI (Serial Peripheral Interface) dt node for Exynos5433 SoC.
SPI transfers serial data by using various peripherals. SPI includes
8-bit/16-bit/32-bit shift registers to transmit and receive data. PDMA is used
for SPI communication.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A6/Bus/Audio clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds the support for Exynos 64bit SoC. The delay_timer is only used
for Exynos 32bit SoC.
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Signed-off-by: Chanwoo Choi
This patch enable Exynos5433 SoC in the arm64 defconfig.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
---
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
Acked-by: Geunsik Lim
This patchset adds new 64-bit Exynos5433 Samsung SoC which contains quad
Cortex-A57 and quad Cortex-A53. It is desigend with the 20nm low power process.
This patchset include some patches such as:
- Support booting of Exynos5433
- Support UART/MCT/GIC/HSI2C/SPI/PDMA/MSHC
- Support the clock
From: Jaehoon Chung jh80.ch...@samsung.com
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim kgene@samsung.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
This patch adds the necessary Kconfig entries to enable
support for the ARMv8 based Exynos5433 SoC.
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Will Deacon will.dea...@arm.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Geunsik Lim geunsik@samsung.com
Acked-by: Inki Dae
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi
This patch adds new s3c24xx_serial_drv_data structure for Exynos5433 SoC
because Exynos5433 has different fifo size from existing Exynos4 SoC.
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Jiri Slaby jsl...@suse.cz
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Chanwoo Choi
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and
This patch adds ths mux/divider/gate clocksof CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Inki Dae inki@samsung.com
This patch adds the mux/divider/gate clock fo CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa
On Monday 01 December 2014 13:51:26 Sören Brinkmann wrote:
Hi Arnd,
On Mon, 2014-12-01 at 10:26PM +0100, Arnd Bergmann wrote:
On Monday 01 December 2014 10:42:32 Soren Brinkmann wrote:
+ usb_phy0: usb-phy@0 {
+ compatible = usb-nop-xceiv;
+
This a series of patches is a DRM Driver for Rockchip Socs, add support
for vop devices. Future patches will add additional encoders/connectors,
such as eDP, HDMI.
The basic crtc for rockchip is a VOP - Video Output Processor.
the vop devices found on Rockchip rk3288 Soc, rk3288 soc have two
On Monday 01 December 2014 17:17:30, Arnd Bergmann wrote:
On Monday 01 December 2014 11:50:06 Boris Brezillon wrote:
I don't have a strong opinion regarding where this driver should
live (I even considered putting it in drivers/bus) :-).
But note that there are other external memory
This patch adds the basic structure of a DRM Driver for Rockchip Socs.
Signed-off-by: Mark Yao mark@rock-chips.com
Signed-off-by: Daniel Kurtz djku...@chromium.org
Acked-by: Daniel Vetter dan...@ffwll.ch
Reviewed-by: Rob Clark robdcl...@gmail.com
---
Changes in v2:
- use the component
This add a display subsystem comprise the all display interface nodes.
Signed-off-by: Mark Yao mark@rock-chips.com
---
Changes in v2:
- add DRM master device node to list all display nodes that comprise
the graphics subsystem.
Changes in v3: None
Changes in v4: None
Changes in v5: None
This adds binding documentation for Rockchip SoC VOP driver.
Signed-off-by: Mark Yao mark@rock-chips.com
---
Changes in v2:
- rename lcdc to vop
- add vop reset
- add iommu node
- add port for display-subsystem
Changes in v3: None
Changes in v4: None
Changes in v5: None
Changes in v6:
On Thu, Oct 02, 2014 at 09:43:32AM -0700, Dylan Reid wrote:
Enables the gpio-base mic detection on the Acer Chromebook 13. This
gpio is set by the jack-detection chip when it notices either of the
TRRS type headsets with a microphone.
Signed-off-by: Dylan Reid dgr...@chromium.org
---
Hi Mark,
Am Dienstag, 2. Dezember 2014, 17:13:20 schrieb Mark Yao:
This a series of patches is a DRM Driver for Rockchip Socs, add support
for vop devices. Future patches will add additional encoders/connectors,
such as eDP, HDMI.
The basic crtc for rockchip is a VOP - Video Output
On Monday 01 December 2014 22:51:07 Hauke Mehrtens wrote:
IRQ support for Broadcom's bus-axi driver bcma was merged into John
Linville's wireless tree and will show up in 3.19. This patch makes use
of this feature in the DTS file for the the BCM5301X SoCs. I left the
PCIe controller out,
Hi Dave
The following changes since commit 656d7077d8ffd1c2492d4a0a354367ab2e545059:
dt-bindings: iommu: Add documentation for rockchip iommu (2014-11-03
17:29:09 +0100)
are available in the git repository at:
https://github.com/markyzq/kernel-drm-rockchip.git drm_iommu_v15
for you to
On 12/02/2014 09:46 AM, Soren Brinkmann wrote:
Add USB nodes to zc702, zc706 and zed device trees.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
---
v2:
- remove '@0' from phy node name
- don't add bogus space
---
arch/arm/boot/dts/zynq-7000.dtsi | 20
On Tuesday 02 December 2014 10:18:45 Alexander Stein wrote:
On Monday 01 December 2014 17:17:30, Arnd Bergmann wrote:
On Monday 01 December 2014 11:50:06 Boris Brezillon wrote:
I don't have a strong opinion regarding where this driver should
live (I even considered putting it in
On Mon, Nov 24, 2014 at 04:17:17PM -0800, Andrew Bresticker wrote:
The Tegra xHCI controller's firmware communicates requests to the host
processor through a mailbox interface. While there is only a single
physical channel, messages sent by the controller can be divided
into two groups: those
On 12/01/2014 07:50 PM, Lina Iyer wrote:
On Thu, Nov 27 2014 at 01:52 -0700, Daniel Lezcano wrote:
On 11/27/2014 06:24 AM, Lina Iyer wrote:
+static bool cpuidle_drv_init;
^
As already said in a previous comment, please find a way to remove that.
I will look into it.
This series implements workarounds for some bugs in Cadence I2C controller.
- The I2C controller when configured in Master Mode generates invalid read
transactions.
When HOLD bit is set and HW timeout occurs, invalid read transactions are
generated on the bus. This will affect repeated start
From: Vishnu Motghare vish...@xilinx.com
Cadence I2C controller has bug wherein it generates invalid read transactions
after time-out in master receiver mode. This driver does not use the HW
timeout and this interrupt is disabled but the feature itself cannot be
disabled. Hence, this patch writes
From: Vishnu Motghare vish...@xilinx.com
This patch defeatures repeated start in the driver if
defeature-repeated-start property is present in the devicetree.
This defeature is proposed due to a few bugs in the controller
- completion indication is not given to the driver at the end of
a
The I2C controller sends a NACK to the slave when transfer size register
reaches zero, irrespective of the hold bit. So, in order to handle transfers
greater than 252 bytes, the transfer size register has to be maintained at a
value = 1. This patch implements the same.
The interrupt status is
From: Vishnu Motghare vish...@xilinx.com
This patch adds defeature-repeated-start property in i2c-cadence.txt.
Signed-off-by: Vishnu Motghare vish...@xilinx.com
Signed-off-by: Harini Katakam hari...@xilinx.com
---
.../devicetree/bindings/i2c/i2c-cadence.txt| 11 +++
1 file
Hi Andy,
Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan:
[...]
+static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ const struct
On Tue, Dec 02, 2014 at 10:51:22AM +0530, punnaiah choudary kalluri wrote:
+/**
+ * synps_edac_get_eccstate - Return the controller ecc enable/disable
status
+ * @base:Pointer to the ddr memory contoller base address
+ *
+ * This routine returns the ECC enable/disable status for
On Mon, Dec 01, 2014 at 02:21:46AM +, Chanwoo Choi wrote:
Dear Mark,
On 11/28/2014 11:00 PM, Mark Rutland wrote:
On Fri, Nov 28, 2014 at 01:18:25PM +, Chanwoo Choi wrote:
Dear Mark,
On 11/27/2014 08:18 PM, Mark Rutland wrote:
On Thu, Nov 27, 2014 at 07:35:13AM +, Chanwoo
On 12/01/2014 04:31 PM, Arnd Bergmann wrote:
On Monday 01 December 2014 14:24:57 Michal Simek wrote:
The driver provide memory allocator which can
be used by others drivers to allocate memory inside OCM.
All locations for 64kB blocks are supported
and driver is trying to allocate the largest
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
PSCI (Power State Coordination Interface) v0.1.
Cc: Kukjin Kim
On Mon, Dec 01, 2014 at 06:57:05PM +, Lina Iyer wrote:
On Thu, Nov 27 2014 at 08:01 -0700, Lorenzo Pieralisi wrote:
On Thu, Nov 27, 2014 at 05:24:07AM +, Lina Iyer wrote:
[...]
+static int spm_set_low_power_mode(enum pm_sleep_mode mode)
+{
+ struct spm_driver_data *drv =
On Mon, Nov 24, 2014 at 01:28:17PM +0100, Tomeu Vizoso wrote:
The ACTMON block can monitor several counters, providing averaging and firing
interrupts based on watermarking configuration. This implementation monitors
the MCALL and MCCPU counters to choose an appropriate frequency for the
On Tue, Dec 2, 2014 at 4:06 PM, Borislav Petkov b...@alien8.de wrote:
On Tue, Dec 02, 2014 at 10:51:22AM +0530, punnaiah choudary kalluri wrote:
+/**
+ * synps_edac_get_eccstate - Return the controller ecc enable/disable
status
+ * @base:Pointer to the ddr memory contoller base
On Tue, Dec 02, 2014 at 10:05:48AM +, Harini Katakam wrote:
From: Vishnu Motghare vish...@xilinx.com
This patch adds defeature-repeated-start property in i2c-cadence.txt.
Signed-off-by: Vishnu Motghare vish...@xilinx.com
Signed-off-by: Harini Katakam hari...@xilinx.com
---
On Tue, Dec 02, 2014 at 10:05:49AM +, Harini Katakam wrote:
From: Vishnu Motghare vish...@xilinx.com
This patch defeatures repeated start in the driver if
defeature-repeated-start property is present in the devicetree.
This defeature is proposed due to a few bugs in the controller
-
Dear Mark,
On 12/02/2014 08:09 PM, Mark Rutland wrote:
Hi,
On Tue, Dec 02, 2014 at 08:49:51AM +, Chanwoo Choi wrote:
This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
Octal core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433
supports
PSCI
On 2 December 2014 at 02:55, NeilBrown ne...@suse.de wrote:
On Fri, 28 Nov 2014 12:56:33 +0100 Ulf Hansson ulf.hans...@linaro.org wrote:
On 8 November 2014 at 01:14, NeilBrown ne...@suse.de wrote:
If the regulator supplying an SDIO device is shared
with another device, the turning the
Hi,
+ psci {
+ compatible = arm,psci;
+ method = smc;
+ cpu_off = 0x8402;
+ cpu_on = 0xC403;
+ };
Given your comments on the latest posting, has CPU_OFF been tested, and
does it work for _all_ CPUs
Hi Mark,
On Tue, Dec 2, 2014 at 4:49 PM, Mark Rutland mark.rutl...@arm.com wrote:
On Tue, Dec 02, 2014 at 10:05:48AM +, Harini Katakam wrote:
From: Vishnu Motghare vish...@xilinx.com
This patch adds defeature-repeated-start property in i2c-cadence.txt.
Signed-off-by: Vishnu Motghare
On Tue, Dec 02, 2014 at 05:05:28PM +0900, gyun...@gmail.com wrote:
From: Gyungoh Yoo jack@skyworksinc.com
Applied, thanks.
signature.asc
Description: Digital signature
On Tue, Dec 02, 2014 at 05:05:29PM +0900, gyun...@gmail.com wrote:
From: Gyungoh Yoo jack@skyworksinc.com
Applied, thanks.
signature.asc
Description: Digital signature
Hi Philipp:
On 2014年12月02日 18:24, Philipp Zabel wrote:
Hi Andy,
Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan:
[...]
+static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
+void *data)
+{
+ struct platform_device *pdev =
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
driver max77686-pmic modalias power
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, December 02, 2014 6:40 AM
On Fri, 2014-11-28 at 12:10 +0200, Madalin Bucur wrote:
Add the device tree binding document for the DPAA corenet node
and DPAA Ethernet nodes.
Signed-off-by: Madalin Bucur
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this patch :
# ls /sys/class/i2c-adapter/i2c-0/0-0009/
driver
+ - defeature-repeated-start: Include this property to defeature repeated
start
+ This defeature is due to a few bugs in the
+ I2C controller.
+ Completion interrupt after a read/receive
+
From: Markus Elfring elfr...@users.sourceforge.net
Date: Tue, 2 Dec 2014 13:54:00 +0100
The of_node_put() function tests whether its argument is NULL and then
returns immediately. Thus the test around the call is not needed.
This issue was detected by using the Coccinelle software.
Hi Andy,
thank you for joining the discussion.
On 02.12.2014 08:36, Andy Yan wrote:
Hi Vladimir:
I am working on convert imx-hdmi to dw_hdmi now:
https://lkml.org/lkml/2014/12/1/190
I also have a plan to use the internal HDMI I2C master under the I2c
framework,
and I also have a
But given the bugs, it will be useful to just disable it if the system doesn't
require repeated start.
What do you do when disable repeated start? Sending STOP and START? If
so, this is really something different than repeated start. By using
I2C_FUNC_I2C a user expects repeated start, so if
Thank you for references.
Yes, thank you all. Really great to see this consolidation effort going
on!
I'll try to review all out of i2c/busses/* registered i2c adapters, may
be there is something in common between all of them.
Yay, cool! Thanks!
I'll prepare the change of the HDMI DDC
On Tue, Nov 25, 2014 at 9:04 AM, Yingjoe Chen yingjoe.c...@mediatek.com wrote:
Add support to use gic as a parent for stacked irq domain.
Signed-off-by: Yingjoe Chen yingjoe.c...@mediatek.com
This change (which is now in -next as commit 9a1091ef0017c40a) breaks
booting on
Hi,
On Tue, Dec 2, 2014 at 6:46 PM, Wolfram Sang w...@the-dreams.de wrote:
But given the bugs, it will be useful to just disable it if the system
doesn't
require repeated start.
What do you do when disable repeated start? Sending STOP and START? If
so, this is really something different
On 02.12.2014 13:45, Yadwinder Singh Brar wrote:
rtc have different i2c client than power(pmic) block. So rtc device should
sit under its own i2c client in device hierarchy, which reflects in sysfs
also.
This patch modifies code to register rtc cell with rtc-dev as parent.
Without this
On 02/12/14 13:27, Geert Uytterhoeven wrote:
On Tue, Nov 25, 2014 at 9:04 AM, Yingjoe Chen yingjoe.c...@mediatek.com
wrote:
Add support to use gic as a parent for stacked irq domain.
Signed-off-by: Yingjoe Chen yingjoe.c...@mediatek.com
This change (which is now in -next as commit
This patchset adds driver for Richtek rt5033 chip The chip contains
switching charge mode Li-Ion/Li-Polymer battery charger, fuelgauge, regulators.
This patchset provides common support for accessing the device.
This patchset have been tested base on exynos board.
Changes in v7
- Use small
This patch device tree binding documentation for rt5033 multifunction device.
Cc: Rob Herring robh...@kernel.org
Cc: Pawel Moll pawel.m...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Ian campbell ijc+devicet...@hellion.org.uk
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Beomho Seo
This patch add device driver of Richtek RT5033 PMIC. The driver support
switching charger. rt5033 charger provide three charging mode.
Three charging mode are pre charge mode, fast cahrge mode and constant voltage
mode. They are have vary charge rate, charge parameters. The charge parameters
can
This patch adds a new driver for Richtek RT5033 driver.
RT5033 is a Multifunction device which includes battery charger, fuel gauge,
flash LED current source, LDO and synchronous Buck converter. It is interfaced
to host controller using I2C interface.
Cc: Samuel Ortiz sa...@linux.intel.com
Cc:
Hi Marc,
On Tue, Dec 2, 2014 at 2:37 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 02/12/14 13:27, Geert Uytterhoeven wrote:
On Tue, Nov 25, 2014 at 9:04 AM, Yingjoe Chen yingjoe.c...@mediatek.com
wrote:
Add support to use gic as a parent for stacked irq domain.
Signed-off-by: Yingjoe
Hi Linus,
On Fri, Nov 28, 2014 at 05:12:44PM +0100, Linus Walleij wrote:
On Thu, Nov 27, 2014 at 11:18 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Nov 27, 2014 at 09:44:42AM +0100, Linus Walleij wrote:
On Tue, Nov 11, 2014 at 1:38 PM, Hongzhou Yang
hongzhou.y...@mediatek.com
On Thu, Nov 27, 2014 at 09:33:59PM +0100, Philippe Reynes wrote:
Signed-off-by: Philippe Reynes trem...@gmail.com
Applied, thanks.
---
arch/arm/boot/dts/imx27-apf27dev.dts | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git
On Tue, Dec 2, 2014 at 7:57 AM, Benoit Parrot bpar...@ti.com wrote:
Alexandre Courbot gnu...@gmail.com wrote on Fri [2014-Nov-28 16:31:19
+0900]:
On Fri, Nov 21, 2014 at 8:54 AM, Benoit Parrot bpar...@ti.com wrote:
Add GPIO hogging documentation to gpio.txt
Signed-off-by: Benoit Parrot
This requires a DT Ack.
From: Gyungoh Yoo jack@skyworksinc.com
Signed-off-by: Gyungoh Yoo jack@skyworksinc.com
---
Changes v9:
Nothing
Changes v8:
Made up the example for backlight DT
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Changed DT for regulator :
On Tue, Dec 2, 2014 at 9:22 AM, Benoit Parrot bpar...@ti.com wrote:
+ }
+
+ if (tmp MAX_PHANDLE_ARGS) {
+ desc = ERR_PTR(-EINVAL);
+ goto out;
+ }
+
+ gg_data.gpiospec.args_count = tmp;
+ gg_data.gpiospec.np = chip_np;
On Fri, Nov 28, 2014 at 12:27:05AM +0100, Stefan Agner wrote:
The Vybrid SoC family (in the kernel known as vf610) is a familiy
of multiple similar SoC's. The VF5xx series comes without secondary
Cortex-M4 core, while the second number VFx1x indicates the presence
of a L2 cache controller.
On 02/12/14 13:55, Geert Uytterhoeven wrote:
Hi Marc,
On Tue, Dec 2, 2014 at 2:37 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 02/12/14 13:27, Geert Uytterhoeven wrote:
On Tue, Nov 25, 2014 at 9:04 AM, Yingjoe Chen yingjoe.c...@mediatek.com
wrote:
Add support to use gic as a parent for
On Tue, Dec 2, 2014 at 1:36 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Fri, Nov 28, 2014 at 04:30:01PM +0900, Alexandre Courbot wrote:
+/**
+ * do_gpio_hog - Given node is a GPIO hog configuration, handle it
+ * @np:device node to get GPIO from
+ *
On Fri, Nov 28, 2014 at 12:35:36AM +0100, Stefan Agner wrote:
During restructuring of the device tree files the watchdog was
changed to be disabled by default. However, since the watchdog
instance is dedicated to the Cortex-A5, enable the peripheral
by default in the base device tree
On Fri, Nov 28, 2014 at 12:40:06AM +0100, Stefan Agner wrote:
On the Colibri module, the RMII clock for the Ethernet PHY is
generated by the SoC. This patch adds that missing pin to the
pinctrl of FEC1. Because the boot loader initializes this pin,
ethernet worked even without this pin so far.
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