Hi,
This series addresses comments from Andrzej Hajda on v4.
Most comments are about the Himax HX8369A DRM panel driver.
And, a single comment is about the Synopsys DesignWare MIPI DSI host
controller DRM bridge driver.
The i.MX MIPI DSI is a Synopsys DesignWare MIPI DSI host controller IP.
This
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* Fix an ordering issue to address Stefan Wahren's comment.
v2-v3:
* None.
v1-v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
If no best divider is normally found, we will try to use the maximum divider.
We should not set the parent clock rate to be 1Hz by force for being rounded.
Instead, we should take the maximum divider as a base and calculate a correct
parent clock rate for being rounded.
Signed-off-by: Liu Ying
This patch adds Synopsys DesignWare MIPI DSI host controller driver support.
Currently, the driver supports the burst with sync pulses mode only.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* Remove 'dsi-panel = NULL;' in dw_mipi_dsi_host_detach() to address
Andrzej Hajda's
This patch adds device tree bindings for Himax HX8369A DRM panel driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* Merge the bs[3:0]-gpios properties into one property - bs-gpios.
This addresses Andrzej Hajda's comment.
v3-v4:
* Newly introduced in v4. This is separated
This patch adds support for Himax HX8369A panel.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the Himax HX8369A panel driver
* make ARCH=arm savedefconfig
* cp defconfig
This patch adds support for MIPI DSI host controller.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* As suggested by Phillip Zabel, change the clocks and the clock-names
properties to use the pllref and core_cfg clocks only.
v1-v2:
* None.
From: Tien Hock Loh th...@altera.com
Adds a new device tree binding and driver for Altera soft GPIO IP.
The driver is able to do read/write and allows GPIO to be a interrupt
controller.
Tested on Altera GHRD on interrupt handling and IO.
v8:
Using for_each_set_bit
added const for struct
The TRULY TFT480800-16-E panel is driven by the Himax HX8369A driver IC.
The driver IC supports several display/control interface modes, including
the MIPI DSI video mode and command mode.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* Replace the bs[3:0]-gpios properties with the
This patch adds support for MIPI DSI host controller.
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm menuconfig and manually choose to build in
the MIPI DSI host controller driver
* make ARCH=arm savedefconfig
* cp defconfig
The new imx_v6_v7_defconfig is generated in this way:
* make ARCH=arm imx_v6_v7_defconfig
* make ARCH=arm savedefconfig
* cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
From: Tien Hock Loh th...@altera.com
Adds a new driver for Altera soft GPIO IP. The driver is able to
do read/write and allows GPIO to be a interrupt controller.
Tested on Altera GHRD on interrupt handling and IO.
Signed-off-by: Tien Hock Loh th...@altera.com
---
MAINTAINERS|
This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's
This patch adds support for Synopsys DesignWare MIPI DSI host controller
which is embedded in the i.MX6q/sdl SoCs.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* Move the relevant dt-bindings to a separate patch to address Stefan
Wahren's comment.
v2-v3:
* To
This patch adds support for Himax HX8369A MIPI DSI panel.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* Address Andrzej Hajda's comments.
* Get the bs-gpios property instead of the bs[3:0]-gpios properties.
* Implement error propagation for panel register configurations.
* Other
This patch adds device tree bindings for i.MX specific Synopsys DW MIPI DSI
driver.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* Newly introduced in v4. This is separated from the relevant driver patch
in v3 to address Stefan Wahren's comment.
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals. This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output. The MIPI DSI host controller embedded in the
The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
clock, according to the i.MX6q/sdl reference manuals. This clock is
actually the gate for several clocks, including the hsi_tx_sel clock's
output and the video_27m clock's output. So, this patch changes the
hsi_tx clock to be a
According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
clock's parent should be the video_27m clock. The i.MX6DL reference manual
has the same statement. This patch changes the hdmi_isfr clock's parent
from the pll3_pfd1_540m clock to the video_27m clock.
Suggested-by:
The MIPI DSI node contains some ports which represent possible DRM CRTCs
it can connect with. Each port has a 'reg' property embedded. This
property will be wrongly interpretted by the MIPI DSI bus driver, because
the driver will take each subnode which contains a 'reg' property as a
DSI
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* Thierry Reding suggested that the mipi_dsi_pixel_format_to_bpp() function
could be placed at the common DRM MIPI DSI driver.
This patch is newly added.
include/drm/drm_mipi_dsi.h
This patch adds a macro to define the GPR3 MIPI muxing control register field
shift bits.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 1 +
1 file changed, 1 insertion(+)
diff
This patch supports the video_27m clock which is a fixed factor
clock of the pll3_pfd1_540m clock.
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
arch/arm/mach-imx/clk-imx6q.c | 1 +
Signed-off-by: Liu Ying ying@freescale.com
---
v4-v5:
* None.
v3-v4:
* None.
v2-v3:
* None.
v1-v2:
* None.
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
On 2014-12-23 21:07, Arnd Bergmann wrote:
On Tuesday 23 December 2014 08:43:55 Marc Zyngier wrote:
Neverthless, MT8173 SoC already use 0x10224000 and 0x10225000 as
VGIC
base address.
Then its fate is sealed virtualization wise.
It should still work with 4kb pages on the host, right?
From: Tien Hock Loh th...@altera.com
Adds a new driver device tree binding for Altera soft GPIO IP
Signed-off-by: Tien Hock Loh th...@altera.com
---
.../devicetree/bindings/gpio/gpio-altera.txt | 43
1 files changed, 43 insertions(+), 0 deletions(-)
create mode
This patch add dts support for NAND flash controller of Hisilicon Soc Hip04
Changes in v2:
- Base on v3.19-rc1
- Use nand-ecc-strength, nand-ecc-step-size to replace hisi,nand-ecc-bits
Changes in v1:
- Move partition and other board related information into board dts file:
hip04-d01.dts
Since RK3288 DMAC's burst length only support max to 4, here
set maxburst of playback and capture dma data to 4.
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
changes since v1:
- new patch since v1
sound/soc/rockchip/rockchip_i2s.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
To make Bus DMA works more efficiency, DMA may work in burst mode,
we set the watermark of transmit and receive reach to 16 bits.
Jianqun Xu (3):
ASoC: rockchip: i2s: fix error defination of transmit data level
ASoC: rockchip: i2s: set TDL and RDL to 16 samples
ASoC: rockchip: i2s: fix
Set Transmit Data Level(TDL) and Receive Data Level(RDL) to 16 samples.
Without this setting, the TDL is default to be 0x00 (means 0 sample),
and the RDL is default to be 0x1f (means 32 samples).
Signed-off-by: Jianqun Xu jay...@rock-chips.com
---
changes since v1:
- modify commit message bit to
According to description about Transmit Data Level,
This bit field controls the level at which a DMA request
is made by the transmit logic.
It is equal to the watermark level.
That is, the dma_tx_req signal is generated when the number
of valid data entries in the TXFIFO
(TXFIFO0 if CSR=00
Hi!
On Tue, Dec 23, 2014 at 10:04:22AM -0300, Walter Lozano wrote:
This patch adds the DTS bindings for the adxl34x digital
accelerometer.
Thanks for doing this. Does the ADXL34 work now? Last time I
tried it, I didn't get any interrupts, but as I didn't really
care for the accelerometer I
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
drivers/mtd/nand/Kconfig|5 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/hisi504_nand.c | 907 +++
3 files changed, 913 insertions(+)
create mode 100644
Signed-off-by: Zhou Wang wangzhou@gmail.com
---
.../devicetree/bindings/mtd/hisi504-nand.txt | 48
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/hisi504-nand.txt
diff --git
This patchset adds the support for NAND controller of hisilicon hip04 Soc.
The NAND controller IP was developed by hisilicon and needs a new driver to
support it. This patchset is based on l2-mtd/master.
I have tested this NAND flash controller driver in Hip04 D01 board using MTD
test modules.
On Wed, 2014-12-24 at 00:22 -0800, th...@altera.com wrote:
Adds a new driver for Altera soft GPIO IP. The driver is able to
do read/write and allows GPIO to be a interrupt controller.
Some trivial comments, some not quite so trivial.
diff --git a/drivers/gpio/gpio-altera.c
On Fri, Dec 19, 2014 at 05:15:53PM +0900, Yoshihiro Shimoda wrote:
The MSIOF controller has DTDL and SYNCDL in SITMDR1 register. So,
this patch adds new properties like the following commit:
d0fb47a5237d8b9576113568bacfd27892308b62
(spi: fsl-espi: Configure FSL eSPI CSBEF and CSAFT)
On Tue, Dec 9, 2014 at 1:57 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 08 December 2014 17:57:03 Zi Shen Lim wrote:
Hi Arnd,
On Mon, Nov 24, 2014 at 3:53 AM, Arnd Bergmann a...@arndb.de wrote:
On Saturday 22 November 2014 02:53:27 Ganapatrao Kulkarni wrote:
Raising the maximum
On Fri, Dec 05, 2014 at 12:07:54PM +0800, Flora Fu wrote:
Add MT6397 regulator driver.
Applied, thanks.
signature.asc
Description: Digital signature
On Fri, Dec 05, 2014 at 12:07:57PM +0800, Flora Fu wrote:
Signed-off-by: Flora Fu flora...@mediatek.com
Applied, thanks.
signature.asc
Description: Digital signature
On Wed, Dec 24, 2014 at 05:36:59PM +0800, Jianqun Xu wrote:
To make Bus DMA works more efficiency, DMA may work in burst mode,
we set the watermark of transmit and receive reach to 16 bits.
Applied all, thanks.
signature.asc
Description: Digital signature
On 12/21/2014 11:43 AM, Rickard Strandqvist wrote:
Remove the function ti_bandgap_write_thot() that is not used anywhere.
This was partially found by using a static code analysis program called
cppcheck.
Signed-off-by: Rickard Strandqvist rickard_strandqv...@spectrumdigital.se
---
On 12/23/2014 05:42 PM, Arnd Bergmann wrote:
On Tuesday 23 December 2014 12:42:05 Murali Karicheri wrote:
here.
Arnd,
I guess so. Besides we need to keep the default coherent dma mask to
32bit 0xull as well to work on Keystone and also in sync with
current defaults used in
From: Kenneth Westfield kwest...@codeaurora.org
Add documentation to the sound directory of the
device-tree bindings for the IPQ806x LPASS CPU DAI
driver.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
From: Kenneth Westfield kwest...@codeaurora.org
Add documentation to the sound directory of the
device-tree bindings for the Maxim MAX98357A audio
codec driver.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
From: Kenneth Westfield kwest...@codeaurora.org
This set of patches adds support for audio on the Qualcomm Technologies
ipq806x SOC.
The ipq806x SOC has audio-related hardware blocks in its low-power audio
subsystem (or LPASS). One of the relevant blocks in the LPASS is its low-power
audio
From: Kenneth Westfield kwest...@codeaurora.org
Add the CPU DAI driver for the QCOM LPASS SOC.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
sound/soc/qcom/lpass-cpu-mi2s.c | 378
1 file
From: Kenneth Westfield kwest...@codeaurora.org
Add PCM platform driver for the LPASS I2S port.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
sound/soc/qcom/lpass-pcm-mi2s.c | 486
1 file
From: Kenneth Westfield kwest...@codeaurora.org
Model the LPASS audio hardware for the IPQ806X.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 23 +++
1 file changed, 23
From: Kenneth Westfield kwest...@codeaurora.org
Now all drivers are in place, allow them to build.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
sound/soc/qcom/Kconfig | 27 +++
sound/soc/qcom/Makefile |
From: Kenneth Westfield kwest...@codeaurora.org
Add the LPASS header files for ipq806x SOCs. This
includes the register definitions for the LPAIF,
and the structure definition for the CPU DAI.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami
From: Kenneth Westfield kwest...@codeaurora.org
Allow for the QCOM LPASS drivers to build.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
2 files changed, 2 insertions(+)
diff
From: Kenneth Westfield kwest...@codeaurora.org
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Kenneth Westfield kwest...@codeaurora.org
Add codec driver for the Maxim MAX98357A DAC.
Signed-off-by: Kenneth Westfield kwest...@codeaurora.org
Acked-by: Banajit Goswami bgosw...@codeaurora.org
---
sound/soc/codecs/Kconfig | 4 ++
sound/soc/codecs/Makefile| 2 +
On Tue, Dec 23, 2014 at 9:22 PM, Vinod Koul vinod.k...@intel.com wrote:
On Thu, Dec 11, 2014 at 02:59:17PM -0800, Andrew Bresticker wrote:
Add support for the IMG Multi-threaded DMA Controller (MDC) found on
certain IMG SoCs. Currently this driver supports the variant present
on the
Hi Maxime,
The recent sun4i-usb-phy changes to add (preliminary) support for the oth phy,
cause the ehci/ohci controllers to no longer work on sun4i / sun5i, because
the phy driver refuses to load due to a missing usb0_reset reset controller
in the dts files for sun4i / sun5i:
[0.094293]
The recent sun4i-usb-phy changes to add (preliminary) support for the oth phy,
cause the ehci/ohci controllers to no longer work on sun4i / sun5i, because
the phy driver refuses to load due to a missing usb0_reset reset controller
in the dts files for sun4i / sun5i:
[0.094293] sun4i-usb-phy
On 24 Dec 2014, at 17:21, Andrew Bresticker abres...@chromium.org wrote:
On Tue, Dec 23, 2014 at 9:22 PM, Vinod Koul vinod.k...@intel.com wrote:
On Thu, Dec 11, 2014 at 02:59:17PM -0800, Andrew Bresticker wrote:
Add support for the IMG Multi-threaded DMA Controller (MDC) found on
certain
dma_mask should be limited to minimum of the default dma mask
and dma-range size configured in DT for proper operation.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
Reviewed-by: Arnd Bergmann a...@arndb.de
---
arch/arm/mm/dma-mapping.c |1 +
1 file changed, 1 insertion(+)
diff --git
When call to of_dma_get_range() fails, the code currently set size
to dev-coherent_dma_mask instead of dev-coherent_dma_mask + 1. Fix this
to make the code consistent with the case when size is obtained from
dma-range property.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
Reviewed-by: Arnd
If there is a DT node available for the root bridge's parent device,
use the dma configuration from that device node. For example, keystone
PCI devices would require dma_pfn_offset to be set correctly in the
device structure of the pci device in order to have the correct dma mask.
The DT node will
Add of_pci_dma_configure() to allow updating the dma configuration
of the pci device using the configuration from DT of the parent of
the root bridge device.
Signed-off-by: Murali Karicheri m-kariche...@ti.com
---
drivers/of/of_pci.c| 73
PCI devices on Keystone doesn't have correct dma_pfn_offset set. This patch
add capability to set the dma configuration such as dma-mask, dma_pfn_offset,
and dma ops etc using the information from DT. The prior RFCs and discussions
are available at [1] and [2] below.
[2] :
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by
We are moving to device tree support on OMAP3, but that currently
breaks ADP1653 driver. This adds device tree support, plus required
documentation.
Signed-off-by: Pavel Machek pa...@ucw.cz
---
Changed -microsec to -us, as requested by devicetree people.
Fixed checkpatch issues.
diff --git
On Tue 2014-12-23 21:49:04, Pavel Machek wrote:
On Tue 2014-12-23 15:23:25, Mauro Carvalho Chehab wrote:
Em Wed, 3 Dec 2014 22:46:41 +0100
Pavel Machek pa...@ucw.cz escreveu:
We are moving to device tree support on OMAP3, but that currently
breaks ADP1653 driver. This adds device
On Wed, Dec 24, 2014 at 6:45 AM, Steffen Trumtrar
s.trumt...@pengutronix.de wrote:
Hi!
On Tue, Dec 23, 2014 at 10:04:22AM -0300, Walter Lozano wrote:
This patch adds the DTS bindings for the adxl34x digital
accelerometer.
Thanks for doing this. Does the ADXL34 work now? Last time I
tried
This patch adds the DTS bindings for the adxl34x digital
accelerometer.
Signed-off-by: Walter Lozano wal...@vanguardiasur.com.ar
---
arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
Hi Matthias,
On Tue, 2014-11-25 at 16:04 +0800, Yingjoe Chen wrote:
Add sysirq settings for mt6589/mt8135/mt8127
This also correct timer interrupt flag. The old setting works
because boot loader already set polarity for timer interrupt.
Without intpol support, the setting was not changed so
One of the patch enables PMU support to BG2Q and BG2CD SoCs. Another patch
adds the missing PPI cpu mask to twd timer interrupts.
Jisheng Zhang (2):
ARM: dts: berlin: add pmu node for BG2Q and BG2CD
ARM: dts: berlin: add PPI cpu mask to twd timer interrupts
arch/arm/boot/dts/berlin2.dtsi
This patch adds the pmu node, enabling the PMU unit on Marvell BG2Q and
BG2CD SoCs.
Signed-off-by: Jisheng Zhang jszh...@marvell.com
---
arch/arm/boot/dts/berlin2cd.dtsi | 5 +
arch/arm/boot/dts/berlin2q.dtsi | 8
2 files changed, 13 insertions(+)
diff --git
Signed-off-by: Jisheng Zhang jszh...@marvell.com
---
arch/arm/boot/dts/berlin2.dtsi | 3 ++-
arch/arm/boot/dts/berlin2cd.dtsi | 3 ++-
arch/arm/boot/dts/berlin2q.dtsi | 3 ++-
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/berlin2.dtsi
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