On 2014/12/31 15:36, Ganapatrao Kulkarni wrote:
> Adding numa support for arm64 based platforms.
> Adding dt node pasring for numa topology using property arm,associativity.
>
Hi,
I applied this patch but started a guest with a dtb which doesn't include NUMA
topology info.
That is I don't add p
This patch device tree binding documentation for rt5033 multifunction device.
Cc: Sebastian Reichel
Cc: Lee Jones
Cc: Mark Brown
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian campbell
Cc: Kumar Gala
Signed-off-by: Beomho Seo
Acked-by: Chanwoo Choi
---
Documentation/devicetree/
This patch add device driver of Richtek RT5033 PMIC. The driver support
switching charger. rt5033 charger provide three charging mode.
Three charging mode are pre charge mode, fast cahrge mode and constant voltage
mode. They are have vary charge rate, charge parameters. The charge parameters
can be
This patchset adds driver for Richtek rt5033 chip The chip contains
switching charge mode Li-Ion/Li-Polymer battery charger, fuelgauge.
Additionally, This includes document for device tree of RT5033 device.
RT5033 core driver is applied by Lee Jones.
RT5033 regulator driver have been merged by Mar
This patch adds device driver of Richtek PMIC.
The driver support battery fuel gange. Fuel gauge calculates and determines the
battery state of charge(SOC) according to battery open circuit voltage(OCV).
Also, this driver provides battery average voltage, voltage and bettery present
property.
Cc:
Hi Arnd,
On Sat, Jan 3, 2015 at 2:47 AM, Arnd Bergmann wrote:
> On Wednesday 31 December 2014 13:03:26 Ganapatrao Kulkarni wrote:
>> DT bindings for numa map for memory, cores and IOs using arm,associativity
>> device node property.
>>
>> Signed-off-by: Ganapatrao Kulkarni
>> ---
>> Documentat
This patch remove unecessary property of gpio-keys node.
gpio-keys driver do not uses interrupts and interrupt-parent.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |2 --
arch/arm/boot/dts
This patch replace number by macro in gpio keys for exynos 3250 boards.
Cc: Kukjin Kim
Cc: Youngjun Cho
Cc: Chanwoo Choi
Reviewed-by: Chanwoo Choi
Signed-off-by: Beomho Seo
---
arch/arm/boot/dts/exynos3250-monk.dts |3 ++-
arch/arm/boot/dts/exynos3250-rinato.dts |3 ++-
2 files cha
This patch revises property of gpio-keys node.
The first patch remove unecessary property.
And then, replace by macro in gpio keys.
Beomho Seo (2):
ARM: dts: exynos3250: remove unecessary property of gpio-keys node
ARM: dts: exynos3250: replace number by macro in gpio keys
arch/arm/boot/dts/
From: Tien Hock Loh
Adds a new device tree binding and driver for Altera soft GPIO IP.
The driver is able to do read/write and allows GPIO to be a interrupt
controller.
Tested on Altera GHRD on interrupt handling and IO.
v9:
Removed duplicated initialization on set_type
using temporals to impro
From: Tien Hock Loh
Adds a new driver for Altera soft GPIO IP. The driver is able to
do read/write and allows GPIO to be a interrupt controller.
Tested on Altera GHRD on interrupt handling and IO.
Signed-off-by: Tien Hock Loh
---
MAINTAINERS| 6 +
drivers/gpio/Kconfig
From: Tien Hock Loh
Adds a new driver device tree binding for Altera soft GPIO IP
Signed-off-by: Tien Hock Loh
---
.../devicetree/bindings/gpio/gpio-altera.txt | 43 ++
1 file changed, 43 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-al
Hi,
On Mon, Jan 05, 2015 at 04:49:08PM -0600, Dave Gerlach wrote:
> >> + /*
> >> + * Write a dummy message to the mailbox in order to trigger the RX
> >> + * interrupt to alert the M3 that data is available in the IPC
> >> + * registers. We must enable the IRQ here and disable it after in
>
Genlty Ping.
Best Regards,
Chanwoo Choi
On 12/29/2014 09:04 AM, Chanwoo Choi wrote:
> This patchset add new devfreq_event class to provide raw data to determine
> current utilization of device which is used for devfreq governor.
>
> [Description of devfreq-event class]
> This patchset add new d
Alim,
On Sun, Jan 4, 2015 at 2:43 PM, Alim Akhtar wrote:
>> You are breaking backward compatibility here. If your change is
>> merged then all old boards will instantly break. Since the "dts" and
>> code changes will likely be merged through different trees you'll end
>> up with a bunch of brok
Dear all,
On Tue, 06 Jan 2015 00:21:22 +0900
Inki Dae wrote:
> On 2015년 01월 05일 23:19, Thierry Reding wrote:
> > On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
> >> Hi Thierry,
> >>
> >> Ping~.
> >>
> >> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
> >> doesn't se
Hi Lucas,
Thanks for picking that up!
I did some short benchmarks on Colibri T20 V1.2, L4T. Write/read speeds
I measured on the YAFFS2 based file system:
# dd if=/dev/zero of=test bs=50M count=1 conv=fdatasync
1+0 records in
1+0 records out
52428800 bytes (52 MB) copied, 9.88293 s, 5.3 MB/s
ech
On 01/05/2015 05:26 PM, Arnd Bergmann wrote:
On Monday 05 January 2015 15:06:57 Murali Karicheri wrote:
On 01/03/2015 04:37 PM, Arnd Bergmann wrote:
Yes, but we also need to pass a PCI device specific identifier along
with the root bus node, because some iommu drivers take the PCI
bus/device/fu
The clock code under drivers/clk/bcm now contains code for both the
Broadcom mobile SoCs and the iProc SoCs. Change the the makefile
dependency to be under config flag CONFIG_ARCH_BCM that's enabled for
both families of SoCs
Signed-off-by: Ray Jui
---
drivers/clk/Makefile |2 +-
1 file chang
Replace current device tree dummy clocks with real clock support for
Broadcom Cygnus SoC
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
arch/arm/boot/dts/bcm-cygnus-clock.dtsi | 110 ---
arch/arm/boot/dts/bcm-cygnus.dtsi |2 +-
2 files changed, 86 i
This adds basic and generic support for various iProc PLLs and clocks
including the ARMPLL, GENPLL, LCPLL, MIPIPLL, and ASIU clocks.
SoCs under the iProc architecture can define their specific register
offsets and clock parameters for their PLL and clock controllers. These
parameters can be passed
Document the device tree binding for Broadcom iProc architecture based
clock controller
Signed-off-by: Ray Jui
Reviewed-by: Scott Branden
---
brcm,iproc-clocks.txt | 178 +
1 file changed, 178 insertions(+)
create mode 100644 brcm,iproc-clocks.t
The Broadcom Cygnus SoC is architected under the iProc architecture. It
has the following PLLs: ARMPLL, GENPLL, LCPLL0, MIPIPLL, all dervied
from an onboard crystal. Cygnus also has various ASIU clocks that are
derived directly from the onboard crystal.
Signed-off-by: Ray Jui
Reviewed-by: Scott B
This patchset contains the initial common clock support for Broadcom's iProc
family of SoCs. The iProc clock architecture comprises of various PLLs, e.g.,
ARMPLL, GENPLL, LCPLL0, MIPIPLL, and etc. An onboard crystal serves as the
basic reference clock for these PLLs. Each PLL may have several leaf
* Dave Gerlach [150105 14:51]:
> Felipe,
> On 01/02/2015 02:16 PM, Felipe Balbi wrote:
> > On Fri, Jan 02, 2015 at 02:00:16PM -0600, Dave Gerlach wrote:
> >> Introduce a wkup_m3_ipc driver to handle communication between the MPU
> >> and Cortex M3 wkup_m3 present on am335x.
> >>
> >> This driver i
* Felipe Balbi [150105 12:23]:
> On Mon, Jan 05, 2015 at 02:10:14PM -0600, Dave Gerlach wrote:
> > >> +static int wkup_m3_rpm_suspend(struct device *dev)
> > >> +{
> > >> +return -EBUSY;
> > >> +}
> > >
> > > looks like this is just coping with omap_device bogosity, no ?
> > >
> >
> > Ye
Felipe,
On 01/02/2015 02:16 PM, Felipe Balbi wrote:
> On Fri, Jan 02, 2015 at 02:00:16PM -0600, Dave Gerlach wrote:
>> Introduce a wkup_m3_ipc driver to handle communication between the MPU
>> and Cortex M3 wkup_m3 present on am335x.
>>
>> This driver is responsible for actually booting the wkup_m3
* Mugunthan V N [141219 00:25]:
> 64KiB is allocated for qspi dtb partition which is not
> sufficient, so updating the partition table size to 512KiB
> for device tree partition.
>
> This also aligns the QSPI partition definitions between
> kernel and U-Boot.
>
> Fixes: dc2dd5b8 ("ARM: dts: dra7
On Monday 05 January 2015 15:06:57 Murali Karicheri wrote:
> On 01/03/2015 04:37 PM, Arnd Bergmann wrote:
> > Yes, but we also need to pass a PCI device specific identifier along
> > with the root bus node, because some iommu drivers take the PCI
> > bus/device/function number into account for crea
Define the Henninger board dependent part of the CAN0 device node.
Signed-off-by: Sergei Shtylyov
---
Changes in version 4:
- refreshed the patch.
Changes in version 3:
- changed "can0_data_a" to "can0_data", removed "can_clk_d" in the
"renesas,groups" property;
- moved CAN0 node to go after
Define the generic R8A7791 parts of the CAN0/1 device nodes.
Signed-off-by: Sergei Shtylyov
Acked-by: Geert Uytterhoeven
---
Changes in version 5:
- fixed whitespace errors/warnings given by checkpatch.pl;
- added Geert's ACK.
Changes in version 4:
- refreshed the patch.
Changes in version 3:
The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock (clkp2)
and external clock fed on CAN_CLK pin. Describe those clocks in the device
tree, along with the USB_EXTAL clock from which clkp2 is derived.
Hello.
Here's the set of 3 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20141231-v3.19-rc2' tag. Here we add the CAN device tree support
for the R8A7791-based Henninger board. It depends on the clk driver RCAN clock
patch reposted today in order to work.
[1/3] ARM: shmobil
From: Schuyler Patton
Added pin mux definitions for collision and carrier sense errors coming
from the ethernet phy. Without these two signals the MAC ends up ignoring
the errors detected by the PHY which end up causing a lower throughput
problem when the phy is in half duplex mode such as connec
Define the generic R8A7790 parts of the CAN0/1 device nodes.
Signed-off-by: Sergei Shtylyov
Acked-by: Geert Uytterhoeven
---
Changes in version 2:
- fixed whitespace errors/warnings given by checkpatch.pl;
- added Geert's ACK.
arch/arm/boot/dts/r8a7790.dtsi | 20
1 file
The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock (clkp2)
and external clock fed on CAN_CLK pin. Describe those clocks in the device
tree, along with the USB_EXTAL clock from which clkp2 is derived.
On Wed, Dec 24, 2014 at 08:57:14AM -0600, Nishanth Menon wrote:
> On 12/21/2014 11:43 AM, Rickard Strandqvist wrote:
> > Remove the function ti_bandgap_write_thot() that is not used anywhere.
> >
> > This was partially found by using a static code analysis program called
> > cppcheck.
> >
> > Si
Hello.
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo,
'renesas-devel-20141231-v3.19-rc2' tag. Here we add the CAN device tree support
for the R8A7790 SoC (unfortunately, it's impossible to test CAN on the Lager
board). It depends on the clk driver RCAN clock patch repost
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by th
Hello.
On 01/05/2015 11:10 PM, Sergei Shtylyov wrote:
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver
Hi,
On Mon, Jan 05, 2015 at 02:10:14PM -0600, Dave Gerlach wrote:
> >> Add a remoteproc driver to load the firmware for and boot the wkup_m3
> >> present on am33xx. The wkup_m3 is an integrated Cortex M3 that allows
> >> the SoC to enter the lowest possible power state by taking control from
> >>
Felipe,
On 01/02/2015 02:04 PM, Felipe Balbi wrote:
> On Fri, Jan 02, 2015 at 01:51:59PM -0600, Dave Gerlach wrote:
>> Add a remoteproc driver to load the firmware for and boot the wkup_m3
>> present on am33xx. The wkup_m3 is an integrated Cortex M3 that allows
>> the SoC to enter the lowest possib
Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by th
On 01/03/2015 04:37 PM, Arnd Bergmann wrote:
On Friday 02 January 2015 17:33:53 Murali Karicheri wrote:
I have no experience with IOMMU and may not offer much help here as I
originally wrote above. Will Deacon has added this API and probably able
to offer some help in this discussion.
Will Dea
On Sun, Dec 28, 2014 at 11:46:54AM +0100, Evgeni Dobrev wrote:
> This patch adds support for Seagate BlackArmor NAS220.
>
> The Seagate BlackArmor NAS 220 is a NAS system based on Marvell 88f6192. It
> has
> 32MB NAND and 128MB DRAM. It has two SATA slots, one Gigabit Ethernet port,
> two
> USB
On Mon, 2015-01-05 at 19:50 +0200, Daniel Baluta wrote:
> On Mon, Jan 5, 2015 at 6:42 PM, Joe Perches wrote:
> > On Mon, 2015-01-05 at 16:20 +0200, Daniel Baluta wrote:
> >> On Mon, Jan 5, 2015 at 3:09 PM, Joe Perches wrote:
> >> > On Mon, 2015-01-05 at 12:51 +0200, Daniel Baluta wrote:
> >> >> O
On Mon, Jan 5, 2015 at 6:42 PM, Joe Perches wrote:
> On Mon, 2015-01-05 at 16:20 +0200, Daniel Baluta wrote:
>> On Mon, Jan 5, 2015 at 3:09 PM, Joe Perches wrote:
>> > On Mon, 2015-01-05 at 12:51 +0200, Daniel Baluta wrote:
>> >> On Thu, Jan 1, 2015 at 2:10 AM, Kevin Tsai wrote:
>> >> > CM3232 i
On Mon, Jan 05, 2015 at 11:33:50AM -0600, Nishanth Menon wrote:
> On 01/05/2015 11:27 AM, Felipe Balbi wrote:
> > On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
> >> TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
> >> a fan (such as AFB02505HHB) over J1 conne
On 5 January 2015 at 11:19, Marc Zyngier wrote:
> On Mon, Jan 05 2015 at 10:08:18 am GMT, Peter Maydell
> wrote:
>> On 5 January 2015 at 09:50, Marc Zyngier wrote:
>>> On 31/12/14 09:25, Peter Maydell wrote:
Will Deacon and Marc Zyngier are currently in possession of that h/w.
I'm sur
On 01/05/2015 11:27 AM, Felipe Balbi wrote:
> On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
>> TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
>> a fan (such as AFB02505HHB) over J1 connector for various purposes.
>> Provide device tree node to enable the sam
On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
> TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
> a fan (such as AFB02505HHB) over J1 connector for various purposes.
> Provide device tree node to enable the same.
>
> Signed-off-by: Nishanth Menon
> ---
> V4
On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
> TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
> a fan (such as AFB02505HHB) over J1 connector for various purposes.
> Provide device tree node to enable the same.
>
> Signed-off-by: Nishanth Menon
have alre
Hi,
On Sun, Jan 04, 2015 at 08:55:01PM +0800, Sneeker Yeh wrote:
> > > So far Fujitsu Semiconductor got Synopsys internal case id , that is "
> > > Case: 8000679552".
> > > However the contents belongs this id cannot be referred except Fujitsu
> > > Semiconductor and Synopsys.
> > > Synopsis decid
Hi Thomas,
On 31/12/2014 11:32, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
>
> On Sat, 27 Dec 2014 12:00:35 +0100, Gregory CLEMENT wrote:
>
>> +spi-flash@0 {
>> +#address-cells = <1>;
>> +#si
On Mon, 2015-01-05 at 16:20 +0200, Daniel Baluta wrote:
> On Mon, Jan 5, 2015 at 3:09 PM, Joe Perches wrote:
> > On Mon, 2015-01-05 at 12:51 +0200, Daniel Baluta wrote:
> >> On Thu, Jan 1, 2015 at 2:10 AM, Kevin Tsai wrote:
> >> > CM3232 is an advanced ambient light sensor with I2C protocol inter
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off-by: Nishanth Menon
---
V4: Change format of the speed-map used.
V3: https://patchwork.kernel.org/patch/
On Mon 2015-01-05 15:41:41, One Thousand Gnomes wrote:
> > It would be really nice if the uart would register the line disciple as a
> > child device, then the line discipline would register whatever it wants.
>
> For almost every case this doesn't work. You need a tty interface as well
> because
Hi,
On Sun, Jan 04, 2015 at 09:16:01PM +0800, Sneeker Yeh wrote:
> > > Then dwc3 core won't be always created via sub node in platform glue
> > node,
> > > and vendors like us can just drop platform glue which don't have any
> > > specific platform code to wrap dwc3 core, and just directly use dwc
Hi,
On Mon, Jan 05, 2015 at 04:28:34PM +0100, Arnd Bergmann wrote:
> On Friday 02 January 2015 19:21:28 Felipe Balbi wrote:
> >
> > On Tue, Dec 30, 2014 at 11:12:51AM +0100, Arnd Bergmann wrote:
> > > On Monday 29 December 2014 01:52:04 Sneeker Yeh wrote:
> > > > > > +static int dwc3_mb86s70_remo
> It would be really nice if the uart would register the line disciple as a
> child device, then the line discipline would register whatever it wants.
For almost every case this doesn't work. You need a tty interface as well
because thats how you manage it.
> But that isn't how it works. The lin
To probe the bcm2835-pwm driver properly, this dts bindings has to be added
to the bcm2835 dtsi file.
In expectation of a bcm2835 clock driver, I've added fixed-clock clock binding.
To change the status of the gpio pins into pwm output pins, some additional
bindings has to be added but this has n
On Sun, 2015-01-04 at 11:16 +, Jonathan Cameron wrote:
> On 31/12/14 08:59, Nicholas Mc Guire wrote:
> > The timeout value to wait_for_completion_timeout is in jiffies but
> > the value being passed seems like it was intended to by microseconds
> > Note that the timeout was extremely long thus
On Monday 22 December 2014 16:32:06 Sean Cross wrote:
> Some PCIe ports gate power to the slot. In order to prevent system lockup,
> these boards must enable power to the slot before attempting communication
> over the PCI bus.
>
> Signed-off-by: Sean Cross
Could this be moved to the common pci
On Mon, Jan 05, 2015 at 08:25:16PM +0900, Inha Song wrote:
> + - clocks : Reference to the codec master clock
> + - clock-names : The clock should be named "mclk"
This should be done in the CODEC driver, not in the machine driver - the
CODEC always needs the clock, it's not something specific to
On Friday 02 January 2015 19:21:28 Felipe Balbi wrote:
>
> On Tue, Dec 30, 2014 at 11:12:51AM +0100, Arnd Bergmann wrote:
> > On Monday 29 December 2014 01:52:04 Sneeker Yeh wrote:
> > > > > +static int dwc3_mb86s70_remove_child(struct device *dev, void
> > > > > *unused)
> > > > > +{
> > > > > +
Just resend it with Thierry's request.
Thanks,
Inki Dae
Original Message
Subject: [PATCH v2 2/3] drm/panel: add s6e63j0x03 LCD panel driver
Date: Tue, 09 Dec 2014 18:29:05 +0900
From: Hyungwon Hwang
To: dri-de...@lists.freedesktop.org
CC: airl...@linux.ie, devicetree@vger.kern
On 2015년 01월 05일 23:19, Thierry Reding wrote:
> On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
>> Hi Thierry,
>>
>> Ping~.
>>
>> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
>> doesn't seem to care for a long time.
>
> I don't seem to have a copy of the v2 2/3 patch
On Mon, Jan 5, 2015 at 3:45 PM, Borislav Petkov wrote:
> On Sat, Jan 03, 2015 at 08:01:29AM +0530, punnaiah choudary kalluri wrote:
>> p is pointing to the stack memory.
>
> So you could go and allocate all that memory at driver init time and
> reuse it each time you handle an error instead of on
On Mon, 2015-01-05 at 17:18 +0900, Joonyoung Shim wrote:
> Hi Sjoerd,
>
> On 12/05/2014 04:27 AM, Sjoerd Simons wrote:
> > Add DTS for the Hardkernel Odroid XU3. The name of the DTS file is kept the
> > same as the vendors naming, which means it's prefixed with exynos5422
> > instead of exynos5800
Hello.
On 1/5/2015 1:21 PM, Suman Tripathi wrote:
Your patch summary seems too long.
This patch implements the function xgene_ahci_poll_reg_val to poll
PxCI for multiple IDENTIFY DEVICE commands to finish before
restarting the DMA engine in case of Port Multiplier.
Signed-off-by: Suman T
On 12/26/2014 01:40 PM, Rob Herring wrote:
On Tue, Dec 23, 2014 at 10:34 AM, Thor Thayer
wrote:
Hi,
What is the best way to queue devicetree child nodes so the node is passed
in the platform_device pointer to the probe() function?
Documentation/devicetree/usage-model.txt has the following:
"
On Fri, Jan 02, 2015 at 09:09:33PM +, Arnd Bergmann wrote:
> On Friday 02 January 2015 12:18:06 Suravee Suthikulanit wrote:
> > On 1/2/2015 5:55 AM, Lorenzo Pieralisi wrote:
> > > Hi Suravee,
> > >
> > > On Mon, Dec 29, 2014 at 07:32:44PM +, Suravee Suthikulpanit wrote:
> > >> >Hi,
> > >> >
Hi Thomas,
On 31/12/2014 10:57, Thomas Petazzoni wrote:
> Dear Gregory CLEMENT,
>
> On Sat, 27 Dec 2014 12:00:32 +0100, Gregory CLEMENT wrote:
>
>> this patch set adds the support for the Armada 385 GP board, this board
>> is pretty close to the Armada 385 RD one. It comes with a new revision
>>
Hi Andrew,
On 27/12/2014 12:50, Andrew Lunn wrote:
[...]
>> +
>> +i2c@11000 {
>> +status = "okay";
>> +clock-frequency = <10>;
>> +
>> +pca9555_0: pca9555@20 {
>
> I think Sebastian will co
On Mon, Jan 05, 2015 at 03:03:38PM +0100, Gregory CLEMENT wrote:
> Hi Andrew,
>
> >> + * Device Tree file for Marvell Armada 385 development board
> >> + * (RD-88F6820-GP)
> >> + *
> >> + * Copyright (C) 2014 Marvell
> >> + *
> >> + * Gregory CLEMENT
> >> + *
> >> + * This file is dual-licensed:
On Wed, Dec 31, 2014 at 07:41:43PM +0900, Inki Dae wrote:
> Hi Thierry,
>
> Ping~.
>
> Or is it ok to pick up this patch to my tree, exynos-drm-next? It
> doesn't seem to care for a long time.
I don't seem to have a copy of the v2 2/3 patch. All I found in my inbox
is the v2 0/3 cover-letter. Pl
On Mon, Jan 5, 2015 at 3:09 PM, Joe Perches wrote:
> On Mon, 2015-01-05 at 12:51 +0200, Daniel Baluta wrote:
>> On Thu, Jan 1, 2015 at 2:10 AM, Kevin Tsai wrote:
>> > CM3232 is an advanced ambient light sensor with I2C protocol interface.
>> > The I2C slave address is internally hardwired as 0x10
On pon, 2015-01-05 at 15:05 +0100, Linus Walleij wrote:
> On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski
> wrote:
>
> > The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
> > operate properly on GPIOs the main block clock 'mau_epll' must be
> > enabled.
> >
> > This was obs
On Fri, Dec 5, 2014 at 12:00 PM, Krzysztof Kozlowski
wrote:
> The audio subsystem on Exynos 5420 has separate clocks and GPIO. To
> operate properly on GPIOs the main block clock 'mau_epll' must be
> enabled.
>
> This was observed on Peach Pi/Pit and Arndale Octa (after enabling i2s0)
> after int
On Mon, Jan 05, 2015 at 07:33:06PM +0530, Suman Tripathi wrote:
> Reverted due to conflicts with the endian fix patches. Please rebase
> these two on top of them.
>
> Will do that .. I should have wait for the endian patch getting
> accepted. Sorry for that.
Ooh, please don't be sorry. It's com
Hi Andrew,
>> + * Device Tree file for Marvell Armada 385 development board
>> + * (RD-88F6820-GP)
>> + *
>> + * Copyright (C) 2014 Marvell
>> + *
>> + * Gregory CLEMENT
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your o
On Mon, Dec 29, 2014 at 08:52:47AM +0530, Suman Tripathi wrote:
> This patch addresses the issue with ATA_CMD_PACKET pio mode
> command for enumeration and device detection with ATAPI devices.
> The X-Gene AHCI controller has an errata in which it cannot clear
> the BSY bit after the PIO setup FIS.
Reverted due to conflicts with the endian fix patches. Please rebase
these two on top of them.
Will do that .. I should have wait for the endian patch getting
accepted. Sorry for that.
On Mon, Jan 5, 2015 at 7:29 PM, Tejun Heo wrote:
> On Mon, Jan 05, 2015 at 08:30:05AM -0500, Tejun Heo wrote:
Hello.
On 1/5/2015 4:13 PM, Geert Uytterhoeven wrote:
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock
gets derived from PLL1. The layout of the ADSPCKCR register is similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-
On Mon, Jan 05, 2015 at 08:30:05AM -0500, Tejun Heo wrote:
> On Mon, Jan 05, 2015 at 03:51:45PM +0530, Suman Tripathi wrote:
> > Due to H/W errata, the controller is unable to save the PMP
> > field fetched from command header before sending the H2D FIS.
> > When the device returns the PMP port fie
On Tue, Dec 16, 2014 at 10:19:35PM +0530, Suman Tripathi wrote:
> This patch addresses the issue with ATA_CMD_PACKET pio mode
> command for enumeration and device detection with ATAPI devices.It is the
> same issue as in patch
>
> www.spinics.net/lists/linux-ide/msg49092.html
>
> Signed-off-by: S
Hi Hans,
On Wed, Dec 24, 2014 at 08:19:18PM +0100, Hans de Goede wrote:
> The recent sun4i-usb-phy changes to add (preliminary) support for the oth phy,
> cause the ehci/ohci controllers to no longer work on sun4i / sun5i, because
> the phy driver refuses to load due to a missing usb0_reset reset
On Fri, Jan 02, 2015 at 01:10:14PM +, Daniel Stone wrote:
> Hi Ajay,
>
> On 17 December 2014 at 09:31, Javier Martinez Canillas <
> javier.marti...@collabora.co.uk> wrote:
>
> > On 12/16/2014 12:37 AM, Laurent Pinchart wrote:
> > >> You asked Ajay to change his series to use the video port an
Hi!
> > > N_HCI activates (registers the hci dev) on HCIUARTSETPROTO ioctl. A child
> > > device would need a way to specify the protocol I resume.
> > > N_MOUSE activates on a 'read' on the tty - and deactivates when the read
> > > completes.
> > > N_GSM0710 activates immediately that the ld
On Tue, Dec 30, 2014 at 9:21 PM, Sergei Shtylyov
wrote:
> Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7790 device tree.
>
> Based on the original patch by Konstantin Kozhevnikov
> .
>
> Signed-off-by: Sergei Shtylyov
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Tue, Dec 30, 2014 at 9:20 PM, Sergei Shtylyov
wrote:
> Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree.
>
> Based on the original patch by Konstantin Kozhevnikov
> .
>
> Signed-off-by: Sergei Shtylyov
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Mon, Jan 5, 2015 at 2:36 PM, Geert Uytterhoeven wrote:
>> + clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
>> +<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
>
> .git/rebase-apply/patch:18: space before tab in indent.
> <&cpg_clocks R8A7790_CLK_RCAN>, <&can_c
On Mon, Dec 29, 2014 at 11:06 PM, Sergei Shtylyov
wrote:
> Define the generic R8A7790 parts of the CAN0/1 device nodes.
>
> Signed-off-by: Sergei Shtylyov
Apart from the minor nit below
Acked-by: Geert Uytterhoeven
> --- renesas.orig/arch/arm/boot/dts/r8a7790.dtsi
> +++ renesas/arch/arm/boot/
On Sat, Dec 27, 2014 at 12:20 AM, Sergei Shtylyov
wrote:
> Define the generic R8A7791 parts of the CAN0/1 device nodes.
>
> Signed-off-by: Sergei Shtylyov
Apart from the minor nit below:
Acked-by: Geert Uytterhoeven
> --- renesas.orig/arch/arm/boot/dts/r8a7791.dtsi
> +++ renesas/arch/arm/boot
On Wed, Dec 24, 2014 at 11:17 PM, Sergei Shtylyov
wrote:
> Add the RCAN clock support to the R-Car generation 2 CPG driver. This clock
> gets derived from the USB_EXTAL clock, dividing it by 6. The layout of the
> RCANCKCR register is similar to those of the clocks supported by the
> 'clk-div
On Wed, Dec 17, 2014 at 12:22:09PM +0800, Anson Huang wrote:
> Add basic i.MX6SoloX Sabre Auto board support, currently
> only debug UART and uSDHC are supported on this board.
>
> Signed-off-by: Anson Huang
Applied, thanks.
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On Mon, Dec 29, 2014 at 11:04 PM, Sergei Shtylyov
wrote:
> The R-Car CAN controllers can derive the CAN bus clock not only from their
> peripheral clock input (clkp1) but also from the other internal clock (clkp2)
> and external clock fed on CAN_CLK pin. Describe those clocks in the device
> tree
On Mon, Jan 05, 2015 at 03:51:45PM +0530, Suman Tripathi wrote:
> Due to H/W errata, the controller is unable to save the PMP
> field fetched from command header before sending the H2D FIS.
> When the device returns the PMP port field in the D2H FIS, there is
> a mismatch and results in command com
On Mon, Jan 5, 2015 at 2:29 PM, Geert Uytterhoeven wrote:
> On Sat, Dec 27, 2014 at 12:18 AM, Sergei Shtylyov
> wrote:
>> The R-Car CAN controllers can derive the CAN bus clock not only from their
>> peripheral clock input (clkp1) but also from the other internal clock (clkp2)
>> and external clo
On Sat, Dec 27, 2014 at 12:18 AM, Sergei Shtylyov
wrote:
> The R-Car CAN controllers can derive the CAN bus clock not only from their
> peripheral clock input (clkp1) but also from the other internal clock (clkp2)
> and external clock fed on CAN_CLK pin. Describe those clocks in the device
> tree
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