Rockchip RK3288 hdmi is compatible with dw_hdmi
Signed-off-by: Andy Yan
---
Changes in v18:
- fix two compile errors when build as module
Changes in v17:
- parse resource and irq in platform driver
Changes in v16: None
Changes in v15:
- remove THIS_MODULE in platform driver
Changes in v14: N
Hi Liu Ying , Philipp:
On 2015年01月07日 10:39, Liu Ying wrote:
On 12/05/2014 02:22 PM, Andy Yan wrote:
We found Freescale imx6 and Rockchip rk3288 and Ingenic JZ4780
(Xburst/MIPS)
use the interface compatible Designware HDMI IP, but they also have some
lightly differences, such as phy pll con
On Wed, Jan 7, 2015 at 1:29 AM, Arnd Bergmann wrote:
> On Tuesday 06 January 2015 14:55:53 Ganapatrao Kulkarni wrote:
>> On Sat, Jan 3, 2015 at 2:40 AM, Arnd Bergmann wrote:
>> >> +int dt_get_cpu_node_id(int cpu)
>> >> +{
>> >> + struct device_node *dn = NULL;
>> >> +
>> >> + while ((dn =
Hi Arnd,
On Wed, Jan 7, 2015 at 1:32 AM, Arnd Bergmann wrote:
> On Tuesday 06 January 2015 15:04:26 Ganapatrao Kulkarni wrote:
>> On Sat, Jan 3, 2015 at 2:47 AM, Arnd Bergmann wrote:
>> > On Wednesday 31 December 2014 13:03:27 Ganapatrao Kulkarni wrote:
>> >> + cpu@00f {
>> >> +
Dear Gregory CLEMENT,
On Tue, 06 Jan 2015 23:00:54 +0100, Gregory CLEMENT wrote:
> On 06/01/2015 22:30, Ken Wilson wrote:
> > Create a new dt binding for the Armada 375 that supports up to
> > 3 chip selects but uses the same prescaler values and algorithm
> > as the basic orion binding.
>
> The
This patch reads charge delay from tsc DT node and writes to
REG_CHARGEDELAY register. If the charge delay is not specified in DT
then default value of 0x400(CHARGEDLY_OPENDLY) is used.
Signed-off-by: Vignesh R
---
v6:
- Move Documentation from DT patch to driver code.
v5:
- print out a war
This series is rebase of v4 onto v3.19-rc1. It also fixes concerns
expressed on v4 wrt simultaneous use of IIO and TSC.
I have tested this patch series on am335x-evm and Beaglebone black
with lcd7-cape.
Note that, these patches do not work as expected on Beaglebone Black
with BB-View 4.3 Cape fro
From: Brad Griffis
TSC interrupt handler had udelay to avoid reporting of false pen-up
interrupt to user space. This patch implements workaround suggesting in
Advisory 1.0.31 of silicon errata for am335x, thus eliminating udelay
and touchscreen lag. This also improves performance of touchscreen a
From: Brad Griffis
This patch makes the initial changes required to workaround TSC-false
pen-up interrupts. It is required to implement these changes in order to
remove udelay in the TSC interrupt handler and false pen-up events.
The charge step is to be executed immediately after sampling X+. He
In one shot mode, sequencer automatically disables all enabled steps at
the end of each cycle. (both ADC steps and TSC steps) Hence these steps
need not be saved in reg_se_cache for clearing these steps at a later
stage.
Also, when ADC wakes up Sequencer should not be busy executing any of the
conf
Previously, delta filtering was applied TSC co-ordinate readouts before
reporting a single value to user space. This patch replaces delta filtering
with median filtering. Median filtering sorts co-ordinate readouts, drops min
and max values, and reports the average of remaining values. This method
The charge delay value is by default 0x400. But it can be set to lower
values on some boards, as long as false pen-ups are avoided. Lowering the
value increases the sampling rate (though current sampling rate is
sufficient for TSC operation). In some boards, the value has to be
increased to avoid f
On Friday 02 January 2015 10:39 PM, Tony Lindgren wrote:
> * Vignesh R [141223 23:07]:
>> The charge delay value is by default 0x400. But it can be set to lower
>> values on some boards, as long as false pen-ups are avoided. Lowering the
>> value increases the sampling rate (though current sampl
This patch adds the device tree binding information for X-Gene PCIe DMA driver.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Tanmay Inamdar
---
Documentation/devicetree/bindings/dma/xgene-pciedma.txt | 16
1 file changed, 16 insertions(+)
create mode 100644 Documentation/dev
Signed-off-by: Mayuresh Chitale
Signed-off-by: Tanmay Inamdar
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ddb9ac8..9d24a02 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7228,6 +7228,14 @@ L: linux-arm-ker...@lists.infradead.o
This patch adds the APM X-Gene SOC PCIe DMA driver.
It can be used to transfer data between PCIe RC and PCIe
endpoints. It supports only dma slave transfers.
Mayuresh Chitale (4):
MAINTAINERS: Add entry for X-Gene PCIE DMA driver
Documentation: dt-bindings: Add the binding info for APM X-Gene
This patch implements DMA engine API for DMA controller on APM
X-Gene PCIe controller. DMA engine can support up to 4 channels per port
and up to 2048 outstanding requests per channel. This is intended
to be used on ports that are configured in EP mode or to transfer
data from a RC port that is co
Add the device tree nodes for APM X-Gene PCIe DMA engine.
Since X-Gene SOC supports maximum 5 PCIe ports, 5 dts nodes
are added.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Tanmay Inamdar
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 40 ++
1 file changed, 40 i
> > > -Original Message-
> > > From: shh@gmail.com [mailto:shh@gmail.com]
> > > Sent: Tuesday, December 23, 2014 3:58 PM
> > > To: linuxppc-...@lists.ozlabs.org; devicetree@vger.kernel.org; Wood
> > > Scott-B07421
> > > Cc: Medve Emilian-EMMEDVE1; Xie Shaohui-B21989
> > > Subject: [
On Tue, Jan 6, 2015 at 9:09 AM, Stephen Warren wrote:
> On 01/06/2015 03:37 AM, Tomeu Vizoso wrote:
>>
>> Following 6dbaff2b, the kernel expects that the bootloader has correctly
>> programmed the Tegra pinmux.
>>
>> DTs for the Jetson and the Venice2 had been updated already but this one
>> was l
This patch adds the missing support for OF to the adxl34x digital
accelerometer. This is a basic version which supports the main
optional parameters. This implementation copies the default values
to the adxl34x_platform_data structure and overrides the values
that are passed from the device tree.
This patch adds a basic documentation regarding the device tree
bindings of adxl34x digital accelerometer.
Signed-off-by: Walter Lozano
---
.../devicetree/bindings/input/adxl34x.txt | 53
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetre
On 12/05/2014 02:22 PM, Andy Yan wrote:
We found Freescale imx6 and Rockchip rk3288 and Ingenic JZ4780 (Xburst/MIPS)
use the interface compatible Designware HDMI IP, but they also have some
lightly differences, such as phy pll configuration, register width(imx hdmi
register is one byte, but rk3
On 1/6/2015 12:21 PM, Arnd Bergmann wrote:
> On Monday 05 January 2015 15:21:15 Ray Jui wrote:
>> +static const struct iproc_clk_ctrl mipipll_clk[BCM_CYGNUS_NUM_MIPIPLL_CLKS]
>> = {
>> +[BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
>> +.channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
>> +
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Jingoo Han
Acked-by: Bryan Wu
---
Changes v10:
Removed trivial get_brightness implementations
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for G
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Lee Jones
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Modified licensing text to GPLv2
Changes v6:
Added new line character at the end of line of dev_err()
Changes v5:
Move sky81452-backlight.h to inclu
From: Gyungoh Yoo
This patch set includes regulator and backlight driver for SKY81452.
Also it includes documents for device tree and module.
sky81452-regulator was already applied. So this series doesn't
include it.
v10:
Removed trivial get_brightness implementations for sky81452-backlight
v9:
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Lee Jones
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Made up the example for backlight DT
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Changed DT for regulator : 'lout' node should be defined under 'regulator'
Remo
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Add SKY81452 to the Trivial Devices list
Documentation/devicetre
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Lee Jones
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Nothing
Changes v7:
Nothing
Changes v6:
Nothing
Changes v5:
Nothing
Changes v4:
Nothing
Changes v3:
Nothing
Changes v2:
Added vendor prefix for Skyworks Solutions, I
From: Gyungoh Yoo
Signed-off-by: Gyungoh Yoo
Acked-by: Bryan Wu
---
Changes v10:
Nothing
Changes v9:
Nothing
Changes v8:
Renamed property names for backlight with vendor prefix
Modified gpio-enable property to generic property for GPIO
Made up the example for backlight DT
Changes v7:
Nothing
On 12/22/2014 3:19 AM, David Braun wrote:
> Hi,
> What is the status of
>
>* devicetree.org
Out of date. But still some useful info.
Another useful wiki (not very active, but more up to date) is
http://elinux.org/Device_Tree
Look at the section "Presentations and Papers". A very good
On Mon, 2015-01-05 at 05:21 -0600, Xie Shaohui-B21989 wrote:
> Hello Scott,
>
> Is this v3 OK?
>
> Best Regards,
> Shaohui Xie
> > -Original Message-
> > From: shh@gmail.com [mailto:shh@gmail.com]
> > Sent: Tuesday, December 23, 2014 3:58 PM
> > To: linuxppc-...@lists.ozlabs.org;
Am Dienstag, den 06.01.2015, 15:27 -0300 schrieb Ezequiel Garcia:
> On 01/04/2015 05:39 PM, Lucas Stach wrote:
>
> Hi Lucas,
>
> The driver looks mostly good. Just a few comments on my side.
>
> > Add support for the NAND flash controller found on NVIDIA
> > Tegra 2/3 SoCs. This is a largely rew
Am Dienstag, den 06.01.2015, 00:41 +0100 schrieb Stefan Agner:
> Hi Lucas,
>
> Thanks for picking that up!
>
> I did some short benchmarks on Colibri T20 V1.2, L4T. Write/read speeds
> I measured on the YAFFS2 based file system:
>
> # dd if=/dev/zero of=test bs=50M count=1 conv=fdatasync
> 1+0 r
On Tue, Jan 6, 2015 at 5:34 PM, Beomho Seo wrote:
> Thank you for review.
>
> On 01/07/2015 01:54 AM, Rob Herring wrote:
>> On Mon, Jan 5, 2015 at 11:45 PM, Beomho Seo wrote:
>>> This patch device tree binding documentation for rt5033 multifunction
>>> device.
[...]
>>> + compati
Thank you for review.
On 01/07/2015 01:54 AM, Rob Herring wrote:
> On Mon, Jan 5, 2015 at 11:45 PM, Beomho Seo wrote:
>> This patch device tree binding documentation for rt5033 multifunction device.
>>
>> Cc: Sebastian Reichel
>> Cc: Lee Jones
>> Cc: Mark Brown
>> Cc: Rob Herring
>> Cc: Pawel
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock
gets derived from PLL1. The layout of the ADSPCKCR register is similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-linear, so can't be supported by that driver...
Based on
Add the ADSP clock support to the R-Car generation 2 CPG driver. This clock
gets derived from PLL1. The layout of the ADSPCKCR register is similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-linear, so can't be supported by that driver...
Based on
On Tue, 6 Jan 2015, Rob Herring wrote:
> On Tue, Jan 6, 2015 at 2:13 PM, wrote:
> > From: Alan Tull
> >
> > New bindings document for Altera fpga manager.
> >
> > Signed-off-by: Alan Tull
>
> Acked-by: Rob Herring
>
> Like I said, this binding doesn't look like it will change other than
> p
CM3232 is an advanced ambient light sensor with I2C protocol interface.
The I2C slave address is internally hardwired as 0x10 (7-bit). Writing
to configure register is byte mode, but reading ALS register requests to
use word mode for 16-bit resolution.
v2:
Removed unused CM3232_CMD_ALS_HS.
Modifi
On Tue, Jan 6, 2015 at 2:13 PM, wrote:
> From: Alan Tull
>
> New bindings document for Altera fpga manager.
>
> Signed-off-by: Alan Tull
Acked-by: Rob Herring
Like I said, this binding doesn't look like it will change other than
perhaps additional optional properties, so it can go into
Docum
On Tue, Jan 6, 2015 at 12:36 PM, Mathieu Poirier
wrote:
> On 6 January 2015 at 10:02, Rob Herring wrote:
>> On Tue, Jan 6, 2015 at 10:45 AM, wrote:
>>> From: Mathieu Poirier
>>>
>>> Among other things, the serial power controller (SPC) controls power to
>>> the A7 and A15 clusters. Theses clu
Hi Ken,
On 06/01/2015 22:30, Ken Wilson wrote:
> Create a new dt binding for the Armada 375 that supports up to
> 3 chip selects but uses the same prescaler values and algorithm
> as the basic orion binding.
There was already a patch that have been sent for this:
http://thread.gmane.org/gmane.lin
Create a new dt binding for the Armada 375 that supports up to
3 chip selects but uses the same prescaler values and algorithm
as the basic orion binding.
Update the Armada 370 so that it supports up to 4 chip selects.
This has been tested on the Armada 375 with multiple SPI-NOR chips.
Signed-of
Hi Ken
> -static const struct orion_spi_dev armada_spi_dev_data = {
> +static const struct orion_spi_dev armada_370_spi_dev_data = {
> .typ = ARMADA_SPI,
> .min_divisor = 1,
> .max_divisor = 1920,
> .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
> + .num_cs = 4,
> +};
>
On 01/06/2015 06:30 PM, Ken Wilson wrote:
> Create a new dt binding for the Armada 375 that supports up to
> 3 chip selects but uses the same prescaler values and algorithm
> as the basic orion binding.
>
> Update the Armada 370 so that it supports up to 4 chip selects.
>
> This has been tested o
On 01/06/2015 02:50 PM, Will Deacon wrote:
On Fri, Jan 02, 2015 at 10:33:53PM +, Murali Karicheri wrote:
On 01/02/2015 03:45 PM, Rob Herring wrote:
On Fri, Jan 2, 2015 at 11:20 AM, Murali Karicheri wrote:
On 12/26/2014 02:33 PM, Rob Herring wrote:
On Wed, Dec 24, 2014 at 4:11 PM, Murali
From: Phani Movva
Add the devicetree binding document for Cosmic Circuits 10001 ADC device.
Reviewed-by: Andrew Bresticker
Acked-by: Rob Herring
Signed-off-by: Phani Movva
Signed-off-by: Naidu Tellapati
Signed-off-by: Ezequiel Garcia
---
.../devicetree/bindings/iio/adc/cc10001_adc.txt|
From: Phani Movva
This commit adds support for Cosmic Circuits 10001 10-bit ADC device.
Reviewed-by: Andrew Bresticker
Signed-off-by: Phani Movva
Signed-off-by: Naidu Tellapati
[ezequiel: code style cleaning]
Signed-off-by: Ezequiel Garcia
---
drivers/iio/adc/Kconfig | 11 ++
drivers
Reviewed-by: Andrew Bresticker
Acked-by: Rob Herring
Signed-off-by: Ezequiel Garcia
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-pre
This series add the support for an ADC IP block from Cosmic Circuits.
The patchset is based on v3.19-rc3.
As agreed with Rob, this series drops the vendor prefix in the
adc-reserved-channels DT property. This property is generic enough to
be used in other drivers (at91 is a potential candidate).
On Monday 05 January 2015 15:21:15 Ray Jui wrote:
> +static const struct iproc_clk_ctrl mipipll_clk[BCM_CYGNUS_NUM_MIPIPLL_CLKS]
> = {
> + [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
> + .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
> + .enable = enable_val(0x4, 12, 6, 18),
> +
From: Alan Tull
Add documentation under drivers/staging for new fpga manager's
sysfs interface.
Signed-off-by: Alan Tull
---
v5 : (actually second version, but keeping version numbers
aligned with rest of patch series)
Move document to drivers/staging/fpga/Documentation/ABI
v6 :
From: Alan Tull
Add driver to fpga manager framework to allow configuration
of FPGA in Altera SoCFPGA parts.
Signed-off-by: Alan Tull
Acked-by: Michal Simek
---
v2: fpga_manager struct now contains struct device
fpga_manager_register parameters now take device
v3: skip a version to align
From: Alan Tull
New bindings document for Altera fpga manager.
Signed-off-by: Alan Tull
---
v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
v6 : No change in this patch for v6 of the patch set
v7 : No change in this patch for v7 of the patch set
v8 : Make compatible string
From: Alan Tull
Supports standard ops for low level FPGA drivers.
Various manufacturors' FPGAs can be supported by adding low
level drivers. Each driver needs to register its ops
using fpga_mgr_register().
Exports methods of doing operations to program FPGAs. These
should be sufficient for ind
From: Alan Tull
v8 changes the compatible string for SOCFPGA FPGA managers
to be more chip specific.
"altr,fpga-mgr" becomes "altr,socfpga-fpga-mgr"
Thanks,
Alan
Alan Tull (4):
doc: add bindings document for altera fpga manager
fpga manager: add sysfs interface document
staging: fpga man
On Tuesday 06 January 2015 15:04:26 Ganapatrao Kulkarni wrote:
> On Sat, Jan 3, 2015 at 2:47 AM, Arnd Bergmann wrote:
> > On Wednesday 31 December 2014 13:03:27 Ganapatrao Kulkarni wrote:
> >> + cpu@00f {
> >> + device_type = "cpu";
> >> + compat
On Tuesday 06 January 2015 14:55:53 Ganapatrao Kulkarni wrote:
> On Sat, Jan 3, 2015 at 2:40 AM, Arnd Bergmann wrote:
> >> +int dt_get_cpu_node_id(int cpu)
> >> +{
> >> + struct device_node *dn = NULL;
> >> +
> >> + while ((dn = of_find_node_by_type(dn, "cpu"))) {
> >> + const
On Fri, Jan 02, 2015 at 10:33:53PM +, Murali Karicheri wrote:
> On 01/02/2015 03:45 PM, Rob Herring wrote:
> > On Fri, Jan 2, 2015 at 11:20 AM, Murali Karicheri
> > wrote:
> >> On 12/26/2014 02:33 PM, Rob Herring wrote:
> >>> On Wed, Dec 24, 2014 at 4:11 PM, Murali Karicheri
> +
On 6 January 2015 at 10:02, Rob Herring wrote:
> On Tue, Jan 6, 2015 at 10:45 AM, wrote:
>> From: Mathieu Poirier
>>
>> Among other things, the serial power controller (SPC) controls power to
>> the A7 and A15 clusters. Theses clusters also happen to contains the
>> coresight tracers used for
On 01/04/2015 05:39 PM, Lucas Stach wrote:
Hi Lucas,
The driver looks mostly good. Just a few comments on my side.
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2/3 SoCs. This is a largely reworked version of the driver
> started by Thierry.
>
> Signed-off-by: Thierry Redi
On Fri, Dec 19, 2014 at 02:55:20PM +0100, Sylwester Nawrocki wrote:
> This series is an attempt to resolve the CDCLK clock gating issue on Odroid
> X2/U3 as reported by Daniel Drake [1], by exposing the CDCLK gate clock
> (and the two other clocks) through clk API.
This all looks basically fine
On Fri, Dec 19, 2014 at 02:55:36PM +0100, Sylwester Nawrocki wrote:
> I2S1, I2S2 on Exynos4 SoC series have limited functionality compared
> to I2S0, "samsung,s3c6410-i2s" compatible should be used for them.
>
> Signed-off-by: Sylwester Nawrocki
> ---
This should probably go to stable as a bug f
On Fri, Dec 19, 2014 at 02:55:22PM +0100, Sylwester Nawrocki wrote:
> Tidy up the samsung_i2s_get_driver_data() function by using
> IS_ENABLE() instead of #ifdef and add missing braces for
> the 'else' part. Also ensure we are not dereferencing NULL
> 'match' pointer.
This doesn't apply against cu
On Fri, Dec 19, 2014 at 02:55:21PM +0100, Sylwester Nawrocki wrote:
> The 'gpios' field in 'struct i2s' is now unused, this change
> seems to be missing in commit 0429ffeff460c4302bd1520e6
> ("ASoC: samsung: Remove obsolete GPIO based DT pinmuxing").
Applied, thanks.
signature.asc
Description: D
Hi Hans,
On 27/12/2014 13:58, Hans de Goede wrote:
> Hi Gregory,
>
> Thanks for working on this. Overall the patch-set / concept looks good,
> you can add "Acked-by: Hans de Goede " to the first
> 2 patches.
Thanks for your review. About the second patch as the change in the regulator
framework
The following patches add arm pl353 static memory controller driver for
xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and
nor/sram memory interfaces. The current implementation supports only a
single SMC instance and nand specific configuration.
xilinx zynq TRM link:
http://w
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v5:
- Configure the nand timing parameters as per the onfi spec
Changes
On Fri, Dec 19, 2014 at 02:55:26PM +0100, Sylwester Nawrocki wrote:
> Gating the I2S bus clock in the driver's runtime PM callbacks has
> currently really no effect since the clock is being enabled
> in the DAI's probe() and thus is permanently turned on. Now we just
> move the enable to the platfo
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v5:
- Added pl353_smc_get_clkrate function, made pl353_smc_set_cycles as public
API
- Remov
The following patches add arm pl353 static memory controller driver for
xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and
nor/sram memory interfaces. The current implementation supports only a
single SMC instance and nand specific configuration.
xilinx zynq TRM link:
http://w
Added notes about the controller and driver
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v5:
- Fixed the review comments
Changes in v4:
- None
---
Documentation/mtd/nand/pl353-nand.txt | 92 +
1 files changed, 92 insertions(+), 0 deletions(-)
create
Added software ecc support.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v5:
- None
Changes in v4:
- Updated the driver to sync with pl353_smc driver APIs
---
drivers/mtd/nand/pl353_nand.c | 164 +
1 files changed, 164 insertions(+), 0 deletion
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors.
Signed-off-by: Punnaiah Choudary Kalluri
---
MAINTAINERS |1 +
drivers/edac/Kconfig |7 +
drivers/edac/Mak
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v5:
- Removed timing properties
Changes in v4:
- none
Changes in v3:
- none
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano
Hi Doug,
Am Montag, 15. Dezember 2014, 16:22:20 schrieb Doug Anderson:
> Specifying these rails should eventually let us do UHS.
>
> Signed-off-by: Doug Anderson
> ---
> Changes in v3: None
> Changes in v2:
> - Fix subject line
>
> arch/arm/boot/dts/rk3288-evb.dtsi | 2 ++
> 1 file changed, 2
Added EDAC support for reporting the ecc errors of synopsys ddr controller.
The ddr ecc controller corrects single bit errors and detects double bit
errors.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes for v8:
- Fixed the review comments that are missed in v7
- Added comment for ECC contr
On Tue, Jan 6, 2015 at 9:30 AM, Andrew Bresticker wrote:
> On Tue, Jan 6, 2015 at 5:06 AM, Thierry Reding
> wrote:
>>
>> Back when we merged the nyan-big DTS there was some discussion and it
>> was concluded that the devices are very similar, with the panel being
>> one notable exception. So I
On Fri, Dec 26, 2014 at 01:28:20PM -0600, Felipe Balbi wrote:
> STATUS register can be modified by the HW, so we
> should bypass cache because of that.
>
> In the case of INT[12] registers, they are the ones
> that actually clear the IRQ source at the time they
> are read. If we rely on the cache
On Fri, Dec 26, 2014 at 01:28:21PM -0600, Felipe Balbi wrote:
> If we don't tell regmap-irq that our first status
> register is at offset 1, it will try to read offset
> zero, which is the chipid register.
>
> Fixes: 44b4dc6 mfd: tps65218: Add driver for the TPS65218 PMIC
> Cc: # v3.15+
> Cc: Kee
Hi,
Please ignore this patch. I will resend this patch with modification history.
Regards,
Punnaiah
On Tue, Jan 6, 2015 at 11:05 PM, Punnaiah Choudary Kalluri
wrote:
> Added EDAC support for reporting the ecc errors of synopsys ddr controller.
> The ddr ecc controller corrects single bit erro
On Tue, Jan 6, 2015 at 5:06 AM, Thierry Reding wrote:
> Cc'ing Dylan and Olof. I've verified that the resulting nyan-big DTB
> after this series is exactly the same as before (well, except where
> changes were made on purpose), but I'd like an Ack from either of you
> regarding the split into the
On Tue, Jan 6, 2015 at 10:59 AM, Ezequiel Garcia
wrote:
> Hi Rob,
>
> Thanks a lot for the comments.
>
> On 01/06/2015 01:30 PM, Rob Herring wrote:
>> On Tue, Jan 6, 2015 at 9:29 AM, Ezequiel Garcia
>> wrote:
>>> From: Phani Movva
>>>
>>> Add the devicetree binding document for Cosmic Circuits 1
On 01/06/2015 03:37 AM, Tomeu Vizoso wrote:
In preparation for adding the DT for the nyan-blaze board.
"git format-patch -M" and/or "git format-patch -C" should make this
patch a lot easier to review, since it'll show the patch as a file
copy/rename rather than a full-file cut/paste.
--
To u
On 01/06/2015 03:37 AM, Tomeu Vizoso wrote:
Following 6dbaff2b, the kernel expects that the bootloader has correctly
programmed the Tegra pinmux.
DTs for the Jetson and the Venice2 had been updated already but this one
was left behind.
So this setup is true for NVIDIA-controlled development/re
On Tue, Jan 6, 2015 at 10:45 AM, wrote:
> From: Mathieu Poirier
>
> Among other things, the serial power controller (SPC) controls power to
> the A7 and A15 clusters. Theses clusters also happen to contains the
> coresight tracers used for HW assisted tracing.
>
> By modellling these to power d
Hi Rob,
Thanks a lot for the comments.
On 01/06/2015 01:30 PM, Rob Herring wrote:
> On Tue, Jan 6, 2015 at 9:29 AM, Ezequiel Garcia
> wrote:
>> From: Phani Movva
>>
>> Add the devicetree binding document for Cosmic Circuits 10001 ADC device.
>>
>> Signed-off-by: Phani Movva
>> Signed-off-by: N
On Mon, Jan 5, 2015 at 11:45 PM, Beomho Seo wrote:
> This patch device tree binding documentation for rt5033 multifunction device.
>
> Cc: Sebastian Reichel
> Cc: Lee Jones
> Cc: Mark Brown
> Cc: Rob Herring
> Cc: Pawel Moll
> Cc: Mark Rutland
> Cc: Ian campbell
> Cc: Kumar Gala
> Signed-o
From: Mathieu Poirier
Among other things, the serial power controller (SPC) controls power to
the A7 and A15 clusters. Theses clusters also happen to contains the
coresight tracers used for HW assisted tracing.
By modellling these to power domains in a way that is comprehensible to
the generic
On Tue, Jan 6, 2015 at 9:29 AM, Ezequiel Garcia
wrote:
> From: Phani Movva
>
> Add the devicetree binding document for Cosmic Circuits 10001 ADC device.
>
> Signed-off-by: Phani Movva
> Signed-off-by: Naidu Tellapati
> [Ezequiel: minor style cleaning]
> Signed-off-by: Ezequiel Garcia
> ---
>
On Mon, 22 Dec 2014, Rob Herring wrote:
> On Fri, Dec 19, 2014 at 10:45 AM, wrote:
> > From: Alan Tull
> >
> > New bindings document for Altera fpga manager.
> >
> > Signed-off-by: Alan Tull
> > ---
> > v5 : Move bindings to drivers/staging/fpga/Documentation/bindings
> >
> > v6 : No change in
For devices which have a complete register for themselves, it is possible to
place them next to the syscon device with overlapping reg ranges. The same is
not possible for devices which only occupy bitfields in registers shared with
other users.
For devices that are completely controlled by bitfiel
Acked-by: Rob Herring
Signed-off-by: Ezequiel Garcia
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b1df0ad..014770f
From: Phani Movva
This commit adds support for Cosmic Circuits 10001 10-bit ADC device.
Signed-off-by: Phani Movva
Signed-off-by: Naidu Tellapati
[ezequiel: code style cleaning]
Signed-off-by: Ezequiel Garcia
---
drivers/iio/adc/Kconfig | 11 ++
drivers/iio/adc/Makefile | 1 +
From: Phani Movva
Add the devicetree binding document for Cosmic Circuits 10001 ADC device.
Signed-off-by: Phani Movva
Signed-off-by: Naidu Tellapati
[Ezequiel: minor style cleaning]
Signed-off-by: Ezequiel Garcia
---
.../devicetree/bindings/iio/adc/cc10001_adc.txt| 22 ++
This series add the support for an ADC IP block from Cosmic Circuits.
The patchset is based on v3.19-rc3.
Rob/Mark: Jonathan has asked for an ack of the devicetree binding. Do you
think you can take a look to that?
Thanks a lot!
--
Changes from v5:
* Fixed CC10001_ADC_CH_MASK macro definition,
Hi Heiko,
Am Dienstag, den 06.01.2015, 12:49 +0100 schrieb Heiko Stübner:
> Hi Philipp,
>
> Am Samstag, 6. Dezember 2014, 00:31:46 schrieb Andy Yan:
> > > I am happy with the series so far. Pending Acks from the device tree
> > > maintainers for the new binding documents, I'd like to apply either
Hi Arnd,
Thanks for the comments!
On 12/12/2014 07:33 PM, Arnd Bergmann wrote:
> On Friday 12 December 2014 19:14:01 Stanimir Varbanov wrote:
>> +config ARCH_APQ8084
>> + bool "Enable support for APQ8084"
>> + select HAVE_ARM_ARCH_TIMER
>> + select PCI
>> + select PCI_DOMA
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