On Tue, Jan 20, 2015 at 11:17:56AM +0200, Stanimir Varbanov wrote:
> + MSM_MUX_blsp1_spi,
> + MSM_MUX_blsp2_spi,
> + MSM_MUX_blsp3_spi,
The above three need to be renamed to blsp_spiX_csX to denote which SPI and chip
select they modify.
> + MSM_MUX_blsp_i2c1,
> + MSM_MUX_bl
On Wed, Jan 28, 2015 at 03:45:19PM +, Rob Herring wrote:
> On Wed, Jan 28, 2015 at 5:05 AM, Catalin Marinas
> wrote:
> > On Tue, Jan 27, 2015 at 06:55:15PM +, Murali Karicheri wrote:
> >> How about having the logic like this?
> >>
> >> ret = of_dma_get_range(np, &dma_addr, &paddr, &s
On 29 January 2015 at 01:36, Mark Brown wrote:
> On Fri, Jan 23, 2015 at 04:14:50PM +0530, Viresh Kumar wrote:
>
>> +- opp-listN:
>> + List of nodes defining performance points. Following belong to the nodes
>> + within the opp-lists.
>
> Why is there the N here? It doesn't correspond to the ex
Add compatible strings for the PCIe IP blocks present on several Tegra
chips. The primary objective here is to avoid checkpatch warnings,
per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
Signed-off-by: Paul Walmsley
Cc: Thierry Reding
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutlan
Add compatible strings for the timer IP blocks present on several
Tegra chips. The primary objective here is to avoid checkpatch
warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt docu
Add compatible strings for the AHB "gizmo" IP block present on several
Tegra chips. The primary objective here is to avoid checkpatch
warnings, per:
http://marc.info/?l=linux-tegra&m=142201349727836&w=2
Signed-off-by: Paul Walmsley
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Cam
On Wed, Jan 28, 2015 at 04:41:44PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 1/25/2015 10:30 PM, Geert Uytterhoeven wrote:
>
> >>Renesas has made some changes to the Henninger low cost board hardware and
> >>at
> >>the same time decided to rename the board to Porter.
>
> >Which changes?
>
On Tue, Jan 27, 2015 at 11:36:39AM +0800, Bo Shen wrote:
> From: Alexander Morozov
>
> The WM8904 and WM8918 has the same data type, while the WM8912
> has different data type. So, use the data in dt ids table to
> distinguish them.
Applied both, thanks - please use subjct lines matching the sty
On Wed, Jan 28, 2015 at 03:16:05PM +0100, Peter Rosin wrote:
> From: Peter Rosin
>
> Hi!
>
> [ Note that the dt change is in patch 5/7, for those only interested
> in that particular bit. ]
Applied all except the register default change, thanks.
signature.asc
Description: Digital signature
On Wed, Jan 28, 2015 at 11:51:05AM +0100, Tomeu Vizoso wrote:
> This is used in the Tegra-based Chromebooks.
This doesn't apply due to the dependency on the previous patch, and
also...
> static const struct snd_kcontrol_new tegra_max98090_controls[] = {
> SOC_DAPM_PIN_SWITCH("Headphones"),
Hi,
On Wed, Jan 28, 2015 at 11:22:05PM +0100, Stefan Wahren wrote:
> > Mark Brown hat am 27. Januar 2015 um 20:43 geschrieben:
> > On Tue, Jan 27, 2015 at 07:35:09PM +0100, Stefan Wahren wrote:
> > > > Mark Brown hat am 27. Januar 2015 um 01:16
> > > > geschrieben:
> >
> > > > > okay i understan
* Roger Quadros [150128 04:15]:
> On 28/01/15 04:19, Chanwoo Choi wrote:
> >>
> >> I still fail to understand that we need to call disable_irq() in
> >> .suspend() and
> >> enable_irq() in .resume()
> >>
> >> can you point me to any other drivers doing so?
> >
> > You can refer the suspend funct
Hi Samuel,
Please ignore this serie. It does not build.
Sorry for that.
Best Regards
Christophe
On 28/01/2015 21:17, Christophe Ricard wrote:
Hi Samuel,
This is a pre-send with an update including your comments on patch #20.
Patch #27 is not yet modified. I hope to send something for review to
Ulf,
On Tue, Jan 27, 2015 at 7:18 AM, Ulf Hansson wrote:
>> I asked Addy to post upstream against mmc_send_tuning(), but I guess
>> he didn't (he posted against Alex's NAKed patch instead).
>>
>> ...when I talked to him about it, Addy was asserting that when tuning
>> fails it is important (at le
On Wed, Jan 28, 2015 at 06:37:36PM -0600, Aaron Sierra wrote:
> - Original Message -
> > From: "Brian Norris"
> > I was thinking about this a bit more, and it seems like we could really
> > just factor this all into the core nand_base code with something like
> > the following patch. It c
On Wednesday 28 January 2015 15:43:57 Murali Karicheri wrote:
> > this. Hope I am on the right track.
>
> Reproduced this. Following errors seen when building the modules.
>
>LD [M] drivers/net/ethernet/ti/keystone_netcp.o
> drivers/net/ethernet/ti/netcp_ethss.o: In function `init_module':
>
age while looking into CONFIG_ARCH_DIGICOLOR. That
Kconfig macro entered linux-next in next-20150128. But there's no
Kconfig symbol ARCH_DIGICOLOR yet in linux-next.
As you might be aware I try to check each linux-next release for Kconfig
oddities. One of the oddities I tend _not_ to report are th
On Tue, Jan 27, 2015 at 06:01:45PM +, Lorenzo Pieralisi wrote:
> In the function of_pci_get_host_bridge_resources() if the parsing of
> ranges fails, previously allocated resources inclusive of bus_range
> are not freed and are not expected to be freed by the function caller
> on error return.
Ulf Hansson wrote:
> On 28 January 2015 at 13:41, Tobias Jakobi wrote:
>> Hello!
>>
>> Jaehoon Chung wrote:
>>> mmc core supported to hw_reset function.
>>> So i think we can use it. It's called at only initial time to clear the
>>> previous status.
>>> But i think it can be called at reboot time
On 01/27/2015 05:28 PM, Arnd Bergmann wrote:
On Tuesday 20 January 2015 10:53:36 Murali Karicheri wrote:
On 01/19/2015 03:11 PM, David Miller wrote:
From: Murali Karicheri
Date: Thu, 15 Jan 2015 19:10:03 -0500
The Network Coprocessor (NetCP) is a hardware accelerator that processes
Ethernet p
From: Peter Rosin
Add helper functions to allow drivers to specify several disjoint
ranges for a variable. In particular, there is a codec (PCM512x) that
has a hole in its supported range of rates, due to PLL and divider
restrictions.
This is like snd_pcm_hw_constraint_list(), but for ranges ins
On Tue, 2015-01-20 at 12:15 +0200, Ivan T. Ivanov wrote:
> This type of volatage ADC could be found in Qualcomm's SPMI PMIC's.
> I'm sorry that it took me so long to send the updated version.
>
> Changes since v4.
> - Addressed review comments from Hartmut Knaack and Jonathan Cameron:
> Fixed s
On 01/28/2015 12:43 PM, Murali Karicheri wrote:
On 01/28/2015 11:49 AM, Murali Karicheri wrote:
On 01/27/2015 05:28 PM, Arnd Bergmann wrote:
On Tuesday 20 January 2015 10:53:36 Murali Karicheri wrote:
On 01/19/2015 03:11 PM, David Miller wrote:
From: Murali Karicheri
Date: Thu, 15 Jan 2015 19
Hello Arend,
Thanks for your feedback.
On 01/28/2015 03:03 PM, Arend van Spriel wrote:
> On 01/28/15 11:10, Javier Martinez Canillas wrote:
>> &dp {
>> @@ -531,17 +538,33 @@
>> status = "okay";
>> num-slots =<1>;
>> broken-cd;
>> +cap-sdio-irq;
>
> This seems like an unrela
From: Peter Rosin
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index 874723c36d65..4c65eb9ab59b 100644
--- a/sound/soc/codecs/pcm512x.c
+++ b/sound/soc/cod
From: Peter Rosin
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c | 441 ++--
sound/soc/codecs/pcm512x.h | 5
Srinivas,
On 01/28/2015 05:34 PM, Srinivas Kandagatla wrote:
>> -- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted at
>> -initialization and prior we start the power up procedure of the card. It
>> -will be de-asserted right after the power has been provided to the card
On Wed, 2015-01-28 at 03:21PM +0100, Michal Simek wrote:
> On 01/27/2015 01:38 AM, Andreas Färber wrote:
> > Am 26.01.2015 um 20:49 schrieb Soren Brinkmann:
> >> In one pinctrl node, a 'bias-disable' property is erroneously assigned a
> >> value.
> >>
> >> Fixes: ARM: zynq: DT: Add pinctrl informat
From: Peter Rosin
Signed-off-by: Peter Rosin
---
sound/soc/codecs/pcm512x.c |2 +-
sound/soc/codecs/pcm512x.h |6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c
index e5f2fb884bf3..874723c36d65 100644
--- a/s
Nokia N900 contains bluetooth module connected on serial
port. Unfortunately, serial and bluetooth are rather closely coupled,
so standard serial driver can not be used, and we really don't want
/dev/ttyS1 to be published for internal port of bluetooth
stack... Hence solution below.
Signed-off-by:
On Mon, Jan 26, 2015 at 06:49:01PM +, Murali Karicheri wrote:
> On 01/25/2015 08:32 AM, Laurent Pinchart wrote:
> > Hi Murali,
> >
> > Thank you for the patch.
> >
> > On Friday 23 January 2015 17:32:34 Murali Karicheri wrote:
> >> Function of_iommu_configure() is called from of_dma_configure()
Add nci_core_conn_create handler according to NFC Forum NCI specification.
It is necessary for example for secure element handling.
Signed-off-by: Christophe Ricard
---
include/net/nfc/nci.h | 25 +
include/net/nfc/nci_core.h | 2 ++
net/nfc/nci/core.c | 24
Some st21nfcb features are only available through HCI commands. Those
HCI commands can be address over NCI by sending data using a dynamic
conn_id. This is useful for example for Secure Element communication.
The HCI core brings the minimal HCI functions required to communicate with
a secure eleme
This patch adds common library for sensorhub iio drivers.
Signed-off-by: Karol Wrona
Acked-by: Kyungmin Park
---
drivers/iio/common/ssp_sensors/ssp_iio.c| 107 +++
drivers/iio/common/ssp_sensors/ssp_iio_sensor.h | 70 +++
2 files changed, 177 insertion
On 01/28/2015 11:49 AM, Murali Karicheri wrote:
On 01/27/2015 05:28 PM, Arnd Bergmann wrote:
On Tuesday 20 January 2015 10:53:36 Murali Karicheri wrote:
On 01/19/2015 03:11 PM, David Miller wrote:
From: Murali Karicheri
Date: Thu, 15 Jan 2015 19:10:03 -0500
The Network Coprocessor (NetCP) is
This patch adds accelerometer iio driver which uses sensorhub as data
provider.
Signed-off-by: Karol Wrona
Acked-by: Kyungmin Park
---
drivers/iio/accel/Makefile |1 +
drivers/iio/accel/ssp_accel_sensor.c | 169 ++
2 files changed, 170 insertions(+
From: Peter Rosin
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described for the PCM5122 chip in t
NFC_EVT_TRANSACTION is not managed so far.
Forward event information up to user space in order to tell an application
that some user action(s) are needed.
Forwarded information are:
- SE host generating the event
- Application IDentifier doing the operation
- Applications parameters
Signed-off-b
Hi Olof,
On Tue, Jan 27, 2015 at 03:01:41PM -0800, Olof Johansson wrote:
> On Wed, Jan 14, 2015 at 10:40:32AM +0200, Baruch Siach wrote:
> > cx92755.dtsi describes CX92755 on chip peripherals. conexant_equinox.dts
> > describes the Equinox evaluation board for the CX92755 SoC.
> >
> > Acked-by: A
Add nci_nfcee_discover handler according to NFC Forum NCI specification.
It is necessary for example for secure element handling.
Signed-off-by: Christophe Ricard
---
include/net/nfc/nci_core.h | 4
net/nfc/nci/core.c | 17 +
net/nfc/nci/ntf.c | 29
On 28 January 2015 at 11:17, Javier Martinez Canillas
wrote:
> Hello Ulf,
>
> On Mon, Jan 19, 2015 at 10:13 AM, Ulf Hansson wrote:
>> System on chip designs may specify a specific MMC power sequence. To
>> successfully detect an (e)MMC/SD/SDIO card, that power sequence must
>> be followed while i
From: Peter Rosin
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post "PCM5142/PCM5242 DAC clock
Add sensorhub bindings for sensorhub on Galaxy Gear 2.
Signed-off-by: Karol Wrona
Acked-by: Kyungmin Park
---
.../devicetree/bindings/iio/sensorhub.txt | 25
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/sensorhub.txt
om v4:
- fix Kconfig - missing MFD_CORE dependency
- rebase on next-20150128
- remove THIS_MODULE usage in sensors' drivers as not needed
Thanks,
Karol
Karol Wrona (5):
iio: common: ssp_sensors: Add sensorhub driver
iio: sensorhub: Add sensorhub bindings
iio: common: ssp_sensors: Ad
On 01/28/2015 10:45 AM, Rob Herring wrote:
On Wed, Jan 28, 2015 at 5:05 AM, Catalin Marinas
wrote:
On Tue, Jan 27, 2015 at 06:55:15PM +, Murali Karicheri wrote:
On 01/27/2015 06:27 AM, Robin Murphy wrote:
On 23/01/15 22:32, Murali Karicheri wrote:
Fix the dma-range size when the DT attr
Sensorhub is MCU dedicated to collect data and manage several sensors.
Sensorhub is a spi device which provides a layer for IIO devices. It provides
some data parsing and common mechanism for sensorhub sensors.
Adds common sensorhub library for sensorhub driver and iio drivers
which uses sensorhu
Hi Murali,
[sorry, missed replying to yesterday's version]
On 27/01/15 21:00, Murali Karicheri wrote:
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev->coherent_dma_mask + 1 instead of dev->coherent_dma_mask. Also add
code to check invalid values of size configured
st21nfcb has 3 SWP lines and can support up to 3 secure elements (UICC/eSE and
µSD in the future).
Some st21nfcb firmware does not support the nci command
nci_nfcee_mode_set(NCI_NFCEE_DISABLE).
For this reason, we assume 2 secures elements are always present (UICC and eSE).
They will be added to
On 01/20/2015 10:59 AM, Guenter Roeck wrote:
> On 01/20/2015 03:13 AM, Ezequiel Garcia wrote:
>> Hi Wim,
>>
>> On 01/06/2015 10:19 AM, Ezequiel Garcia wrote:
>>> Here's the seventh round for IMG PDC Watchdog driver.
>>> The series is based on v3.19-rc3.
>>>
>>
>> Guenter has reviewed both patches.
Hello,
I am swimming in a sea of confusion, and am hoping someone would toss
me a life-jacket (of enlightenment). Please forgive me if some of my
questions are poorly asked or appear in seemingly random order.
Working on a Cortex A9 based SoC, I set out to "clean up" the platform
specific timer
On Wednesday 28 January 2015 09:53:25 Suman Tripathi wrote:
>
> I added the iommus in the IOMMU AHBC patch. Anything wrong in that ?
> In the next version Also I will remove the IOMMU hacks from arasan
> driver
Hmm, I guess you have a required ordering between the patches either
way, which makes i
On 28/01/15 17:29, Eduardo Valentin wrote:
Looks like there are still occurencies of adc-dummy after your patch.
But I am amending myself, no need to resend.
Thanks for fixing.. :-)
--srini
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to m
On Wednesday 28 January 2015 12:29:42 Will Deacon wrote:
> On Wed, Jan 28, 2015 at 12:23:03PM +, Laurent Pinchart wrote:
> > On Wednesday 28 January 2015 11:33:00 Will Deacon wrote:
> >> On Mon, Jan 26, 2015 at 06:49:01PM +, Murali Karicheri wrote:
> >>> On 01/25/2015 08:32 AM, Laurent Pinc
Hello.
On 1/25/2015 10:30 PM, Geert Uytterhoeven wrote:
Renesas has made some changes to the Henninger low cost board hardware and at
the same time decided to rename the board to Porter.
Which changes?
I don't have a list ready, sorry. One thing I know is that HDMI chip is
different (
On 2015-01-26 15:18, Stefan Agner wrote:
> On 2015-01-26 14:36, Mark Rutland wrote:
>> On Thu, Jan 15, 2015 at 08:04:05AM +, Stefan Agner wrote:
>>> Add binding documentation for Miscellaneous System Control Module
>>> found in Freescale Vybrid SoC's.
>>>
>>> Signed-off-by: Stefan Agner
>>> --
On Wed, Jan 21, 2015 at 01:28:14PM +0800, Hongzhou Yang wrote:
> From: Hongzhou Yang
>
> Add devicetree bindings for Mediatek SoC pinctrl driver.
>
> Signed-off-by: Hongzhou Yang
This basically follows the pinmux binding I suggested as generic pinmux
binding for per-pin type controllers, so:
Hi Lyra Zhang,
On Wed, Jan 28, 2015 at 04:46:33PM +0800, Lyra Zhang wrote:
> On Wed, Jan 28, 2015 at 2:12 PM, Baruch Siach wrote:
> > On Wed, Jan 28, 2015 at 10:47:41AM +0800, Chunyan Zhang wrote:
> >> + if (uart_handle_sysrq_char(port, ch))
> >> + continue;
> >
>
On 2015-01-27 11:57, Bhuvanchandra DV wrote:
> MCP2515 CAN controller is available on Colibri Evaluation board.
> Hence enable MCP2515 CAN.
>
> Signed-off-by: Bhuvanchandra DV
> ---
> arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 31
> +++
> arch/arm/boot/dts/vf-colibr
On 01/28/15 11:10, Javier Martinez Canillas wrote:
The Snow board has a MMC/SDIO wifi chip that is always powered but it
needs a power sequence involving a reset (active low) and an enable
(active high) pins. Both pins are marked as active low since the MMC
simple power sequence driver asserts th
On Tue, Jan 27, 2015 at 03:19:01PM +0100, Linus Walleij wrote:
> On Wed, Jan 21, 2015 at 6:28 AM, Hongzhou Yang
> wrote:
>
> > From: Hongzhou Yang
> >
> > Add devicetree bindings for Mediatek SoC pinctrl driver.
> >
> > Signed-off-by: Hongzhou Yang
>
> Sascha can you ACK this binding?
Just di
This driver observes the USB ID pin connected over a GPIO and
updates the USB cable extcon states accordingly.
The existing GPIO extcon driver is not suitable for this purpose
as it needs to be taught to understand USB cable states and it
can't handle more than one cable per instance.
For the USB
On Wed, Jan 28, 2015 at 01:15:10PM +, Laurent Pinchart wrote:
> On Wednesday 28 January 2015 12:29:42 Will Deacon wrote:
> > On Wed, Jan 28, 2015 at 12:23:03PM +, Laurent Pinchart wrote:
> > > On Wednesday 28 January 2015 11:33:00 Will Deacon wrote:
> > >> On Mon, Jan 26, 2015 at 06:49:01PM
On Tue, Jan 27, 2015 at 06:55:15PM +, Murali Karicheri wrote:
> On 01/27/2015 06:27 AM, Robin Murphy wrote:
> > On 23/01/15 22:32, Murali Karicheri wrote:
> >> Fix the dma-range size when the DT attribute is missing. i.e set size to
> >> dev->coherent_dma_mask + 1 instead of dev->coherent_dma_m
On 23 January 2015 at 11:56, Gregory CLEMENT
wrote:
> According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
> specific clock adjustments in SDIO3 Configuration register. However,
> this register was not part of the device tree binding. Even if the
> binding can (and will) be extende
On 01/28/2015 06:21 AM, Robin Murphy wrote:
Hi Murali,
[sorry, missed replying to yesterday's version]
On 27/01/15 21:00, Murali Karicheri wrote:
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev->coherent_dma_mask + 1 instead of dev->coherent_dma_mask. Also add
code
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas
---
Changes since v1: None.
---
Documentation/devicetree/bindi
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. For example, is very common for chips to have two
pins: one for reset and one for power enable.
This patch adds support for more reset pins to the pwrseq_simple driver
and instead hardcoding a fixed numbe
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
On 20/01/15 16:02, Stefan Agner wrote:
> The ADC clock frequency is limited depending on modes used. Add
> device tree property which allow to set the mode used and the
> maximum frequency ratings for the instance. These allows to
> set the ADC clock to a frequency which is within specification
> a
Hello Ulf,
Many WLAN chips attached to an SDIO interface needs more than one GPIO
for their reset sequence and also need an external clock to be operational.
Since this is very common, this series extend the simple MMC power sequence
to support more than one reset GPIO and also an optional extern
On 01/28/2015 03:57 PM, Guenter Roeck wrote:
> On Wed, Jan 28, 2015 at 03:39:22PM -0300, Ezequiel Garcia wrote:
>> On 01/20/2015 10:59 AM, Guenter Roeck wrote:
>>> On 01/20/2015 03:13 AM, Ezequiel Garcia wrote:
Hi Wim,
On 01/06/2015 10:19 AM, Ezequiel Garcia wrote:
> Here's the
At Wed, 28 Jan 2015 15:16:06 +0100,
Peter Rosin wrote:
>
> From: Peter Rosin
>
> Add helper functions to allow drivers to specify several disjoint
> ranges for a variable. In particular, there is a codec (PCM512x) that
> has a hole in its supported range of rates, due to PLL and divider
> restri
Enabling SDIO IRQ signalling for the wifi MMC/SDIO slot
doubles the transmission transfer rate.
Signed-off-by: Javier Martinez Canillas
---
Changes since v1: None, new patch.
---
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos52
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 6 +++---
1 file changed, 3 insertions(+),
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. For example, is very common for chips to have two
pins: one for reset and one for power enable.
This patch adds support for more reset pins to the pwrseq_simple driver
and instead hardcoding a fixed numbe
Some WLAN chips attached to a SDIO interface, need a reference clock.
Since this is very common, extend the prseq_simple driver to support
an optional clock that is enabled prior the card power up procedure.
Note, the external clock is optional. Thus an error is not returned
if the clock is not f
On 23 January 2015 at 17:46, Gregory CLEMENT
wrote:
> From: Marcin Wojtas
>
> According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
> specific clock adjustments in SDIO3 Configuration register.
>
> This commit add the support of this register and for SDR50 or DDR50
> mode use it as
On 28/01/15 13:35, Ulf Hansson wrote:
On 28 January 2015 at 14:16, Srinivas Kandagatla
wrote:
This patchset adds support to reset/powerup multiple gpio pins on a given
sdio bus. The use case is simple, on sdio we could have multiple devices
like WLAN, BT which are controlled by there own reset
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas
---
Changes since v1:
- Make the explanation clearer by adding an explicit "they".
Suggested by Srinivas
On 01/28/2015 01:20 PM, Murali Karicheri wrote:
On 01/28/2015 12:43 PM, Murali Karicheri wrote:
On 01/28/2015 11:49 AM, Murali Karicheri wrote:
On 01/27/2015 05:28 PM, Arnd Bergmann wrote:
On Tuesday 20 January 2015 10:53:36 Murali Karicheri wrote:
On 01/19/2015 03:11 PM, David Miller wrote:
The same 24MHz counter is also present on Versatile AB and PB boards, so
add the compatible string for them.
Signed-off-by: Rob Herring
Cc: Liviu Dudau
Cc: Sudeep Holla
Cc: Lorenzo Pieralisi
Cc: Daniel Lezcano
Cc: Thomas Gleixner
---
drivers/clocksource/versatile.c | 4 +++-
1 file changed,
Some WLAN chips attached to a SDIO interface, need a reference clock.
Since this is very common, extend the prseq_simple driver to support
an optional clock that is enabled prior the card power up procedure.
Note: the external clock is optional. Thus an error is not returned
if the clock is not f
The Snow board has a MMC/SDIO wifi chip that is always powered but it
needs a power sequence involving a reset (active low) and an enable
(active high) pins. Both pins are marked as active low since the MMC
simple power sequence driver asserts the pins prior to the card power
up procedure and de-as
The Snow board has a MMC/SDIO wifi chip that is always powered but it
needs a power sequence involving a reset (active low) and an enable
(active high) pins. Both pins are marked as active low since the MMC
simple power sequence driver asserts the pins prior to the card power
up procedure and de-as
Hello Ulf,
Many WLAN chips attached to an SDIO interface needs more than one GPIO
for their reset sequence and also an external clock to be operational.
Since this is very common, this series extend the simple MMC power sequence
to support more than one reset GPIO and also an optional external cl
On Wed, Jan 28, 2015 at 12:23:03PM +, Laurent Pinchart wrote:
> On Wednesday 28 January 2015 11:33:00 Will Deacon wrote:
> > On Mon, Jan 26, 2015 at 06:49:01PM +, Murali Karicheri wrote:
> > > On 01/25/2015 08:32 AM, Laurent Pinchart wrote:
> > >> On Friday 23 January 2015 17:32:34 Murali K
Hi Mark,
First of all, thanks for taking the rest of the series!
Mark Brown wrote:
> On Wed, Jan 28, 2015 at 03:16:08PM +0100, Peter Rosin wrote:
>
> > @@ -78,7 +78,7 @@ static const struct reg_default
> pcm512x_reg_defaults[] = {
> > { PCM512x_DIGITAL_VOLUME_2, 0x30 },
> > { PCM512x_DI
Chanwoo,
On 28/01/15 04:19, Chanwoo Choi wrote:
> Hi Roger,
>
> On 01/28/2015 12:38 AM, Roger Quadros wrote:
>> Chanwoo,
>>
>> On 27/01/15 03:54, Chanwoo Choi wrote:
>>> Hi Roger,
>>>
>>> On 01/27/2015 01:27 AM, Roger Quadros wrote:
Hi Chanwoo,
All your comments are valid. Need som
The Versatile clocksource driver can also be used on Versatile AB and PB
platforms, not just Versatile Express. This series adds support for
those boards.
I've split this off from the rest of the Versatile DT and
multi-platform support as I'm not going to get it in place for 3.20.
This part is
Hi Andy,
On 01/28/2015 12:10 AM, Andy Gross wrote:
> This patch adds automatic configuration for the ADM CRCI muxing required to
> support DMA operations for GSBI clients. The GSBI mode and instance determine
> the correct TCSR ADM CRCI MUX value that must be programmed so that the DMA
> works pr
The Versatile boards have the same sysregs as other ARM Ltd boards. Add
the nodes in order to enable support for 24MHz counter as sched_clock.
This is a minimal node definition as the existing sub node definition
used on VExpress has some issues raised by Linus W.
Signed-off-by: Rob Herring
Cc:
Hello Ulf,
On Mon, Jan 19, 2015 at 10:13 AM, Ulf Hansson wrote:
> To support SOCs which specifies specific MMC power sequences, document
> some MMC DT bindings to be able to describe these hardwares.
>
> Let's also document bindings for a simple MMC power sequence provider,
> which purpose is to
On 01/27/2015 01:38 AM, Andreas Färber wrote:
> Am 26.01.2015 um 20:49 schrieb Soren Brinkmann:
>> In one pinctrl node, a 'bias-disable' property is erroneously assigned a
>> value.
>>
>> Fixes: ARM: zynq: DT: Add pinctrl information
>> Signed-off-by: Soren Brinkmann
>
> Reviewed-by: Andreas Färb
Hi Pavel,
On 01/27/2015 11:37 PM, Pavel Machek wrote:
Hi!
+ - flash_fault - list of flash faults that may have occurred:
+ * led-over-voltage - flash controller voltage to the flash LED
+ has exceededthe limit specific to the flash controller
+
On 2015-01-27 11:57, Bhuvanchandra DV wrote:
> Acked-by: Stefan Agner
> Signed-off-by: Bhuvanchandra DV
> ---
> arch/arm/boot/dts/vf500.dtsi | 4
> arch/arm/boot/dts/vfxxx.dtsi | 11 +++
> 2 files changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/b
On 28/01/15 11:05, Catalin Marinas wrote:
On Tue, Jan 27, 2015 at 06:55:15PM +, Murali Karicheri wrote:
On 01/27/2015 06:27 AM, Robin Murphy wrote:
On 23/01/15 22:32, Murali Karicheri wrote:
Fix the dma-range size when the DT attribute is missing. i.e set size to
dev->coherent_dma_mask + 1
Hi Marc,
> -Original Message-
> From: Marc Kleine-Budde [mailto:m...@pengutronix.de]
> Sent: Wednesday, January 28, 2015 8:16 PM
> To: Appana Durga Kedareswara Rao; w...@grandegger.com; Michal Simek;
> Soren Brinkmann; grant.lik...@linaro.org; robh...@kernel.org
> Cc: linux-...@vger.kernel
Hi,
On 28-01-15 11:02, Hans de Goede wrote:
Hi,
On 04-01-15 21:06, Michal Suchanek wrote:
Signed-off-by: Michal Suchanek
Thanks, I've merged this with a number of changes:
- Cleaned it up a bit
- Ported it to our new simplified dram config code in u-boot-sunxi/next
- Added OTG (host mode)
Hi Javier,
You are in a lead of 3 hrs from me..
Surprisingly I send very much same patch just few Mins ago :-)
May be we can merge goods in both :-)
On 28/01/15 10:10, Javier Martinez Canillas wrote:
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. F
Add binding for Versatile board system registers found in the FPGA of the
Versatile/AB and Versatile/PB boards.
Signed-off-by: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: devicetree@vger.kernel.org
---
Documentation/devicetree/bindings/arm/versatile-sysreg
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