On Tuesday 10 March 2015 10:10:54 Feng Kan wrote:
+
+ soc {
+ compatible = simple-bus;
+ #address-cells = 2;
+ #size-cells = 2;
+ ranges;
+
+ serial0: serial@1060 {
+ device_type =
On Tue, Mar 10, 2015 at 6:57 PM, Florian Fainelli f.faine...@gmail.com wrote:
Export of_mdio_parse_addr() which allows parsing a given Ethernet PHY
node MDIO address, verify it is within the allowed range, and return
its value. This is going to be useful for the DSA code which needs to
deal
Am Dienstag, den 10.03.2015, 22:20 +0100 schrieb Maxime Coquelin:
2015-03-10 21:21 GMT+01:00 Arnd Bergmann a...@arndb.de:
On Tuesday 10 March 2015 16:44:24 Maxime Coquelin wrote:
2015-03-10 16:02 GMT+01:00 Arnd Bergmann a...@arndb.de:
On Friday 20 February 2015 19:01:06 Maxime Coquelin
On Tuesday 10 March 2015 16:44:24 Maxime Coquelin wrote:
2015-03-10 16:02 GMT+01:00 Arnd Bergmann a...@arndb.de:
On Friday 20 February 2015 19:01:06 Maxime Coquelin wrote:
+/* AHB1 */
+#define GPIOA_RESET0
+#define GPIOB_RESET1
+#define GPIOC_RESET2
+#define GPIOD_RESET
On Wed, Mar 11, 2015 at 3:21 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
On Wed, Mar 11, 2015 at 2:17 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 11 March 2015 14:07:11 Javier Martinez Canillas wrote:
Right now it seems that all boards in mainline with a WiLink6 part are
This patch adds the support for APM Merlin board. The Merlin board
is based on the APM X-Gene Shadowcat SoC. This DTS enables PMU,
SATA and Serial.
Signed-off-by: Feng Kan f...@apm.com
---
V1 Change:
- add memreserve for spintable.
- remove clkfreq attribute
- update
On 03/09/2015 03:02 PM, Andy Shevchenko wrote:
On Mon, Mar 9, 2015 at 9:47 PM, Thor Thayer
ttha...@opensource.altera.com wrote:
On 03/09/2015 01:54 PM, Andy Shevchenko wrote:
Yes, I just need the 32 bit write. I was trying to remain consistent but I
agree that only changing only writes
On Tue, Mar 10, 2015 at 10:20 AM, Mark Rutland mark.rutl...@arm.com wrote:
Hi,
On Tue, Mar 10, 2015 at 05:10:54PM +, Feng Kan wrote:
This patch adds the support for APM Merlin board. The Merlin board
is based on the APM X-Gene Shadowcat SoC. This DTS enables PMU,
SATA and Serial.
Hi,
On Sat, Mar 7, 2015 at 11:53 AM, Sebastian Reichel s...@kernel.org wrote:
Please CC linux-pm.
Will do.
I would prefer to have a generic driver like syscon-reboot does for
system reset.
Will look into it,
-- Moritz
--
To unsubscribe from this list: send the line unsubscribe devicetree
* Nishanth Menon n...@ti.com [150310 10:25]:
On 03/10/2015 10:33 AM, Tony Lindgren wrote:
* Linus Walleij linus.wall...@linaro.org [150310 03:39]:
On Wed, Mar 4, 2015 at 1:00 AM, Nishanth Menon n...@ti.com wrote:
+Configuration definition follows similar model as the pinctrl-single:
Hi Dave,
On 03/06/2015 07:45 PM, Tony Lindgren wrote:
* Dave Gerlach d-gerl...@ti.com [150306 09:28]:
On 03/05/2015 06:41 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150305 12:24]:
* Dave Gerlach d-gerl...@ti.com [150305 11:53]:
On 03/05/2015 12:49 PM, Tony Lindgren wrote:
*
Hi Linus,
On 3/10/2015 3:20 AM, Linus Walleij wrote:
On Mon, Mar 9, 2015 at 9:45 PM, Ray Jui r...@broadcom.com wrote:
This adds the initial support of the Broadcom Cygnus GPIO/PINCONF driver
that supports all 3 GPIO controllers on Cygnus including the ASIU GPIO
controller, the chipCommonG
Grygorii,
On 03/10/2015 12:36 PM, Grygorii Strashko wrote:
Hi Dave,
On 03/06/2015 07:45 PM, Tony Lindgren wrote:
* Dave Gerlach d-gerl...@ti.com [150306 09:28]:
On 03/05/2015 06:41 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150305 12:24]:
* Dave Gerlach d-gerl...@ti.com
On Tue, Mar 10, 2015 at 07:59:24PM +0800, Chen-Yu Tsai wrote:
The Hummingbird A31 has an AMPAK AP6210 WiFi+Bluetooth module. The
WiFi part is a BCM43362 IC connected to MMC1 in the A31 SoC via SDIO.
The IC also takes a power enable signal via GPIO. This is supported
with the new power
On Tue, Mar 10, 2015 at 07:59:22PM +0800, Chen-Yu Tsai wrote:
mmc1 is used to connect to the WiFi chip on the Hummingbird A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 8
1 file changed, 8 insertions(+)
diff --git
On Tue, Mar 10, 2015 at 07:59:21PM +0800, Chen-Yu Tsai wrote:
This patch adds the AXP221 regulators. Only the ones directly used
on the board are added.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android
On 03/11/2015 06:08 AM, Geert Uytterhoeven wrote:
TL;DR
After removing the console= parameter from chosen/bootargs, and relying
solely on chosen/stdout-path, Hiep-san's Linaro userland cannot find the
console device anymore.
On Wed, Mar 11, 2015 at 7:45 AM, Laurent Pinchart
Just a few nits, I'm afraid.
On Wed, 2015-03-11 at 14:18 +0800, CK Hu wrote:
drivers/gpu/drm/bridge/Kconfig | 10 +
drivers/gpu/drm/bridge/Makefile | 1 +
I applied 1/2 and 2/2 on top of next-20150312 to check a trivial issue.
The chunks for these two files needed context changes to git
Hi Paul,
Yes, I didn't notice that. I'll include it in the next patch. Thanks for
the review.
Jon
On 15-03-11 02:46 AM, Paul Bolle wrote:
One nit is all I can report.
On Tue, 2015-03-10 at 18:17 -0700, Jonathan Richardson wrote:
--- a/drivers/input/touchscreen/Kconfig
+++
Hi Suman,
On Thu, Mar 5, 2015 at 4:01 AM, Suman Anna s-a...@ti.com wrote:
This is the latest version of the hwspinlock dt support series,
rebased onto v4.0-rc1 and addressing the long discussion on the
bindings in v7 [1]. I really hope that this series can make it
into 4.1.
From a quick
[adding RobH to the CC list, as he was commenting on the subject earlier]
Hi Pranav,
On 12/03/15 03:52, Pranavkumar Sawargaonkar wrote:
Hi Marc,
On Wed, Mar 11, 2015 at 11:47 PM, Marc Zyngier marc.zyng...@arm.com wrote:
On 11/03/15 17:57, Feng Kan wrote:
On Wed, Mar 11, 2015 at 10:31 AM,
Hi,
On Wed, Mar 11, 2015 at 10:43:17AM -0700, Tony Lindgren wrote:
No no, capacity-uah is what we should use, but you need an ack from
the battery and device tree people that this is OK. Let's not add
ti,capacity-uah” as that can obviously be a generic property.
I'm okay with capacity-uah.
On 2015-03-11 01:48, Shawn Guo wrote:
On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to get information of the individual and current (accessing)
CPU. In
On 11 March 2015 at 05:43, Mike Turquette mturque...@linaro.org wrote:
Sorry, I am not who you asked for advice but I will chime in anyways ;-)
Always welcome :)
I really hate this intermediate frequency stuff in cpufreq. As we
I am starting to :)
Furthermore any intermediate-frequency
Hi Mark, Rob,
On Sat, Feb 28, 2015 at 12:30 AM, Bjorn Andersson
bjorn.anders...@sonymobile.com wrote:
Add binding documentation for the Qualcomm Hardware Mutex.
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
I think the conclusion on the dt binding discussion for
Hi Dave,
On 03/10/2015 07:59 PM, Dave Gerlach wrote:
On 03/10/2015 12:36 PM, Grygorii Strashko wrote:
On 03/06/2015 07:45 PM, Tony Lindgren wrote:
* Dave Gerlach d-gerl...@ti.com [150306 09:28]:
On 03/05/2015 06:41 PM, Tony Lindgren wrote:
* Tony Lindgren t...@atomide.com [150305 12:24]:
*
Hi,
As part of the system timer cleanup, I'll actually be needing that
patch. Is it scheduled for inclusion or should I use simple-bus in the
meantime?
On 03/03/2015 at 10:32:24 +0100, Linus Walleij wrote :
This defines a new compatible option for MFD devices simple-mfd that will
make the OF
On 11 March 2015 at 18:15, Mark Brown broo...@kernel.org wrote:
Ugh, no - that's a hideous bodge which is only going to create trouble
later. Remember, DT is an ABI and should describe the hardware so if
we're doing bodges that are visible there to shoehorn things onto our
implementation
Update the Image placement logic used by the stub to make absolutely
sure that the Image is placed such that the early init code will
always be able to map it. This means the entire static memory footprint
of the Image should be inside the same naturally aligned 512 MB region.
First of all, the
This splits off the reservation of the memory occupied by the FDT
binary itself from the processing of the memory reservations it
contains. This is necessary because the physical address of the FDT,
which is needed to perform the reservation, may not be known to the
FDT driver core, i.e., it may
Hi,
* Marek Belisko ma...@goldelico.com [150310 14:28]:
Signed-off-by: Marek Belisko ma...@goldelico.com
---
.../bindings/power_supply/twl4030_madc_battery.txt | 43
++
1 file changed, 43 insertions(+)
create mode 100644
With the relaxed FDT placement requirements in place, we can change
the allocation strategy used by the stub to put the FDT image higher
up in memory. At the same time, reduce the minimal alignment to a
power of 2 upper bound of the size: this way, we are still guaranteed
not to cross a 2 MB
On 11 March 2015 at 05:29, Mike Turquette mturque...@linaro.org wrote:
I assume you are saying that you want to update loops-per-jiffie while
at an intermediate frequency. Why? This operation should not take very
long.
Imagine a (hypothetical?) processor that changes frequency in many small
On Thu, Mar 12, 2015 at 11:36 AM, Rafał Miłecki zaj...@gmail.com wrote:
On 12 March 2015 at 11:19, Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Wed, Mar 11, 2015 at 10:57 PM, Brian Norris
computersforpe...@gmail.com wrote:
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt
On Wed 04 Mar 18:01 PST 2015, Suman Anna wrote:
This patch adds a new OF-friendly API of_hwspin_lock_get_id()
for hwspinlock clients to use/request locks from a hwspinlock
device instantiated through a device-tree blob. This new API
can be used by hwspinlock clients to get the id for a
On Thu, Mar 12, 2015 at 5:28 PM, Viresh Kumar viresh.ku...@linaro.org wrote:
On 11 March 2015 at 18:15, Mark Brown broo...@kernel.org wrote:
Ugh, no - that's a hideous bodge which is only going to create trouble
later. Remember, DT is an ABI and should describe the hardware so if
we're doing
This patch set implements the APM X-Gene SoC DMA driver support to offload
the DMA operations such as memory copy(memcpy), scatter gather memory copy,
raid5 xor and raid6 p+q.
v7 changes:
1. Added raid5 xor offload support.
2. Added raid6 p+q offload support.
v6 changes:
2015-03-11 7:18 GMT+01:00 CK Hu ck...@mediatek.com:
Add devicetree bindings for IT6151 MIPI to eDP bridge chip driver.
Signed-off-by: CK Hu ck...@mediatek.com
Signed-off-by: Jitao Shi jitao@mediatek.com
Please use scripts/get_maintainer.pl for all people to which send the
next version of
On 12 March 2015 at 11:19, Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Wed, Mar 11, 2015 at 10:57 PM, Brian Norris
computersforpe...@gmail.com wrote:
diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt
b/Documentation/devicetree/bindings/mtd/m25p80.txt
index
[...]
Do CPUs enter the kernel at EL2 or at EL1?
Could you give me a tip how to check the kernel at EL2 or EL1?
Hmm... I thought we logged this but it looks like we don't.
You could hack in a check of is_hyp_mode_available() and
is_hyp_mode_mismatched(). That will tell you if
This patch implements the APM X-Gene SoC DMA engine driver. The APM X-Gene
SoC DMA engine consists of 4 DMA channels for performing DMA operations.
These DMA operations include memory copy, scatter-gather memory copy,
raid5 xor, and raid6 p+q offloading.
Signed-off-by: Rameshwar Prasad Sahu
This patch adds device tree binding for APM X-Gene SoC DMA engine driver.
Signed-off-by: Rameshwar Prasad Sahu rs...@apm.com
Signed-off-by: Loc Ho l...@apm.com
---
.../devicetree/bindings/dma/apm-xgene-dma.txt | 47 ++
1 file changed, 47 insertions(+)
create mode 100644
This patch adds the device tree node for APM X-Gene SoC
DMA controller and DMA clock.
Signed-off-by: Rameshwar Prasad Sahu rs...@apm.com
Signed-off-by: Loc Ho l...@apm.com
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git
On 03/11/2015 07:16 PM, Stephen Boyd wrote:
On 03/09/15 08:16, Lina Iyer wrote:
Register cpuidle ops for Krait Processor Sub-System.
Supports v1 and v2 versions of KPSS.
Cc: Stephen Boyd sb...@codeaurora.org
Cc: Arnd Bergmann a...@arndb.de
Cc: Kevin Hilman khil...@linaro.org
Cc: Daniel Lezcano
Hi,
On 12-03-15 13:23, Vince Hsu wrote:
Cc'd Hans.
Thanks,
Vince
On 03/12/2015 08:19 PM, Tejun Heo wrote:
On Thu, Mar 12, 2015 at 08:15:15PM +0800, Vince Hsu wrote:
We have the generic PM domain support for Tegra SoCs now. So remove the
duplicated sequence here.
Signed-off-by: Vince Hsu
On Thu, Mar 12, 2015 at 08:15:18PM +0800, Vince Hsu wrote:
We switch to generic power domain now. So remove the legacy functions.
Signed-off-by: Vince Hsu vin...@nvidia.com
---
drivers/soc/tegra/pmc.c | 68
-
include/soc/tegra/pmc.h | 22
Hello,
I have spun one more version to address feedback from Paul Bolle and to include
the .dtsi with the timings for the Nyan Blaze in the right DTS.
Because of the DT changes for the Nyan boards this now depends on the Nyan
series, but all the rest should apply cleanly on top of v4.0-rc1.
From: Mikko Perttunen mperttu...@nvidia.com
This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main Jetson TK1 device tree.
The data is generated from the V5.0.17 version of the DVFS tables.
Signed-off-by: Mikko
Hi,
On 03/12/2015 08:45 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Mar 12, 2015 at 08:15:18PM +0800, Vince Hsu wrote:
We switch to generic power domain now. So remove the legacy functions.
Signed-off-by: Vince Hsu vin...@nvidia.com
---
drivers/soc/tegra/pmc.c | 68
This adds a new file, tegra124-nyan-big-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Big.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the
This adds a new file, tegra124-nyan-blaze-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main device tree file for the Nyan Blaze.
The frequency 528MHz is missing because we don't currently have a timing
configuration that works.
Additionally, only the
From: Frank Rowand frank.row...@sonymobile.com
Fix an of_unittest.c include path to account for the move of
unittest.c into unittest-data/.
Signed-off-by: Frank Rowand frank.row...@sonymobile.com
---
drivers/of/unittest-data/unittest.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
MIC(Mobile image compressor) is newly added IP in Exynos5433. MIC
resides between decon and mipi dsim, and compresses frame data by 50%.
With dsi, not display port, to send frame data to the panel, the
bandwidth is not enough. That is why this compressor is introduced.
Signed-off-by: Hyungwon
Gentlemen,
I think this has soaked for long enough now. Hopefully there are no issues.
The following changes since commit c517d838eb7d07bbe9507871fab3931deccff539:
Linux 4.0-rc1 (2015-02-22 18:21:14 -0800)
are available in the git repository at:
Since Exynos5420 there are async-bridges (ASB) between different IPs. These
bridges must be operational during power domain on/off, ie. clocks used
by these bridges should be enabled.
This patch enabled these clocks during domain on/off.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Dear Tomasz,
Thanks very much for review so detail!
Please check my reply below. Others I will fix it in the next
version.
And I have got your comment of [2/5]. Do you have plan for the
other patch?
On Sun, 2015-03-08 at 13:12 +0900, Tomasz Figa wrote:
Hi Yong Wu,
MIC must be initilized by MIPI DSI when it is being bound.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
When there are multiple ports or multiple endpoints in a port, they have to be
distinguished by the value of reg property. It is common. The drivers can get
the specific endpoint in the specific port via this function. Now the drivers
have to implement this code in themselves or have to force the
From: Joonyoung Shim jy0922.s...@samsung.com
DECON(Display and Enhancement Controller) is new IP replacing FIMD in
Exynos5433. This patch adds Exynos5433 decon driver.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
From: Frank Rowand frank.row...@sonymobile.com
Move of_unittest.c into unittest-data/
This is based on v4.0-rc3.
All checkpatch errors are ignored, as this is just a file move. At least
two of the checkpatch errors appear to be real bugs, to be addressed in
a future patch.
Signed-off-by:
Hi Kukjin,
This is resend of my patchset with added (Reviewed|Tested)-by tags and removed
RFC
prefix.
Exynos chipsets since 542x have asynchronous bridges connecting different IPs.
These bridges should be operational during power domain switching, ie associated
clocks cannot be gated.
This
The patch adds bindings for clocks required by async-bridges
present in the particular power domain.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Catalin, Rob,
do you agree with this patchset ?
Thanks
-- Daniel
On 03/03/2015 01:29 PM, Daniel Lezcano wrote:
There is a big number of cpuidle drivers for the ARM architecture.
These drivers have been cleaned up and grouped into the drivers/cpuidle
directory to keep track of the changes
On some board, TE GPIO should be configured properly thoughout pinctrl driver
as an wakeup interrupt. So this gpio should be configurable in the board's DT,
not being requested as a input pin.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 4
This patchset is based on the git(branch name: exynos-drm-next) which is
maintained by Inki Dae.
https://kernel.googlesource.com/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
This patchset adds 2 new device drivers, decon and mic, and adds support for
Exynos5433 mipi dsi. To enable display in a
From: Frank Rowand frank.row...@sonymobile.com
This 3 patch series is not bisectable. If CONFIG_OF_UNITTEST=y then the kernel
will not build with just patch 1 or just patches 1 and 2 applied.
If CONFIG_OF_UNITTEST=y then a kernel image make will always cause .version to
be incremented, even if
Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Javier Martinez
FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Javier Martinez Canillas
From: Donghwa Lee dh09@samsung.com
This patch adds support for Exynos5433. The goal is achieved by
1. Getting the address of registers from driver data
2. Getting the fixed value for registers from driver data
3. Getting different number of clocks using driver data
4. Getting max frequency of
Hi Philipp,
On 03/12/2015 11:01 PM, Philipp Zabel wrote:
Hi Vince,
Am Donnerstag, den 12.03.2015, 20:15 +0800 schrieb Vince Hsu:
Add of_reset_control_get_by_index() to allow the drivers to get reset device
without knowing its name.
I see this is useful in the case of PM domain drivers that
On Thu, Mar 12, 2015 at 10:03:08AM +0100, Stefan Agner wrote:
On 2015-03-11 01:48, Shawn Guo wrote:
On Sun, Mar 01, 2015 at 11:41:29PM +0100, Stefan Agner wrote:
Add the Miscellaneous System Control Module (MSCM) to the base
device tree for Vybrid SoC's. This module contains registers
to
Stephen Warren was concerned that the rmb() present in the new mailbox
driver was unnecessary, and after seeing the docs, that it was just so
surprising that somebody would come along and remove it later. The
explanation for the need for the rmb() is long enough that we won't
want to place it at
From: Lubomir Rintel lkund...@v3.sk
Implement BCM2835 mailbox support as a device registered with the
general purpose mailbox framework. Implementation based on commits by
Lubomir Rintel [1], Suman Anna and Jassi Brar [2] on which to base the
implementation.
[1]
From: Lubomir Rintel lkund...@v3.sk
Signed-off-by: Lubomir Rintel lkund...@v3.sk
Signed-off-by: Craig McGeachie slap...@yahoo.com.au
Signed-off-by: Eric Anholt e...@anholt.net
---
v2: Split into a separate patch for submitting to the devicetree list.
Consistently start node docs with a
Signed-off-by: Eric Anholt e...@anholt.net
Acked-by: Lee Jones lee.jo...@linaro.org
---
arch/arm/boot/dts/bcm2835.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
index 3342cb1..6b5c3a1 100644
---
On Wed, Mar 11, 2015 at 09:46:09AM +0800, Shawn Guo wrote:
On Mon, Mar 09, 2015 at 05:28:06PM +0800, Peter Chen wrote:
max7310 is an i2c interface gpio expander
Signed-off-by: Peter Chen peter.c...@freescale.com
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 43
On Fri, Mar 13, 2015 at 10:40:43AM +0800, Peter Chen wrote:
On Wed, Mar 11, 2015 at 09:46:09AM +0800, Shawn Guo wrote:
On Mon, Mar 09, 2015 at 05:28:06PM +0800, Peter Chen wrote:
max7310 is an i2c interface gpio expander
Signed-off-by: Peter Chen peter.c...@freescale.com
---
On 11 March 2015 at 09:41, Viet Nga Dao vn...@altera.com wrote:
On Tue, Mar 10, 2015 at 4:09 PM, Viet Nga Dao vn...@altera.com wrote:
Ok. I will modify the code the way you suggest.
I just realize that the opcode for RDID is handled by hardware in my
case, therefore i dont really need to
Hi,
Could anyone please help me review the lock, unlock modification part
i did in spi-nor?
Thanks,
Viet Nga
On Mon, Feb 23, 2015 at 9:30 AM, Viet Nga Dao vn...@altera.com wrote:
Hi,
It has been nearly 2 weeks since i submitted this patch. Could you
please help to review?
Thanks,
On Tue,
Hi Sakari,
Thanks for the review.
On Fri, Mar 13, 2015 at 12:04 AM, Sakari Ailus sakari.ai...@iki.fi wrote:
Hi Prabhakar,
On Thu, Mar 12, 2015 at 11:22:36PM +, Lad Prabhakar wrote:
...
+static int ov2659_probe(struct i2c_client *client,
+ const struct i2c_device_id
On Tue, Mar 10, 2015 at 09:47:44AM -0400, Peter Hurley wrote:
Hi David,
On 03/09/2015 08:17 PM, David Gibson wrote:
On Fri, Mar 06, 2015 at 10:12:38AM -0500, Peter Hurley wrote:
Properties may contain path names which are not NUL-terminated.
For example, the 'stdout-path' property allows
On Tue, Mar 10, 2015 at 09:47:44AM -0400, Peter Hurley wrote:
Hi David,
On 03/09/2015 08:17 PM, David Gibson wrote:
On Fri, Mar 06, 2015 at 10:12:38AM -0500, Peter Hurley wrote:
Properties may contain path names which are not NUL-terminated.
For example, the 'stdout-path' property allows
Hi Laurent,
Thanks for the patch.
On Fri, Mar 13, 2015 at 12:03 AM, Laurent Pinchart
laurent.pinch...@ideasonboard.com wrote:
Parse DT properties into a platform data structure when a DT node is
available.
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
[snip]
On 03/11/2015 12:40 PM, Murali Karicheri wrote:
On some platforms such as that based on x86, ia64 etc, root bus is
created with parent node passed in as NULL to pci_create_root_bus().
On these platforms, the patch series PCI: get DMA configuration from
parent device when applied causes kernel
This commit introduces two new optional device-tree properties:
tp-sensitive-adjust: adjust sensitivity of pen down detection
filter-type: select median and averaging filter
The previous fixed defaults, didn't work well for the Olimex
A13-LCD10TS (I have).
Signed-off-by: Jens Thiele
The MC driver needs some timing-specific information to program the EMEM during
a rate change of the EMC clock.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
v4: * Add more information about nvidia,emem-configuration
* Remove mandatory naming of the timings subnode
This patch adds helper functions for registering/unregistering
LED Flash class devices as V4L2 sub-devices. The functions should
be called from the LED subsystem device driver. In case the
support for V4L2 Flash sub-devices is disabled in the kernel
config the functions' empty versions will be
This series tries to fix the issue reported here[1]. In short: A DT entry wants
a fixed id but its probe was deferred. When it was probed again, its id was
taken by a dynamically assigned muxed bus. So, the probe failed.
Let's start all dynamically assigned ids after the highest fixed one. We do
Hi James,
On Wed, Mar 11, 2015 at 7:06 PM, James Hartley james.hart...@imgtec.com wrote:
This adds the binding documentation for the Imagination Technologies hash
accelerator that provides hardware acceleration for SHA1/SHA224/SHA256/MD5
hashes. This hardware will be present in the upcoming
This patch adds a description of 'flashes' property
to the samsung-fimc.txt.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Sylwester Nawrocki s.nawro...@samsung.com
---
.../devicetree/bindings/media/samsung-fimc.txt |8
This patch adds device tree binding documentation for
1.5A Step-Up Current Regulator for Flash LEDs.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Bryan Wu coolo...@gmail.com
Cc: Richard Purdie rpur...@rpsys.net
---
From: Courtney Cavin courtney.ca...@sonymobile.com
This adds device tree binding documentation for the WLED ('White' LED)
block on Qualcomm's PM8941 PMICs.
Signed-off-by: Courtney Cavin courtney.ca...@sonymobile.com
Signed-off-by: Bjorn Andersson bjorn.anders...@sonymobile.com
---
Changes since
Add support for V4L2 Flash sub-device to the max77693 LED Flash class
driver. The support allows for V4L2 Flash sub-device to take the control
of the LED Flash class device.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Bryan Wu
This patch set is a follow-up of the LED / flash API integration
series [1]. It is based on linux-next_20150312, with patches
for mfd max77693 from the previous version of the patch set.
Those patches have been recently applied to mfd tree and are
awaiting merging with linux-next.
LED_FLASH_MAX_SYSFS_GROUPS macro had value that was relevant for
previous version of the patches introducing LED Flash class. Currently
it is required to reserve the room for maximum 4 sysfs groups.
Since the last element of the struct attribute_group array passed to
the function
This patch adds a driver for the 1.5A Step-Up Current Regulator
for Flash LEDs. The device is programmed through a Skyworks proprietary
AS2Cwire serial digital interface.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Bryan Wu
Add support for V4L2 Flash sub-device to the aat1290 LED Flash class
driver. The support allows for V4L2 Flash sub-device to take the control
of the LED Flash class device.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Cc: Bryan Wu
From: Mikko Perttunen mperttu...@nvidia.com
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
v7: * Remove nvidia,emc-cfg-dig-dll as it's unused
*
On Thu, Mar 12 2015 at 06:34 -0600, Daniel Lezcano wrote:
On 03/11/2015 07:16 PM, Stephen Boyd wrote:
On 03/09/15 08:16, Lina Iyer wrote:
[...]
+#if IS_ENABLED(CONFIG_QCOM_PM)
Why not #ifdef CONFIG_QCOM_PM? I thought IS_ENABLED was for C code where
you want to put it in an if ()
The EMC clock needs some extra information for changing its rate.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
v5: * Remove constraint on the unit-address of the timings and timing
subnodes
v4: * Remove comma from unit-address of CAR node in the example
*
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