From: Igal Liberman igal.liber...@freescale.com
Describe the PHY topology for all configurations supported by each board
Based on prior work by Andy Fleming aflem...@gmail.com
Signed-off-by: Igal Liberman igal.liber...@freescale.com
Signed-off-by: Shruti Kanetkar kanetkar.shr...@gmail.com
This patch adds dts support for NAND flash controller of Hisilicon Soc Hip04.
Now it is based on v4.0-rc5
Changes in v3:
- Change E-mail address in signed-off-by to wangzh...@hisilicon.com
Changes in v2:
- Base on v3.19-rc1
- Use nand-ecc-strength, nand-ecc-step-size to replace hisi,nand-ecc-bits
On 03/24/2015 07:51 PM, Lorenzo Pieralisi wrote:
On Tue, Mar 24, 2015 at 09:54:02AM +, Daniel Lezcano wrote:
Add kernel-doc format documentation in the code.
Signed-off-by: Daniel Lezcano daniel.lezc...@linaro.org
---
[ ... ]
+ * Returns:
+ * 0 on success,
+ * -ENODEV if it fails to
On Fri, 20 Mar 2015 08:32:12 -0500
, Rob Herring robherri...@gmail.com
wrote:
On Fri, Mar 20, 2015 at 7:25 AM, Grant Likely grant.lik...@linaro.org wrote:
On Fri, 23 Jan 2015 17:10:04 +0100
, Geert Uytterhoeven geert+rene...@glider.be
wrote:
Currently OF_DYNAMIC and OF_OVERLAY are not
On 25 March 2015 at 14:57, Zhou Wang wangzh...@hisilicon.com wrote:
This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
corresponding dts. The default value of ARCH_NR_GPIOS is used to find
Hi Rob,
On 15-03-22 06:20 PM, Rob Herring wrote:
On 03/20/2015 08:06 PM, Scott Branden wrote:
This patchset attempts to standardize the naming of dt-bindings
documents based on the Broadcom vendor prefix of brcm.
Although there are no guidelines currently present for how to name
the
On Tue, Mar 24, 2015 at 10:30:30PM +, Srinivas Kandagatla wrote:
This patch adds bindings for simple eeprom framework which allows eeprom
consumers to talk to eeprom providers to get access to eeprom cell data.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
[Maxime Ripard:
On Tue, Mar 24, 2015 at 10:30:19PM +, Srinivas Kandagatla wrote:
This patch adds just consumers part of the framework just to enable easy
review.
Up until now, EEPROM drivers were stored in drivers/misc, where they all had
to
duplicate pretty much the same code to register a sysfs
From: Zhou Wang wangzhou@gmail.com
The GPIO controller of Hisilicon hip04 Soc uses the IP from Sysnopsis,
gpio-dwapb.c can be reused to support this GPIO controller. This patch
adds related configure item in hisi_defconfig.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Zhou
From: Zhou Wang wangzhou@gmail.com
Hisilicon Soc hip04 has four GPIO controllers, each one has 32
GPIOs and can be configured to be an interrupt controller.The GPIO
controllers are compatible with the snps,dw-apb-gpio driver.
This patch add the corresponding device tree nodes.
Acked-by:
This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
corresponding dts. The default value of ARCH_NR_GPIOS is used to find gpio
base here.
Now this patchset is based on v4.0-rc5
Change in v6:
-
From: kongxinwei kong.kongxin...@hisilicon.com
Thank you all for giving this RFC patches stages some comments. Here is v1
patches and address all the issues raised as part of RFC review.
The Linaro connect introduce 96boards series in Hong Kong,The HiKey board
is the first board to be certified
On Tue, Mar 17, 2015 at 4:09 PM, Sebastian Hesselbarth
sebastian.hesselba...@gmail.com wrote:
If we do this, we should have a look at syscon and potentially also
simple-mfd which will allow us to share the registers and register
platform_devices for the sub-nodes.
I've just sent a pull
Hi Sakari,
On 03/25/2015 02:06 AM, Sakari Ailus wrote:
Hi Jacek,
On Fri, Mar 20, 2015 at 04:03:29PM +0100, Jacek Anaszewski wrote:
This patch adds a description of 'flashes' property
to the samsung-fimc.txt.
Signed-off-by: Jacek Anaszewski j.anaszew...@samsung.com
Acked-by: Kyungmin Park
Hi Sakari,
On 03/25/2015 02:00 AM, Sakari Ailus wrote:
Hi Jacek,
On Tue, Mar 24, 2015 at 09:35:05AM +0100, Jacek Anaszewski wrote:
...
diff --git a/drivers/media/v4l2-core/v4l2-flash.c
b/drivers/media/v4l2-core/v4l2-flash.c
new file mode 100644
index 000..804c2e4
--- /dev/null
+++
From: kongxinwei kong.kongxin...@hisilicon.com
This patch adds the support for hisilicon thermal sensor, within
hisilicon SoC. there will register sensors for thermal framework
and use device tree to bind cooling device.
Signed-off-by: Leo Yan leo@linaro.org
Signed-off-by: kongxinwei
Hi ARM SoC maintainers,
as discussed back and forth with Lee Jones Arnd, here is the patch
set adding the simple-mfd subtree analogous to simple-bus. I have
not got the attentions of some subsystem maintainers but I'm out of
patience and thus assume they just don't care. However for us in the
From: kongxinwei kong.kongxin...@hisilicon.com
This adds documentation of device tree bindings for the
thermal sensor controller of hi6220 SoC.
Signed-off-by: Leo Yan leo@linaro.org
Signed-off-by: kongxinwei kong.kongxin...@hisilicon.com
---
.../bindings/thermal/hisilicon-thermal.txt
Hi,
Am 25.03.2015 um 02:45 schrieb Sebastian Reichel s...@kernel.org:
Hi,
On Tue, Mar 24, 2015 at 06:58:15PM +0100, Dr. H. Nikolaus Schaller wrote:
So you propose that the parent-child relationship is “control”? I.e. some
channel which allows to address some bus client (through reg) and
On 2015/3/25 15:02, Haojian Zhuang wrote:
On 25 March 2015 at 14:57, Zhou Wang wangzh...@hisilicon.com wrote:
This series add the support for the GPIOs of Hisilicon Soc hip04. Hip04 uses
synopsis' GPIO IP, and we use the dwapb GPIO driver here. This series add the
corresponding dts. The
On Thu, Dec 25, 2014 at 09:49:10AM -0800, Kevin Cernekee wrote:
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC. To
avoid possible
Support only for ETF, FUNNEL, STM are included currently.
Support for ETM, TPIU and the replicator linked to it are not included in
this version patch.
Signed-off-by: Chunyan Zhang zhang.chun...@linaro.org
---
arch/arm64/boot/dts/sprd/sc9836.dtsi | 55
1 file
Hi Sricharan,
On Fri, 2015-03-13 at 23:19 +0530, Sricharan R wrote:
#define QUP_I2C_MASTER_GEN 0x408
+#define QUP_I2C_MASTER_CONFIG 0x408
Unused.
#define QUP_READ_LIMIT 256
+#define MX_TX_RX_LEN SZ_64K
+#define MX_BLOCKS
Hi Grant,
On Tue, Mar 24, 2015 at 11:54 PM, Grant Likely grant.lik...@linaro.org wrote:
On Fri, 20 Mar 2015 08:32:12 -0500
, Rob Herring robherri...@gmail.com
wrote:
On Fri, Mar 20, 2015 at 7:25 AM, Grant Likely grant.lik...@linaro.org
wrote:
On Fri, 23 Jan 2015 17:10:04 +0100
, Geert
Support only for ETF, FUNNEL, STM are included currently.
Support for ETM, TPIU and the replicator linked to it are not included in
this version patch.
Signed-off-by: Chunyan Zhang zhang.chun...@linaro.org
---
Change for v2:
- Corrected the TMC whose space is wrongly used as ETB in v1.
-
On Tue, Mar 24, 2015 at 11:08 PM, Mathieu Poirier
mathieu.poir...@linaro.org wrote:
On 23 March 2015 at 23:48, Chunyan Zhang zhang.chun...@linaro.org wrote:
Support only for ETB, FUNNEL, STM are included currently.
Support for ETM, TPIU and the replicator linked to it are not included in
this
On 03/24/2015 02:25 AM, Lee Jones wrote:
On current ST platforms the LPC controls a number of functions including
Watchdog and Real Time Clock. This patch provides the bindings used to
configure LPC in Watchdog mode.
Signed-off-by: Lee Jones lee.jo...@linaro.org
---
Hi Ingi,
Thank you for the patch.
On Wed, Mar 25, 2015 at 10:30:44AM +0900, Ingi Kim wrote:
This patch adds a driver to support the ktd2692 flash LEDs.
ktd2692 can control flash current by ExpressWire interface.
Signed-off-by: Ingi Kim ingi2@samsung.com
---
drivers/leds/Kconfig
On Fri, Feb 20, 2015 at 05:02:57PM +0100, Robert Jarzmik wrote:
Lee Jones lee.jo...@linaro.org writes:
Arnd, Greg,
Perhaps you have some ideas WRT programmables (PLDs/CPLDs/FPGAs)?
Hi Arnd and Greg,
I have this driver I'm upstreaming, which comes out of
On 25/03/15 07:16, Sascha Hauer wrote:
On Tue, Mar 24, 2015 at 10:30:19PM +, Srinivas Kandagatla wrote:
This patch adds just consumers part of the framework just to enable easy
review.
Up until now, EEPROM drivers were stored in drivers/misc, where they all had to
duplicate pretty much
Hi Sricharan,
On Fri, 2015-03-13 at 23:19 +0530, Sricharan R wrote:
From: Andy Gross agr...@codeaurora.org
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a operation like read/write. This new tagging version
This DMAC is Renesas USB high-speed module DMA controller that
supports slave transfer.
This USB-DMAC has similar register sets with R-Car Gen2 DMAC, but
the USB-DMAC has specific registers to control the USB transactions.
If this code is added into the rcar-dmac driver, it will become
Document the device tree bindings for the Renesas USB DMA
Controller (USB-DMAC).
Signed-off-by: Yoshihiro Shimoda yoshihiro.shimoda...@renesas.com
---
.../devicetree/bindings/dma/renesas,usb-dmac.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644
This patch set is based on slave-dma.git / next branch.
(commit id = ebb3abd4042e2ab5f97c43a6f71b206947255fd6)
Changes from v2:
- Change descriptor management to store the residue in descriptor instead
of the channel.
- Change acceptable any sg_len.
- Modify usb_dmac_tx_status() to
Hi,
Just wondering if this has gotten lost in the archives?
Regards,
ZubairLK
On 09/03/15 11:58, Zubair Lutfullah Kakakhel wrote:
Hi,
Two patches based on 4.0-rc3 that add NAND and BCH controller
drivers for the Ingenic JZ4780 SoC.
Core JZ4780 support is still in-flight.
Review and
On Mon, 23 Mar 2015 15:06:35 +1100
, Benjamin Herrenschmidt b...@kernel.crashing.org
wrote:
On Mon, 2015-03-23 at 14:50 +1100, Michael Ellerman wrote:
On Mon, 2015-23-03 at 03:16:38 UTC, Benjamin Herrenschmidt wrote:
The sdc node is missing the ranges property, it needs to be treated
as
Hi,
On Wed, Mar 25, 2015 at 08:59:14AM +0100, Dr. H. Nikolaus Schaller wrote:
Am 25.03.2015 um 02:45 schrieb Sebastian Reichel s...@kernel.org:
On Tue, Mar 24, 2015 at 06:58:15PM +0100, Dr. H. Nikolaus Schaller wrote:
So you propose that the parent-child relationship is “control”? I.e. some
On Tue, Mar 24, 2015 at 6:04 AM, Thierry Reding
thierry.red...@gmail.com wrote:
On Wed, Feb 11, 2015 at 06:50:08PM +0100, Philipp Zabel wrote:
Add Ampire Co., Ltd. to the list of device tree vendor prefixes.
Signed-off-by: Philipp Zabel p.za...@pengutronix.de
---
Hi,
Just wondering if this has gotten lost in the archives?
Regards,
ZubairLK
On 11/03/15 14:26, Zubair Lutfullah Kakakhel wrote:
Hi,
Here we have two patches that add support for the i2c
controller present in the Ingenic JZ4780.
V1 - V2
Rebased to v4.0-rc3
Minor tweaks/fixes.
Hi Neil,
On 03/18/2015 01:58 AM, NeilBrown wrote:
uart_{suspend,resume}_port seach the children of a uart device
to find a particular tty device.
This requires all the ttys to be direct children of the uart.
A future patch will allow a 'tty_slave' to intervene between
the port and the
This adds support for Freescale NAND flash controller (NFC) found on
various devices such as Vybrid (VF610), MPC5125, MCF54418 (ColdFire)
and Kinetis K70.
The patchset is based on the patchset by Bill Pringlemeir, see:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/295419
A variant of this
This adds the NAND flash controller (NFC) peripherial. The driver
supports the SLC NAND chips found on Freescale's Vybrid Tower System
Module. The Micron NAND chip on the module needs 4-bit ECC per 512
byte page. Use 24-bit ECC per 2k page, which is supported by the
driver.
Signed-off-by: Bill
Am Montag, den 23.03.2015, 19:17 +0100 schrieb Heiko Stuebner:
Hi Philipp,
Am Donnerstag, 12. März 2015, 21:45:19 schrieb Heiko Stuebner:
At least the Rockchip variant of the dw_hdmi can have controllable power
supplies providing 1.0 and 1.8V. Therefore add the possibility for the
On Wed, Mar 25, 2015 at 2:23 AM, Ralf Baechle r...@linux-mips.org wrote:
On Thu, Dec 25, 2014 at 09:49:10AM -0800, Kevin Cernekee wrote:
BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer
may cause parts
Hi,
Am 25.03.2015 um 16:21 schrieb Sebastian Reichel s...@kernel.org:
Hi,
On Wed, Mar 25, 2015 at 08:59:14AM +0100, Dr. H. Nikolaus Schaller wrote:
Am 25.03.2015 um 02:45 schrieb Sebastian Reichel s...@kernel.org:
On Tue, Mar 24, 2015 at 06:58:15PM +0100, Dr. H. Nikolaus Schaller wrote:
On Wed, Mar 25, 2015 at 08:10:06AM +0100, Sascha Hauer wrote:
On Tue, Mar 24, 2015 at 10:30:30PM +, Srinivas Kandagatla wrote:
This patch adds bindings for simple eeprom framework which allows eeprom
consumers to talk to eeprom providers to get access to eeprom cell data.
This driver supports Freescale NFC (NAND flash controller) found on
Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70.
Limitations:
- DMA and pipelining not used
- Pages larger than 2k are not supported
- No hardware ECC
The driver has only been tested on Vybrid (VF610).
Signed-off-by: Bill
This adds hardware ECC support using the BCH encoder in the NFC IP.
The ECC encoder supports up to 32-bit correction by using 60 error
correction bytes. There is no sub-page ECC step, ECC is calculated
always accross the whole page (up to 2k pages).
Signed-off-by: Bill Pringlemeir
Enable NAND access by adding pinmux and NAND flash controller node
to device tree. The NAND chips currently used on the Colibri VF61
requires 8-bit ECC per 512 byte page, hence specify 32-bit ECC
strength per 2k page size.
Signed-off-by: Stefan Agner ste...@agner.ch
---
Enable the NAND Flash Controller driver which is part of the Vybrid
SoC by default.
Signed-off-by: Stefan Agner ste...@agner.ch
---
arch/arm/mach-imx/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c8dffce..182e30e 100644
Signed-off-by: Bill Pringlemeir bpringlem...@nbsps.com
Signed-off-by: Stefan Agner ste...@agner.ch
---
.../devicetree/bindings/mtd/vf610-nfc.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/vf610-nfc.txt
diff
On 03/18/2015 01:58 AM, NeilBrown wrote:
+ * A tty-slave is a device permanently attached to a particularly
+ * tty, typically wired to a UART.
Why permanently?
Is that a limitation of the implementation or design?
Regards,
Peter Hurley
--
To unsubscribe from this list: send the line
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
Documentation/devicetree/bindings/net/apm-xgene-enet.txt | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
- Added wrapper functions around napi_add, napi_del, napi_enable and
napi_disable
- Moved platform_get_irq function call after reading phy_mode
- Associating the new irq to tx completion for the supported ethernet interfaces
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by:
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
arch/arm64/boot/dts/apm/apm-storm.dtsi | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi
On Fri, Feb 20, 2015 at 07:19:27PM +0800, Chen-Yu Tsai wrote:
From: Carlo Caione ca...@caione.org
Bindings documentation for the AXP20x driver. In this file also
sub-nodes are documented.
Signed-off-by: Carlo Caione ca...@caione.org
[w...@csie.org: clarify interrupt source for the axp
SGMII based 1GbE and 10GbE interfaces support multiple interrupts.
Adding separate tx completion descriptor ring and associating a dedicated irq
for the TX completion.
Signed-off-by: Iyappan Subramanian isubraman...@apm.com
Signed-off-by: Keyur Chudgar kchud...@apm.com
---
Iyappan Subramanian
Document cpuidle states of QCOM cpus. In addition to arm-idle-state
compatible string, the ARM idle state definition must define one of the
following compatible strings -
qcom,idle-state-ret,
qcom,idle-state-spc,
qcom,idle-state-pc,
The compatibles helps the SPM platform
Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
Cc: Stephen Boyd sb...@codeaurora.org
Cc: Arnd Bergmann a...@arndb.de
Cc: Kevin Hilman khil...@linaro.org
Cc: Daniel Lezcano daniel.lezc...@linaro.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
drivers/cpuidle/Kconfig.arm | 7
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer
Update defconfig to allow cpuidle for QCOM cpus.
* Enable QCOM_PM
* Enable ARM_QCOM_CPUIDLE
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig
Add ARM common idle state device bindings for cpuidle support for APQ
8064.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
Add ARM common idle states device bindings for cpuidle support for APQ
8084.
Support Standalone power collapse (SPC) idle state (power down that does not
affect any SoC idle states) for each cpu.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
Update qcom,saw2 node bindings with compatible strings to identify nodes
that provides cpuidle functionality for a particular SoC. Remove
unused compatible strings.
Update examples for different SAW nodes.
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
Add ARM common idle states device bindings for cpuidle support for APQ
8974/8074.
Support Standalone power collapse (SPC) idle state (power down that does
not affect any SoC idle states) for each cpu.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
---
Hi,
This v18 revision of patch has minor changes since v17.
Changes since v17:
- Added: SPM changes submitted on v17, per Daniel's comments.
- Moved: The DT documentation out of SPM driver patch. It was getting bigger.
- Fixed: Per Kumar's comments on removing qcom,saw and other unused
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Cc: Kumar Gala ga...@codeaurora.org
Signed-off-by: Lina Iyer lina.i...@linaro.org
Reviewed-by: Stephen
Hi!
AFAIK the chip simply starts to emit NMEA records if powered on.
There is no command going over the serial interface to address it
or control it.
Right, since GPS basically doesn't need any configuration/control.
That’s not true for other UART attached devices, though.
Do you
Hi,
Am 25.03.2015 um 21:42 schrieb Pavel Machek pa...@ucw.cz:
Hi!
In the case of our GPS, it receives control over the serial connection from
the UART,
Ahem - does it?
AFAIK the chip simply starts to emit NMEA records if powered on. There is no
command going over the serial interface
Hi!
In the case of our GPS, it receives control over the serial connection from
the UART,
Ahem - does it?
AFAIK the chip simply starts to emit NMEA records if powered on. There is no
command going over the serial interface to address it or control it.
Well _most_ GPSes enable you to
subscribe
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More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Juergen,
Juergen Borleis juer...@kreuzholzen.de hat am 24. März 2015 um 21:45
geschrieben:
Stefan Wahren wrote:
[...]
Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM
controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
restrictions. VDD
Am 25.03.2015 um 21:53 schrieb Pavel Machek pa...@ucw.cz:
Hi!
AFAIK the chip simply starts to emit NMEA records if powered on.
There is no command going over the serial interface to address it
or control it.
Right, since GPS basically doesn't need any configuration/control.
That’s not
On Wed, 25 Mar 2015 12:30:00 -0400 Peter Hurley pe...@hurleysoftware.com
wrote:
On 03/18/2015 01:58 AM, NeilBrown wrote:
+ * A tty-slave is a device permanently attached to a particularly
+ * tty, typically wired to a UART.
Why permanently?
Is that a limitation of the implementation or
On 03/20, Daniel Lezcano wrote:
The current state of the different cpuidle drivers is the different PM
operations are passed via the platform_data using the platform driver
paradigm.
This approach allowed to split the low level PM code from the arch specific
and the generic cpuidle code.
On Thu, Mar 26, 2015 at 04:09:23AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 26 March 2015 03:47 AM, Dmitry Torokhov wrote:
On Wed, Mar 25, 2015 at 3:11 PM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
Hi,
On Thursday 26 March 2015 04:19 AM, Dmitry Torokhov wrote:
On Thu, Mar 26, 2015 at 04:09:23AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 26 March 2015 03:47 AM, Dmitry Torokhov wrote:
On Wed, Mar 25, 2015 at 3:11 PM, Kishon Vijay Abraham I kis...@ti.com
wrote:
Hi,
On
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
This driver adds support for USB 2.0 host and device phy for
Broadcom's Cygnus chipset. The host controller is connected to
three separate phys and one of the phys (port 2) is connected to
the device controller
one blank line
Le mardi 24 mars 2015 à 09:01 +0100, Hans de Goede a écrit :
Hi,
On 24-03-15 00:12, Rob Herring wrote:
On Mon, Mar 23, 2015 at 6:30 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 22-03-15 22:01, Rob Herring wrote:
snip
There is already serial-number (a string) which
On Thursday 26 March 2015 04:12 AM, Dmitry Torokhov wrote:
Hi Kishon,
On Thu, Mar 26, 2015 at 03:58:50AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
+struct bcm_phy_driver {
+ void __iomem *usbphy_regs;
+ void __iomem
* Kalle Valo kv...@codeaurora.org [150322 21:52]:
Tony Lindgren t...@atomide.com writes:
After John retired we actually have two set of trees now: mac80211
maintained by Johannes and wireless-drivers maintained by me. I haven't
pulled anything from your tree and I'm 100% sure Johannes
+Maxime, Srinivas, patrice
On Monday 09 March 2015 06:55 PM, Axel Lin wrote:
2015-03-09 19:44 GMT+08:00 Kishon Vijay Abraham I kis...@ti.com:
Hi,
On Thursday 05 March 2015 07:27 AM, Axel Lin wrote:
The defines in phy-miphy365x.h are all covered in phy.h:
MIPHY_TYPE_SATA == PHY_TYPE_STA
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
Multi-port phy's may have per-port power supplies. Let's change phy core
to first attempt to look up the supply at the port level, and then, if
not found, check parent device.
Why not just have every port provide the power supply
Hi,
On Thursday 26 March 2015 03:47 AM, Dmitry Torokhov wrote:
On Wed, Mar 25, 2015 at 3:11 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
Multi-port phy's may have per-port power supplies. Let's change phy core
to first
From: Wei Chen wei.c...@csr.com
Add hwspinlock support for the CSR atlas7 SoC.
The Hardware Spinlock device on atlas7 provides hardware assistance
for synchronization between the multiple processors in the system
(dual Cortex-A7, CAN bus Cortex-M3 and audio DSP).
Signed-off-by: Wei Chen
On Thu, Mar 26, 2015 at 05:14:07AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 26 March 2015 04:19 AM, Dmitry Torokhov wrote:
On Thu, Mar 26, 2015 at 04:09:23AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Thursday 26 March 2015 03:47 AM, Dmitry Torokhov wrote:
On Wed, Mar
On 15-03-25 05:01 PM, Kishon Vijay Abraham I wrote:
On Thursday 26 March 2015 04:12 AM, Dmitry Torokhov wrote:
Hi Kishon,
On Thu, Mar 26, 2015 at 03:58:50AM +0530, Kishon Vijay Abraham I wrote:
Hi,
On Saturday 21 March 2015 02:55 AM, Arun Ramamurthy wrote:
+struct bcm_phy_driver {
+
Hi Varka,
On 2015년 03월 25일 12:28, Varka Bhadram wrote:
On 03/25/2015 07:00 AM, Ingi Kim wrote:
This patch adds a driver to support the ktd2692 flash LEDs.
ktd2692 can control flash current by ExpressWire interface.
Signed-off-by: Ingi Kim ingi2@samsung.com
---
drivers/leds/Kconfig
Hi Varka,
Thanks for the review
On 2015년 03월 25일 12:31, Varka Bhadram wrote:
On 03/25/2015 07:00 AM, Ingi Kim wrote:
This patch adds the device tree bindings for ktd2692 flash LEDs.
Add optional properties 'flash-timeout-us' to control flash timeout
and 'vin-supply' for flash-led regulator
On 25 March 2015 at 15:04, Zhou Wang wangzh...@hisilicon.com wrote:
This patch adds dts support for NAND flash controller of Hisilicon Soc Hip04.
Now it is based on v4.0-rc5
Changes in v3:
- Change E-mail address in signed-off-by to wangzh...@hisilicon.com
Changes in v2:
- Base on v3.19-rc1
Hi Mark
These are remains of my previous patch set.
Basically, these doesn't need soc-core's new feature, but it is assuming
DPCM base sampling rate convert has both playback/capture in same time.
1 - 2: new Renesas sound card for DPCM
3: bug fix patch. it can be applied in
Dear Daniel,
On Wed, 18 Mar 2015 12:24:40 +
Daniel Stone dan...@fooishbar.org wrote:
Hi,
Some feedback comments - most of these are not unique to your 5433
DECON driver but endemic throughout Exynos, so I don't blame you for
them - but they should be fixed anyway.
On 18 March 2015 at
Dear Inki dae,
On Tue, 24 Mar 2015 14:51:31 +0900
Inki Dae inki@samsung.com wrote:
On 2015년 03월 18일 17:16, Hyungwon Hwang wrote:
MIC(Mobile image compressor) is newly added IP in Exynos5433. MIC
resides between decon and mipi dsim, and compresses frame data by
50%. With dsi, not
Dear Inki dae,
Sorry for the previous mail which is not completed. I typed something
and it was the shortcut for maybe.
On Tue, 24 Mar 2015 14:51:31 +0900
Inki Dae inki@samsung.com wrote:
On 2015년 03월 18일 17:16, Hyungwon Hwang wrote:
MIC(Mobile image compressor) is newly added IP in
Enable DCU pixel clock when platform devices initinalizing and
provide enable and disable pixel clock functions for drm driver
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Xiubo Li lixi...@cmss.chinamobile.com
Signed-off-by: Jianwei Wang b52...@freescale.com
---
This patch add support for Two Dimensional Animation and Compositing
Engine (2D-ACE) on the Freescale SoCs.
2D-ACE is a Freescale display controller. 2D-ACE describes
the functionality of the module extremely well its name is a value
that cannot be used as a token in programming languages.
Hi Ivan,
On 03/25/2015 05:54 PM, Ivan T. Ivanov wrote:
Hi Sricharan,
On Fri, 2015-03-13 at 23:19 +0530, Sricharan R wrote:
From: Andy Gross agr...@codeaurora.org
QUP from version 2.1.1 onwards, supports a new format of
i2c command tags. Tag codes instructs the controller to
perform a
Hi!
Main reason is, that I would need to go
through the UART to “communicate with the w2sg0004.
You can always communicate” through the UART. Even without DT. As long as
the connected chip is powered up by any means (could be some
fixed-regulator
or hard wired).
But you don't
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