On 2015-04-03 22:09, Russell King - ARM Linux wrote:
> On Fri, Apr 03, 2015 at 09:44:48PM +0200, Stefan Agner wrote:
>> In order to support SoC with heterogenous CPU architectures (such
>> as Freescale Vybrid/i.MXSX) it is preferable to use the same
>> architecture (ARCH_MXC in this case) for the M
Add device tree binding documentation for the Qualcom Shared Memory
manager.
Signed-off-by: Bjorn Andersson
---
.../devicetree/bindings/soc/qcom/qcom,smem.txt | 49 ++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,sme
On Sat, Apr 4, 2015 at 1:09 AM, Andy Shevchenko
wrote:
> On Fri, Apr 3, 2015 at 8:01 PM, Maxime Coquelin
> wrote:
>> STM32 MCUs feature 16 and 32 bits general purpose timers with prescalers.
>> The drivers detects whether the time is 16 or 32 bits, and applies a
>> 1024 prescaler value if it is 1
On Fri, Apr 3, 2015 at 8:01 PM, Maxime Coquelin
wrote:
> STM32 MCUs feature 16 and 32 bits general purpose timers with prescalers.
> The drivers detects whether the time is 16 or 32 bits, and applies a
> 1024 prescaler value if it is 16 bits.
>
Few comments below.
> Reviewed-by: Linus Walleij
>
On Fri, Apr 3, 2015 at 8:01 PM, Maxime Coquelin
wrote:
> This drivers adds support to the STM32 USART controller, which is a
> standard serial driver.
>
Few minor comments.
> Tested-by: Chanwoo Choi
> Signed-off-by: Maxime Coquelin
> ---
> drivers/tty/serial/Kconfig | 17 +
> drivers/t
Lina Iyer writes:
> SPM is a hardware block that controls the peripheral logic surrounding
> the application cores (cpu/l$). When the core executes WFI instruction,
> the SPM takes over the putting the core in low power state as
> configured. The wake up for the SPM is an interrupt at the GIC, wh
On Fri, Apr 03, 2015 at 10:26:24PM +0200, Pavel Machek wrote:
> > > + - power-gpios: Reference to the GPIO that controls the power for the
> > > chip.
> >
> > You're using power-gpios in documentation only.
>
> Which is ok, because generic code adds "-gpios" itself.
Do you think you need this
Hi Pavel,
On Fri, Apr 03, 2015 at 10:26:24PM +0200, Pavel Machek wrote:
>
> Documentation for adp1653 binding.
>
> ---
>
> > Please split this as Javier suggested. I'd think both could go through
> > the media-tree unless someone objects.
>
> Please apply.
>
> > > + - power-gpios: Reference
On Fri, Apr 03, 2015 at 10:29:53PM +0200, Pavel Machek wrote:
> On Fri 2015-04-03 14:23:56, Sakari Ailus wrote:
> > Hi Pavel,
> >
> > On Fri, Apr 03, 2015 at 10:23:44AM +0200, Pavel Machek wrote:
> > > Hi!
> > >
> > > > Hi Pawel,
> > >
> > > I'm still Pavel. v, not w.
> >
> > I know too many Pa
Signed-off-by: Joachim Eastwood
---
arch/arm/boot/dts/lpc4357-ea4357.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/lpc4357-ea4357.dts
b/arch/arm/boot/dts/lpc4357-ea4357.dts
index 39340e355b0a..c2b85f8e6e31 100644
--- a/arch/arm/boot/dts/lpc4357-ea
Driver for the GPIO block found on NXP LPC18xx/43xx devices.
The GPIO block is divided into 8 ports which each support up
to 32 gpios. The which gpios that are available depends on the
specific device and it's package.
Signed-off-by: Joachim Eastwood
---
drivers/gpio/Kconfig| 8 ++
dr
This patch set adds drivers for pinctrl and gpio on NXP LPC18xx/43xx
devices. Patchset is based on Linus master 4.0-rc6.
The pinctrl driver uses the generic muxing and properties DT bindings as
described in pinctrl-bindings.txt. There is still two TODOs left in the
pinctrl driver regarding propert
Signed-off-by: Joachim Eastwood
---
.../bindings/pinctrl/nxp,lpc1850-scu.txt | 57 ++
1 file changed, 57 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc18
Signed-off-by: Joachim Eastwood
---
arch/arm/boot/dts/lpc18xx.dtsi | 57 ++
1 file changed, 57 insertions(+)
diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi
index 8e9f51c88fad..e0099a7793b9 100644
--- a/arch/arm/boot/dts/lpc18x
Signed-off-by: Joachim Eastwood
---
.../devicetree/bindings/gpio/nxp,lpc1850-gpio.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt
diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpi
Pinctrl driver for the System Control Unit (SCU) found on NXP
LPC18xx/43xx devices.
Driver uses the generic pinctrl DT bindings for multiplexing
and property settings.
Signed-off-by: Joachim Eastwood
---
drivers/pinctrl/Kconfig |8 +
drivers/pinctrl/Makefile |1 +
dri
Hi!
> > + pd->max_flash_intensity = val/1000;
> > +
> > + if (of_property_read_u32(child, "max-microamp", &val))
> > + return -EINVAL;
> > + pd->max_torch_intensity = val/1000;
>
> I think you need to do of_node_put(child) here and after you're done with
> indicator below.
...and
We were having intermittent problems writing to SRAM chip on SPI bus on vf610
SoM. Added support for CS setup and hold times to meet the SRAM spec. In the
process noticed that the baud rate was a little high.
Changes since v2:
* Incorporate fixes per Stefen Agner review, namely moved hard-coded
Add delay between chip select and clock signals, before clock starts and
after clock stops.
Signed-off-by: Aaron Brice
---
drivers/spi/spi-fsl-dspi.c | 64 +++---
1 file changed, 60 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-fsl-dspi.c b/d
Previous algorithm had an outer loop with the values {2,3,5,7} and an
inner loop with {2,4,6,8,16,32,...,32768}, and would pick the first
value over the required scaling value (where the total scale was the two
numbers multiplied).
Since the inner loop went up to 32768 it would always pick a value
Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to
support delays before and after starting the clock in a transfer.
Signed-off-by: Aaron Brice
---
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/dev
[+cc Ben, linuxppc-dev, Grant, Rob, devicetree]
On Tue, Mar 31, 2015 at 07:57:48PM -0700, Yinghai Lu wrote:
> Found "no compatible bridge window" warning in boot log from T5-8.
>
> pci :00:01.0: can't claim BAR 15 [mem 0x1-0x4afff pref]: no
> compatible bridge window
>
> That re
Hi!
> >>+- flash-timeout-us : Timeout in microseconds after which the flash
> >>+ LED is turned off. If omitted this will default to the
> >>+maximum timeout allowed by the device.
> >>
> >>
> >> Examples:
> >
> >Pavel pointed out that the brightness between ma
On Fri 2015-04-03 14:23:56, Sakari Ailus wrote:
> Hi Pavel,
>
> On Fri, Apr 03, 2015 at 10:23:44AM +0200, Pavel Machek wrote:
> > Hi!
> >
> > > Hi Pawel,
> >
> > I'm still Pavel. v, not w.
>
> I know too many Pawels. Sorry about that. :-)
>
> > I guess it uses adp1653_id_table. I'd hade to ad
Documentation for adp1653 binding.
---
> Please split this as Javier suggested. I'd think both could go through
> the media-tree unless someone objects.
Please apply.
> > + - power-gpios: Reference to the GPIO that controls the power for the
> > chip.
>
> You're using power-gpios in documen
On Fri, Apr 03, 2015 at 09:44:48PM +0200, Stefan Agner wrote:
> In order to support SoC with heterogenous CPU architectures (such
> as Freescale Vybrid/i.MXSX) it is preferable to use the same
> architecture (ARCH_MXC in this case) for the MMU enabled and !MMU
> CPU. Hence allow to select MULTIPLAT
> +/**
> + * nvec_slave_cb - I2C slave callback
> + *
> + * This callback fills our RX buffers and empties our TX
> + * buffers. This uses a finite state machine.
> + */
> +static int nvec_slave_cb(struct i2c_client *client,
> + enum i2c_slave_event event, u8 *val)
> +{
> + struct n
On Wed, Mar 25, 2015 at 08:52:11PM +0800, Chunyan Zhang wrote:
> Support only for ETF, FUNNEL, STM are included currently.
> Support for ETM, TPIU and the replicator linked to it are not included in
> this version patch.
>
> Signed-off-by: Chunyan Zhang
> ---
> Change for v2:
> - Corrected the T
This adds an initial device tree to run Linux on the Cortex-M4 on
the Vybrid based Colibri VF61 module.
Signed-off-by: Stefan Agner
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/vf610m4-colibri.dts | 98 +++
arch/arm/boot/dts/vf610m4.dtsi
From: Arnd Bergmann
Since the multiplatform configuration can support no-MMU kernels now,
there is nothing stopping us from moving the efm32 platform in there
as well. This introduces a new ARCH_MULTI_V7M CPU architecture selection
option, since v7-M is incompatible with v7-A, and we can have eit
Remove the needless differences between MMU/!MMU addruart calls.
This allows to use the same addruart macro on SoC level. Useful
for SoC consisting of multiple CPUs with and without MMU such as
Freescale Vybrid.
Signed-off-by: Stefan Agner
---
arch/arm/include/debug/efm32.S | 2 +-
arch/arm/kern
Add defconfig for Linux on Vybrid (vf610) on the secondary Cortex-
M4 CPU. The use of a XIP image has been tested which needs to be
loaded (e.g. using the custom m4boot loader) to the end of the
available RAM at address 0x8f00. The Cortex-M4 has a code-alias
which makes sure that the instructio
Add the minimal dependencies required to use the Vybrid PIT
clocksource driver. Those are not part of the SoC dependencies.
Acked-by: Daniel Lezcano
Signed-off-by: Stefan Agner
---
drivers/clocksource/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clocksource/Kconfig b/dr
On Mon, Mar 30, 2015 at 11:00:11PM +0300, Andrey Danin wrote:
> NVEC driver contains code to manage tegra i2c controller in slave mode.
> I2C slave support was implemented in linux kernel. The goal of this
> patch serie is to implement I2C slave mode in tegra drived and rework
> NVEC driver to use
> +static void tegra_i2c_slave_write(struct tegra_i2c_dev *i2c_dev, u32 val)
> +{
> + i2c_writel(i2c_dev, val, I2C_SL_RCVD);
> +
> + /*
> + * TODO: A correct fix needs to be found for this.
> + *
> + * We experience less incomplete messages with this delay than without
> +
Support the NVIC interrupt controller as node parent of the MSCM
interrupt router. On the dual-core variants of Vybird (VF6xx), the
NVIC interrupt controller is used by the Cortex-M4. To support
running Linux on this core too, MSCM needs NVIC parent support too.
Signed-off-by: Stefan Agner
---
d
Vybrids has 112 peripherial interrupts which can be routed to the
Cortex-M4's NVIC interrupt controller.
Signed-off-by: Stefan Agner
---
arch/arm/mm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 16d077e..8eebc0d 100644
--- a/arch/arm/
Add support for hierarchy irq domains. This is required to stack
the MSCM interrupt router and the NVIC controller found in Vybrid
SoC.
Signed-off-by: Stefan Agner
---
drivers/irqchip/Kconfig| 1 +
drivers/irqchip/irq-nvic.c | 28 +++-
2 files changed, 28 insertions(
Use the new helper function irq_domain_set_info to make sure the
function irq_domain_set_hwirq_and_chip is being called, which is
crucial to save irqdomain specific data to irq_data.
Signed-off-by: Stefan Agner
---
kernel/irq/generic-chip.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions
This patch allows to build the Kernel for Vybrid (VF6xx) SoC
when ARMv7-M CPU is selected. The resulting image runs on the
secondary Cortex-M4 core. This core has equally access to all
peripherals as the main Cortex-A5 core. However, there is no
resource control mechanism, hence when both cores are
In order to support SoC with heterogenous CPU architectures (such
as Freescale Vybrid/i.MXSX) it is preferable to use the same
architecture (ARCH_MXC in this case) for the MMU enabled and !MMU
CPU. Hence allow to select MULTIPLATFORM even without MMU.
Signed-off-by: Stefan Agner
---
arch/arm/Kco
The fourth version has one small fix in the MSCM IR driver and
one dependency fix.
Like version 3 of the patchset, it does not contain the interrupt
router driver anymore (MSCM IR). The driver has been merged
inbetween:
https://lkml.org/lkml/2015/3/8/6
This patchset extends the NVIC driver to sup
Hi Laurent,
On Fri, Apr 3, 2015 at 6:24 PM, Laurent Pinchart
wrote:
> On Friday 03 April 2015 14:41:57 Geert Uytterhoeven wrote:
>> This RFC patch series adds board staging support for r8a7740/armadillo.
>> For now this supports only the frame buffer device for the on-board LCD.
>
> I've started
Hi Mark,
On 15-03-30 11:43 PM, Mark Brown wrote:
On Mon, Mar 30, 2015 at 08:16:22PM -0700, Scott Branden wrote:
The audio PLL is embedded in the audio block and only used
by the audio block. The audio PLL registers are also in the middle of
the audio register map.
When you say it's only use
On Tue, Mar 31, 2015 at 02:03:54PM +0100, Zubair Lutfullah Kakakhel wrote:
> Hi,
>
> Here we have two patches that add support for the i2c
> controller present in the Ingenic JZ4780.
>
> Driver tested on the MIPS Creator CI20.
>
> V2 - > V3
> Fixes based on feedback from Wolfram Sang. Thank-you.
On Fri, Apr 3, 2015 at 12:13 PM, Kumar Gala wrote:
>
> On Apr 3, 2015, at 1:18 PM, Olof Johansson wrote:
>
>> On Fri, Apr 03, 2015 at 11:14:01AM -0700, Olof Johansson wrote:
>>> On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote:
On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Ga
On Apr 3, 2015, at 1:18 PM, Olof Johansson wrote:
> On Fri, Apr 03, 2015 at 11:14:01AM -0700, Olof Johansson wrote:
>> On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote:
>>> On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote:
Add initial device tree support for Qualcomm
Hi,
I understand this is bikeshedding to some extent, but I'd also like to
avoid needless variation in binding formats:
On Tue, Mar 3, 2015 at 1:32 AM, Linus Walleij wrote:
> +
> +foo@1000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x01 0x1000>;
> +
>
> >> + paddr = dma_map_single(ctx->dev, ctx->dma_buffer, readlen,
> >> +DMA_FROM_DEVICE);
> >
> > The device should be the device of the dma channel.
>
> The device is not visible on linux, DMA is done by the helper processor.
> Perhaps you cah give me some idea how
On Fri, Apr 03, 2015 at 11:14:01AM -0700, Olof Johansson wrote:
> On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote:
> > On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote:
> > > Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board.
> > > This board is also
> While thinking about it (and I still think of it as a 'big issue'
> compared to the intention of the initial patch) I came to the
> conclusion that I should maybe just go for a board-specific
> i2c-mux-pinctrl node instead of adding it to the SoC dtsi. That will
> also avoid doubled i2c busses o
On Fri, Apr 03, 2015 at 11:12:17AM -0700, Olof Johansson wrote:
> On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote:
> > Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board.
> > This board is also referred to as the DragonBoard 410c.
> >
> > Signed-off-by: Kumar Gala
On Mon, Mar 23, 2015 at 05:51:05PM -0500, Kumar Gala wrote:
> Add initial device tree support for Qualcomm APQ8016 SBC Evaluation board.
> This board is also referred to as the DragonBoard 410c.
>
> Signed-off-by: Kumar Gala
Hi,
Patch applied but see comment below.
> ---
> arch/arm64/boot/dts
On 03/04/15 06:38, Andy Shevchenko wrote:
> On Thu, Apr 2, 2015 at 10:23 PM, Jonathan Richardson
> wrote:
>> The Broadcom MSPI controller is used on various chips. The driver only
>> supported BCM53xx chips with BCMA (an AMBA bus variant). The driver is
>> refactored to make BCMA optional and prov
On Fri, 2015-04-03 at 19:01 +0200, Maxime Coquelin wrote:
> This drivers adds support to the STM32 USART controller, which is a
> standard serial driver.
trivia:
> diff --git a/drivers/tty/serial/stm32-usart.c
> b/drivers/tty/serial/stm32-usart.c
[]
> +static struct uart_ops stm32_uart_ops = {
On 04/03/2015 01:01 PM, Maxime Coquelin wrote:
> This drivers adds support to the STM32 USART controller, which is a
> standard serial driver.
Reviewed-by: Peter Hurley
PS - I saw Rob's comment about 'hw-flow-ctrl' vs 'auto-flow-control'
and I'm ok with either so feel free to and my review comme
On Fri, Apr 3, 2015 at 12:01 PM, Maxime Coquelin
wrote:
> This adds documentation of device tree bindings for the
> STM32 USART
>
> Tested-by: Chanwoo Choi
> Signed-off-by: Maxime Coquelin
> ---
> .../devicetree/bindings/serial/st,stm32-usart.txt | 32
> ++
> 1 file change
On Fri, Apr 3, 2015 at 12:01 PM, Maxime Coquelin
wrote:
> This adds documentation of device tree bindings for the
> STM32 timer.
>
> Tested-by: Chanwoo Choi
> Signed-off-by: Maxime Coquelin
One minor thing below, otherwise:
Acked-by: Rob Herring
> ---
> .../devicetree/bindings/timer/st,stm3
On Fri, Apr 3, 2015 at 12:01 PM, Maxime Coquelin
wrote:
> This adds documentation of device tree bindings for the
> ARM System timer.
>
> Tested-by: Chanwoo Choi
> Signed-off-by: Maxime Coquelin
Acked-by: Rob Herring
> ---
> .../devicetree/bindings/arm/armv7m_systick.txt | 26
>
On Fri, Apr 03, 2015 at 03:27:40PM +0200, Geert Uytterhoeven wrote:
> On Fri, Apr 3, 2015 at 2:57 PM, Dan Carpenter
> wrote:
> >> + error = clk_register_clkdev(clk, bsc->con_id, bsc->dev_id);
> >> + if (error)
> >> + pr_err("Failed to register clock %s (%d)\n", bsc->clk,
> >>
This patch adds clocksource support for ARMv7-M's System timer,
also known as SysTick.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
drivers/clocksource/Kconfig | 7
drivers/clocksource/Makefile | 1 +
drivers/clocksource/armv7m_systick.c | 79 ++
This adds documentation of device tree bindings for the
STM32 reset controller.
Tested-by: Chanwoo Choi
Acked-by: Philipp Zabel
Acked-by: Rob Herring
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/reset/st,stm32-rcc.txt | 107 +
1 file changed, 107 insertio
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
arch/arm/boot/dts/armv7-m.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi
index 5a660d0..b1ad7cf 100644
--- a/arch/arm/boot/dts/armv7-m.dtsi
+++ b/arch/arm/bo
This drivers adds support to the STM32 USART controller, which is a
standard serial driver.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
drivers/tty/serial/Kconfig | 17 +
drivers/tty/serial/Makefile | 1 +
drivers/tty/serial/stm32-usart.c | 736 +
>From Cortex-M reference manuals, the nvic supports up to 240 interrupts.
So the number of entries in vectors table is up to 256.
This patch adds a new config flag to specify the number of external interrupts.
Some ifdeferies are added in order to respect the natural alignment without
wasting too
STM32 MCUs feature 16 and 32 bits general purpose timers with prescalers.
The drivers detects whether the time is 16 or 32 bits, and applies a
1024 prescaler value if it is 16 bits.
Reviewed-by: Linus Walleij
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
drivers/clocksource/Kconfi
This adds documentation of device tree bindings for the
STM32 timer.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/
This adds documentation of device tree bindings for the
ARM System timer.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/arm/armv7m_systick.txt | 26 ++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bind
The STMicrolectornics's STM32F419 MCU has the following main features:
- Cortex-M4 core running up to @180MHz
- 2MB internal flash, 256KBytes internal RAM
- FMC controller to connect SDRAM, NOR and NAND memories
- SD/MMC/SDIO support
- Ethernet controller
- USB OTFG FS & HS controllers
- I2C
On Fri, Apr 03, 2015 at 03:57:27PM +0300, Dan Carpenter wrote:
> On Fri, Apr 03, 2015 at 02:42:02PM +0200, Geert Uytterhoeven wrote:
> > +int __init board_staging_register_clock(const struct board_staging_clk
> > *bsc)
> > +{
> > + struct clk *clk;
> > + int error;
> > +
> > + pr_debug("Regi
This patch adds a new config for STM32 MCUs.
STM32F429 Discovery board boots successfully with this config applied.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
arch/arm/configs/stm32_defconfig | 71
1 file changed, 71 insertions(+)
create
Add a MAINTAINER entry covering all STM32 machine and drivers files.
Signed-off-by: Maxime Coquelin
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ddc5a8c..08c08c4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1467,6 +1467,14 @@ F:
This adds documentation of device tree bindings for the
STM32 USART
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
.../devicetree/bindings/serial/st,stm32-usart.txt | 32 ++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/s
STMicrolectronics's STM32 series is a family of Cortex-M
microcontrollers. It is used in various applications, and
proposes a wide range of peripherals.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
Documentation/arm/stm32/overview.txt | 32 ++
Doc
The STM32 MCUs family IPs can be reset by accessing some registers
from the RCC block.
The list of available reset lines is documented in the DT bindings.
Tested-by: Chanwoo Choi
Acked-by: Philipp Zabel
Signed-off-by: Maxime Coquelin
---
drivers/reset/Makefile | 1 +
drivers/reset/rese
When Kernel is executed in place from ROM, the symbol addresses can be
lower than the page offset.
Tested-by: Chanwoo Choi
Signed-off-by: Maxime Coquelin
---
scripts/link-vmlinux.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinu
This fifth round only contains cosmetic fixes, and add some more Acks.
STM32 MCUs are Cortex-M CPU, used in various applications (consumer
electronics, industrial applications, hobbyists...).
Datasheets, user and programming manuals are publicly available on
STMicroelectronics website.
With this
Hello Geert,
Thank you for the patches.
On Friday 03 April 2015 14:41:57 Geert Uytterhoeven wrote:
> Hi all,
>
> This RFC patch series adds board staging support for r8a7740/armadillo.
> For now this supports only the frame buffer device for the on-board LCD.
I've started adding DT suppor
Hi,
On Thursday 02 April 2015 02:20 AM, Arun Ramamurthy wrote:
This driver adds support for USB 2.0 host and device phy for
Broadcom's Cygnus chipset. The host controller is connected to
three separate phys and one of the phys (port 2) is connected to
the device controller
Reviewed-by: Ray Jui
Hi,
On Fri, Apr 03, 2015 at 10:49:12AM +0200, Javier Martinez Canillas wrote:
> >> The convention nowadays is to not use unnamed DT properties for GPIOs
> >> but instead use a prefix that explains what those GPIOs are used for.
> >> So something like "power-gpios" or "power-gpio" (if there is only
Hi,
On Thursday 02 April 2015 02:20 AM, Arun Ramamurthy wrote:
Broadcom's Cygnus chip has a USB 2.0 host controller connected to
three separate phys. One of the phs (port 2) is also connectd to
a usb 2.0 device controller
Signed-off-by: Arun Ramamurthy
Reviewed-by: Ray Jui
Reviewed-by: Scott
On Thu, Apr 2, 2015 at 9:11 PM, Tim Bird wrote:
> On Wed, Apr 1, 2015 at 9:40 PM, Ohad Ben-Cohen wrote:
>> Sorry, I can't take this without a DT ack.
>
> Hmmm.
>
> The policy seems to be:
> "For driver (not subsystem) bindings: If you are comfortable with the
> binding, and it hasn't re
On Thursday 02 April 2015 02:20 AM, Arun Ramamurthy wrote:
From: Dmitry Torokhov
Multi-port phy's may have per-port power supplies. Let's change phy core
to first attempt to look up the supply at the port level, and then, if
not found, check parent device.
This commit log is no longer valid
On Thu, Apr 2, 2015 at 10:23 PM, Jonathan Richardson
wrote:
> The Broadcom MSPI controller is used on various chips. The driver only
> supported BCM53xx chips with BCMA (an AMBA bus variant). The driver is
> refactored to make BCMA optional and provides a new config for non BCMA
> systems.
> str
On Thu, Apr 2, 2015 at 10:23 PM, Jonathan Richardson
wrote:
> The Broadcom MSPI controller is used on various SoCs. It is being
> renamed so that it can be extended and reused on other chips. It is
> renamed to bcm-mspi.
>
What if you resend this one with -M -C applied?
--
With Best Regards,
An
On Fri, Apr 3, 2015 at 2:57 PM, Dan Carpenter wrote:
>> + error = clk_register_clkdev(clk, bsc->con_id, bsc->dev_id);
>> + if (error)
>> + pr_err("Failed to register clock %s (%d)\n", bsc->clk, error);
>> + return error;
>
> Missing curly braces. Also it's weird th
On Fri, Apr 03, 2015 at 02:42:02PM +0200, Geert Uytterhoeven wrote:
> +int __init board_staging_register_clock(const struct board_staging_clk *bsc)
> +{
> + struct clk *clk;
> + int error;
> +
> + pr_debug("Registering clock %s for con_id %s dev_id %s\n", bsc->clk,
> + bsc-
Hi Sakari,
On 04/03/2015 02:09 PM, Sakari Ailus wrote:
Hi Jacek,
On Tue, Mar 31, 2015 at 03:52:37PM +0200, Jacek Anaszewski wrote:
Description of flash LEDs related properties was not precise regarding
the state of corresponding settings in case a property is missing.
Add relevant statements.
Add support for easy registering of one ore more platform devices that
may:
- need clocks that are described in DT,
- need pin control configuration,
- rely on a configured GPIO,
- be part of a PM Domain.
All these dependencies are optional.
Signed-off-by: Geert Uytterhoeven
---
drivers
Currently the staging board code is initialized from a late_initcall().
However, unused PM domains are also disabled from a late_initcall(),
which happens before due to link order.
Change the initialization of staging board code from using
late_initcall() to device_initcall() to fix this.
Signed-
This reverts commit d13778d537a0ed6115d2a79a942af999cfb8eec6.
Commit 13c11072536f2613 ("staging:board: remove unnecessary function")
fixed the build of drivers/staging/board/board.c.
Signed-off-by: Geert Uytterhoeven
---
drivers/staging/board/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff -
Add staging board support for the r8a7740-based armadillo800eva board
and add platform devices to allow in-tree continuous development of the
drivers on the armadillo800eva board.
When DT bindings are ready for theses drivers then the platform devices
in the armadillo800eva staging board code can
Hi all,
This RFC patch series adds board staging support for r8a7740/armadillo.
For now this supports only the frame buffer device for the on-board LCD.
The goal is to complete the move to ARM multiplatform kernels for all
shmobile platforms, and drop the existing board files
(arch/arm/mac
As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq
domain."), GIC IRQ numbers are virtual, breaking hardcoded hardware IRQ
numbers in platform device resources.
Translate the hardware IRQ numbers to virtual IRQ numbers to fix this.
Signed-off-by: Geert Uytterhoeven
---
Untested
As of commit 9a1091ef0017c40a ("irqchip: gic: Support hierarchy irq
domain."), GIC IRQ numbers are virtual, breaking hardcoded hardware IRQ
numbers in platform device resources.
Add support for translating hardware IRQ numbers to virtual IRQ numbers,
and fixing up platform device resources with ha
Hyungwon,
Can you re-base your patch set on top of exynos-drm-next-todo?
I merged cleanup series[1] and atomic feature support[2] to
exynos-drm-next-todo for the test so you can re-base your patch set on
top of exynos-drm-next-todo. You would need to modify
exynos5433_drm_decon.c module.
Please
Hi Jacek,
On Wed, Mar 25, 2015 at 09:52:02AM +0100, Jacek Anaszewski wrote:
> Hi Sakari,
>
> On 03/25/2015 02:06 AM, Sakari Ailus wrote:
> >Hi Jacek,
> >
> >On Fri, Mar 20, 2015 at 04:03:29PM +0100, Jacek Anaszewski wrote:
> >>This patch adds a description of 'flashes' property
> >>to the samsung
Hi Jacek,
On Tue, Mar 31, 2015 at 03:52:37PM +0200, Jacek Anaszewski wrote:
> Description of flash LEDs related properties was not precise regarding
> the state of corresponding settings in case a property is missing.
> Add relevant statements.
> Removed is also the requirement making the flash-ma
Hi Pavel,
Thanks for the update.
On Fri, Apr 03, 2015 at 10:33:53AM +0200, Pavel Machek wrote:
>
> We are moving to device tree support on OMAP3, but that currently
> breaks ADP1653 driver. This adds device tree support, plus required
> documentation.
>
> Signed-off-by: Pavel Machek
>
> ---
Hi Pavel,
On Fri, Apr 03, 2015 at 10:23:44AM +0200, Pavel Machek wrote:
> Hi!
>
> > Hi Pawel,
>
> I'm still Pavel. v, not w.
I know too many Pawels. Sorry about that. :-)
>
> > > > Hi Pawel,
>
> > > > A corresponding change to the N900 dts would be very nice.
> > >
> > > Corresponding chang
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