On Mon, May 4, 2015 at 10:49 AM, Johan Hovold jo...@kernel.org wrote:
On Mon, Apr 13, 2015 at 01:05:15PM +0200, Martin Fuzzey wrote:
The above means that, in order to export the GPIO to userspace via
/sys/class/gpio/export the userspace code must know the exact hardware and
kernel version
On Wed, Apr 29, 2015 at 3:13 AM, Andrew Bresticker
abres...@chromium.org wrote:
Add a device-tree binding document for the pin controller present
on the IMG Pistachio SoC.
Signed-off-by: Damien Horsley damien.hors...@imgtec.com
Signed-off-by: Ezequiel Garcia ezequiel.gar...@imgtec.com
Am Mittwoch, 6. Mai 2015, 08:59:28 schrieb Uwe Kleine-König:
Hello,
On Tue, May 05, 2015 at 12:55:13PM +0200, Wolfram Sang wrote:
So what about adding a new property i2c-slave-reg? This does not only
prevent the confusion above, but also makes it very clear that this node
is an I2C slave
On Wed, May 06, 2015 at 05:39:28PM +0530, Laxman Dewangan wrote:
This patch is not available on linux-next. Is it pending for any clean-up?
Ah, sorry - forgot to follow up on this. The patch doesn't apply
against curent code, please check and resend.
signature.asc
Description: Digital
Hi Nikolaus,
On 05/06/2015 01:19 AM, Dr. H. Nikolaus Schaller wrote:
Am 05.05.2015 um 21:54 schrieb Peter Hurley pe...@hurleysoftware.com:
Hi Neil,
On 03/18/2015 01:58 AM, NeilBrown wrote:
here is version 3 of support for tty-slaves.
Is there a v4 of this that I missed?
We did have a
On Wed, May 6, 2015 at 6:55 AM, Linus Walleij linus.wall...@linaro.org wrote:
On Wed, Apr 29, 2015 at 4:20 PM, frank...@freescale.com wrote:
From: Frank Li frank...@freescale.com
Add i.MX7D pinctrl driver support
Signed-off-by: Frank Li frank...@freescale.com
Signed-off-by: Anson Huang
Hi Pavel,
Am 06.05.2015 um 11:27 schrieb Pavel Machek pa...@ucw.cz:
On Wed 2015-05-06 07:19:31, Dr. H. Nikolaus Schaller wrote:
Hi Peter,
Am 05.05.2015 um 21:54 schrieb Peter Hurley pe...@hurleysoftware.com:
Hi Neil,
On 03/18/2015 01:58 AM, NeilBrown wrote:
here is version 3 of
On Wed, May 6, 2015 at 4:14 AM, Gabriel Fernandez
gabriel.fernan...@linaro.org wrote:
Hi Bjorn,
On 6 May 2015 at 00:16, Bjorn Helgaas bhelg...@google.com wrote:
On Fri, Apr 10, 2015 at 11:12:46AM +0200, Gabriel FERNANDEZ wrote:
sti pcie is built around a Synopsis Designware PCIe IP.
On Wed, May 06, 2015 at 04:30:50PM +, Opensource [Steve Twiss] wrote:
On 06 May 2015 17:02 Guenter Roeck wrote:
On Wed, May 06, 2015 at 02:54:37PM +, Opensource [Steve Twiss] wrote:
On 18 April 2015 16:53 Guenter Roeck wrote:
Hi Guenter,
Thanks for your comments.
Allow to specify in the device-tree that no physical write-protect signal
is connected to a particular instance of a MMC controller. Setting the
property will cause the core will assume that the SD card is always
read-write.
The name for the new property is 'disable-wp' and was chosen based on
It is not uncommon to see systems where there is no physical write-protect
signal (e.g. when using eMMC or microSD card slots). For some controllers,
which have a dedicated write-protection detection logic (like SDHCI
controllers), the get_ro() callback can return bogus data in such a case.
Stephen Warren swar...@wwwdotorg.org writes:
On 04/21/2015 12:09 PM, Eric Anholt wrote:
This is my first submission of a Raspberry Pi 2 port. It can be found
at https://github.com/anholt/linux/tree/bcm2836
I'm using the 2835 interrupt controller support, without adding the
checks for ARM
On Fri, Apr 10, 2015 at 11:12:47AM +0200, Gabriel FERNANDEZ wrote:
Call directly pci_*() instead of using pci_common_init_dev().
Enforce error handling in probe.
It also allows st pcie driver not to declare IO space:
pci_common_init_dev() is assigning one by default.
Can you verify that none
Hello Stephen,
On Wed, May 06, 2015 at 09:57:37AM -0600, Stephen Warren wrote:
On 05/06/2015 02:09 AM, Uwe Kleine-König wrote:
On Wed, May 06, 2015 at 09:53:55AM +0200, Marc Dietrich wrote:
Am Mittwoch, 6. Mai 2015, 08:59:28 schrieb Uwe Kleine-König:
On Tue, May 05, 2015 at 12:55:13PM +0200,
On 6 May 2015 at 15:06, Johan Hovold jo...@kernel.org wrote:
On Wed, May 06, 2015 at 09:22:22AM +0200, Linus Walleij wrote:
On Mon, May 4, 2015 at 10:49 AM, Johan Hovold jo...@kernel.org wrote:
On Mon, Apr 13, 2015 at 01:05:15PM +0200, Martin Fuzzey wrote:
The above means that, in
Add compatible string and config structure for Zynq Ultrascale+ MPSoC
Signed-off-by: Harini Katakam hari...@xilinx.com
Reviewed-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Added in v3
---
drivers/net/ethernet/cadence/macb.c |8
1 file changed, 8 insertions(+)
diff --git
Hi Arnd/Borislav/Rob,
v8:
* Change ASM_EDAC_H to __ASM_EDAC_H in file edac.h
* Add WARN_ONCE in stub function atomic_scrub
* Update DTS binding documentation (with only memory controller node)
* Temporary remove L1/L2, L3, and SoC driver code and update memory driver
code
Signed-off-by: Brian Norris computersforpe...@gmail.com
---
.../devicetree/bindings/mtd/brcm,brcmstb-nand.txt | 39 +-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/brcm,brcmstb-nand.txt
On Wed, May 06, 2015 at 02:18:02AM +0100, Ben Hutchings wrote:
On Fri, 2015-05-01 at 09:57 +0900, Simon Horman wrote:
Hi Ben,
thanks for your patch-set.
On Thu, Apr 30, 2015 at 01:31:54PM +0100, Ben Hutchings wrote:
Signed-off-by: Ben Hutchings ben.hutchi...@codethink.co.uk
---
Initial commit for a new SoC family, UniPhier, developed by
Socionext Inc. (formerly, System LSI Business Division of
Panasonic Corporation).
This commit includes a minimal set of components for booting the
kernel, including SMP support.
Signed-off-by: Masahiro Yamada
At Mon, 04 May 2015 17:09:21 +0200,
Arnd Bergmann wrote:
On Monday 04 May 2015 19:42:02 Yoshinori Sato wrote:
+
+ h8intc: intc@0 {
+ compatible = renesas,h8s-intc, renesas,h8300-intc;
+ #interrupt-cells = 1;
+ interrupt-controller;
+ };
The node
On Wed, May 06, 2015 at 10:06:21AM +0200, Heiko Schocher wrote:
This patch add support for the imx6dl based aristainetos2 board
with following configuration:
CPU: Freescale i.MX6DL rev1.1 at 792 MHz
MReset cause: POR
MBoard: aristaitenos2
DRAM: 1 GiB
NAND: 1024 MiB
MMC: FSL_SDHC:
22 matches
Mail list logo
