Hi Geert,
On May 7, 2015, at 10:17 , Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Tue, May 5, 2015 at 6:51 PM, Michal Suchanek hramr...@gmail.com wrote:
On 5 May 2015 at 17:18, Michal Suchanek hramr...@gmail.com wrote:
where is a device tree compiler that can compile an overlay?
The
Oh, and since I forgot to include that earlier, there’s a git tree against
mainline that I update regularly:
https://github.com/pantoniou/linux-beagle-track-mainline/tree/bbb-overlays
Regards
— Pantelis
On May 7, 2015, at 10:17 , Geert Uytterhoeven ge...@linux-m68k.org wrote:
On Tue, May
Noralf Trønnes nor...@tronnes.org writes:
Den 05.05.2015 22:27, skrev Eric Anholt:
From: Lubomir Rintel lkund...@v3.sk
This mailbox driver provides a single mailbox channel to write 32-bit
values to the VPU and get a 32-bit response. The Raspberry Pi
firmware uses this mailbox channel to
On Thu, May 07, 2015 at 10:18:49AM +0200, Paul Bolle wrote:
Just a nit: a license mismatch.
On Wed, 2015-05-06 at 01:37 -0700, Gregory Fong wrote:
--- /dev/null
+++ b/drivers/gpio/gpio-brcmstb.c
+ * This program is free software; you can redistribute it and/or
+ * modify it under the
Hi Lee,
On Thu, 07 May 2015, Lee Jones wrote:
This IP is shared with Watchdog and RTC functionality. Only one of
these IPs can be used at the same time. We use the device-driver
model combined with a DT 'mode' property to enforce this.
Which means my previous assertion in V1 that the IP
On Wed, Apr 15, 2015 at 02:04:00PM +0800, Zhou Wang wrote:
This patchset adds PCIe host support for Hisilicon Soc Hip05. The PCIe hosts
use PCIe IP core from Synopsys. So the driver is based on designware PCIe
driver.
Zhou Wang (3):
PCI: host: designware: support ARM64
PCI: Host: Add
Add initial CoreSight support for the Qualcomm 8x16 chipsets
This patch series add initial set of CoreSight components for the
8x16 chipsets.
Components will not be functional, because of missing clock controller
driver, which is under internal testing.
Patches are based on Enable CoreSight for
